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| Layers(number)||4||6||-
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| Power Plane Layers||2||-4||-
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| Clearence(mils)||4-||6||-
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| Vias hole (mechanical)||0,3||||-
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* If vias smaller than minimum advised size are used, take care to maintain an adeguate number of via when you change layer on for each power signal.<br/>
* PCB heights less than minimum advised can produce PCB heating and mechanical issues
==== PCB Basics Guidelins ====
* Avoid stubs
* Isolate clock and HI-SPEED signal (differential lines i.e.see interface specifications for further details) for at least two times trace width or gap for differential lines
* Avoid voids on planes
* Use Solid Connection for on plane vias
== Interfaces Guidelines ==
This section provides guidelines for the most used interfaces on DAVE's SOMs module. <br/>Please refer to SOM's detailed pages for specific additional information.
=== Ethernet 10/100 ===
====Case #1: PHY is integrated on SOM====
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* If LAN connector with integrated magnetic is used:
** do not route traces under the connettor, neither on opposite side
** place filter diode near connector
** place others signals far from connector.** Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
* If on board magnetic are used
** adeguately isolate system GND from magnetic connector side
** Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
* try to match as best as possible each differential pair (intrapair matching)
* no Keep as best as possibile the same route for TX and RX matching requiredtraces* If less than minimum gap is used, use a GND trace for improve trace separation
==== Case #2: PHY is not integrated on SOM and a RGMII PHY is used ====
This section refers to the case of PHY is not integrated on SOM and a RGMII Gigabit Ethernet PHY is usedsuch as [[Maya SOM|Naon]].
===== Schematics =====
* Add series resistors (RPACK resistors recommended) to RGMII lines
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* Place bypass capacitor near every PHY supply pin
* Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
* Place PHY device at least 1" (25mm) distance far away from connector
* Keep MDIO clock signal isolated from other signals
==== Case #3: PHY is not integrated on SOM and a RMII PHY is used ====
This section refers to the case of PHY is not integrated on SOM and an RMII 10/100 Ethernet PHY is usedsuch as [[Maya SOM|Maya]].
===== Schematics =====
* If possible, place series resistor to RMII interface signals
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* Since RMII signals are not critical such as RGMII, is not necessary a strong matching between lines.signal* Avoid use of long traces
* Avoid stubs
* Keep as best as possibile the same routing for all RMII traces
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| Intra pair matching(mils)||0||25||150
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<br/>
| Max allowed stubs ||-||-||0
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| Max traces length ||-||-||18"note 1
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| Max allowed plane split under traces ||-||-||0
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'''note 1''' see SOM detailed specifications
* If a stub is unavoidable in the design, no stub should be greater than 200 mils.
* Place a continuos reference plane underneath differential pair
| Max allowed plane split under traces ||-||-||0
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| Max allowed length||-||-||6.0" note 1
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'''note 1''' see SOM detailed specifications
* Place a continuos reference plane underneath differential pair
* Minimized vias use
==== Schematics ====
* Please refer to DAVE system-on-modules (SOM) specific documentation
* Predispose series resistor terminator(RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
==== PCB ====
* If possible, use 50ohm common mode lines
* Match as best as possibile LCD parallel lines (signals in accordition with Pixel Clock frequency(further details in SOM specifications)
=== VIN Interface ===
==== Schematics ====
* Please refer to DAVE system-on-modules (SOM) specific documentation
* Predispose series resistor terminator(RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
==== PCB ====
* If possible, use 50ohm common mode lines
* Match as best as possibile VIN parallel lines (signals in accordition with Pixel Clock frequency(further details in SOM specifications)
=== TVOUT ===
==== Schematics ====
| Gap than other signals||2xwidth||-||-
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=== I2C Interface ===
==== Schematics ====
* Please refer to DAVE system-on-modules (SOM) specific documentation
* Predispose properly pullup resistors on line in accordition with DAVE system-on-modules (SOM)
* Do not overload I2C lines with too much devices
* Ensure that I2C devices are properly reset during power up
==== PCB ====
* Isolate I2C clock from noise senitive signals
* Avoid stub