3,260
edits
Changes
no edit summary
| Layers(number)||4||6||-
|-
| Power Plane Layers||2||2-||-
|-
| Clearence(mils)||4||6||-
* If vias smaller than minimum advised size are used, take care to maintain an adeguate number of via when you change layer on each power signal.<br/>
* PCB heights less than minimum advised can produce PCB heating and mechanical issues.* Use Solid Connection for on plane vias
==== PCB Basics Guidelins ====
| Common Mode Impedance||46,75||55||63,25
|-
| Gap between TX and RX lines||2xseparation||4xseparation2xseparation||-
|-
| Gap between other signal||2xseparation||2xseparation4xseparation||-
|-
| Intra pair matching(mils)||-0||24025||-240
|-
| TX and RX via mismatch||0||0||1
|-
| Max PCB trace length ||-||-||3"
|-
|}
* Common differential impedance value is 100ohm
* If LAN connector with integrated magnetic is used:
** do not route traces under the connettor, neither on opposite side
* If on board magnetic are used
** adeguately isolate system GND from magnetic connector side
** Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary* try to match as best as possible each differential pair(intrapair matching)
* no TX and RX matching required
==== Case #2: PHY is not integrated on SOM and a RGMII PHY is used ====
This section refers to the case of PHY is not integrated on SOM and a RGMII Gigabit Ethernet PHY is used.
===== Schematics =====
* Add series resistors (RPACK resistors recommended) to RGMII lines
* Properly decouple PHY Power Supplies rails
* Properly decouple every supply pin of Ethernet PHY
* Properly separate analog Supply Rails
===== PCB =====
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for RGMII interface '''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Common mode impedance(ohm)||-||50||-
|-
| Gap between lines||2xW||-||-
|-
| Gap between other signal||4xW||||-
|-
| Matching(mils)||-||250||-
|-
| Via Mismatch||0||0||1
|-
|}
<br/>
<br/>
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for Gigabit Lines'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||76||95||114
|-
| Common Mode Impedance||46,75||55||63,25
|-
| Gap between TX and RX lines||2xseparation||2xseparation||-
|-
| Gap between other signal||2xseparation||4xseparation||-
|-
| Intra pair matching(mils)||0||10||10
|-
| TX and RX via mismatch||0||0||1
|-
| Max PCB trace length ||-||-||3"
|-
|}
<br/>
* Ground and VCC planes must be as large as possible
* Avoid plane split and voids
* Place bypass capacitor near every PHY supply pin
* Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
* Place PHY device not too near to connector (250 mils reccomended distance)
* Keep MDIO clock signal isolated from other signals
==== Case #3: PHY is not integrated on SOM and a RMII PHY is used ====
This section refers to the case of PHY is not integrated on SOM and an RMII 10/100 Ethernet PHY is used.
===== Schematics =====
* If possible, place series resistor to RMII interface signals
* Properly decouple PHY Power Supplies rails
* Properly separate analog Supply Rails
* Properly decouple every supply pin of Ethernet PHY
* Use a standard RMII PHY that supports correct clock mode (see SOM specification for further details)
===== PCB =====
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for RMII interface '''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Reccomended Common mode impedance(ohm)||-||50||-
|-
| Gap between other signal||2xW||||-
|-
|}
* Since RMII signals are not critical such as RGMII, is not necessary a strong matching between lines.
* Avoid signal traces too long
* Avoid stubs
<br/>
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for Ethernet Lines'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||76||95||114
|-
| Common Mode Impedance||46,75||55||63,25
|-
| Gap between TX and RX lines||2xseparation||2xseparation||-
|-
| Gap between other signal||2xseparation||4xseparation||-
|-
| Intra pair matching(mils)||0||25||240
|-
| TX and RX via mismatch||0||0||1
|-
| Max PCB trace length ||-||-||3"
|-
|}
<br/>
* Ground and VCC planes must be as large as possible
* Avoid plane split and voids
* Place bypass capacitor near every PHY supply pin
* Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
* Place PHY device not too near to connector (250 mils reccomended distance)
* Keep MDIO clock signal isolated from other signals