View source for Carrier board design guidelines (SOM)

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<section begin=Body/>
==Carrier board design guidelines==
This page provides useful information and resources to system designers in order to design carrier boards hosting '''DAVE Embedded Systems''' system-on-modules (SOM).

These guidelines are provided with the goal to help designers to design compliant systems with '''DAVE Embedded Systems''' modules and they cover schematics and PCB aspects. They apply to several products that are listed on the top right corner of this page (see "Applies to" boxes).

=== Basic guidelines === 
In this section basic hardware guidelines valid for all '''DAVE Embedded Systems''' SOMs are detailed.
==== Schematics ====
* Check mirroring and pinout of '''DAVE Embedded Systems''' system-on-modules (SOM) connector
* Properly decouple '''DAVE Embedded Systems''' system-on-modules (SOM) power supply with large bulk capacitor and small bypass capacitor
* Use low-ESR X7R capacitor if possible
* Check for correct connection of TX and RX lines
* Add series resistors as interface needs (see interface details)
==== PCB ====
===== PCB Tecnology =====
Use a PCB technology as advised in the following table
{| class="wikitable" border="1" 
| align="center" style="background:#f0f0f0;"|'''Parameter'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Layers(number)||4||6||-
|-
| Power Plane Layers||2||4||-
|-
| Clearence(mils)||-||6||-
|-
| Trace Width(mils)||-||6||-
|-
| Vias hole (mechanical)||0,3||||-
|-
| Minimum number of via for each power signal layer changes||2||3||-
|-
| Minimum number of via for each power signal SOM connector pin||1||2||-
|-
| Component package size||-||0603||-
|-
| PCB Height(mm)||1,4||1,6||-
|- 
|}

* If vias smaller than minimum advised size are used, take care to maintain an adeguate number of via when you change layer for each power signal.<br/>
* PCB heights less than minimum advised can produce PCB heating and mechanical issues

===== PCB Basics Guidelines =====
* Avoid stubs
* Isolate clock and HI-SPEED signal (see interface specifications for further details)
* Avoid voids on planes
* Use Solid Connection for on plane vias
* Place bulk and ByPass capacitor near '''DAVE Embedded Systems''' system-on-modules (SOM) power supply pins
* Place series terminator resistor near the related transmitter

==== SOM Connectors ====

This section provides information and suggestions regarding the SOM mating connectors.

===== SO-DIMM =====

SO-DIMM mating connectors from different vendors may have slight differences in mechanical characteristics. One critical point is the position of the end of the mating area (please see the picture below), that can be slightly shifted inwards or outwards in respect to the retention holes on the carrier board. This can lead to a misalignment with the holes on the SO-DIMM modules, making difficult or impossible to insert the retentions screws or locking supports.

[[File:So-dimm-mating.png|250px]]

If you plan to use the holes as additional retention system, we recommend to pay attention to the mechanical characteristics when evaluating the SO-DIMM mating connectors to be mounted on the carrier board.

=== Power-up sequence ===
In order to prevent back powering effects, DAVE Embedded Systems' SOMs provide the signals required to handle power-up sequence properly. For instance, see the recommended sequence for the BORA SOM [[BORA_SOM/BORA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence|here]].

In case the power-up sequence is not managed properly, the circuitry populating the SOM '''may be damaged'''.

=== Interfaces Guidelines ===
This section provides guidelines for the most used interfaces on '''DAVE Embedded Systems''' SOMs module. <br/>
Please refer to SOM's detailed pages for specific additional information. 
==== Ethernet 10/100/1000 ====
=====Case #1: PHY is integrated on SOM=====
This section refers to the case of PHY integrated on SOM such as [[:Category:Lizard|Lizard]] and [[:Category:Maya|MAYA]].
====== Schematics ======
* If LAN connector with integrated magnetic is used:
** predispose ethernet protection diodes on ethernet lines
** Connect connector shield to an adeguate GND or shield Plane
====== PCB ======
'''Refer to this table for 10/100 differential pairs routing'''<br/>
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for 10/100 differential pair'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||-||100||-
|-
| Common Mode Impedance||-||50||-
|-
| Gap than TX and RX signals ||2xgap||2xgap||-
|-
| Gap than other signals ||2xgap||4xgap||-
|-
| Intra pair matching(mils)*||0||25||150
|-
| TX and RX via # mismatch*||0||0||1
|- 
|}

'''Refer to this table for Gigabit differential pairs routing''' <br/>
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for Gigabit Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||-||100||-
|-
| Common Mode Impedance||-||50||-
|-
| Gap than TX and RX signals ||2xgap||2xgap||-
|-
| Gap than other signals ||2xgap||4xgap||-
|-
| Intra pair matching(mils)*||0||10||10
|-
| Max PCB trace length ||3"||5"||-
|-
| TX and RX via # mismatch*||0||0||1
|-
|}
<br/>
<nowiki>*</nowiki> Not mandatory but recommended.
* If LAN connector with integrated magnetic is used:
** do not route traces under the connettor, neither on opposite side
** place filter diode near connector
** place others signals far from connector
** Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias
* If on board magnetic are used
** adeguately isolate system GND from magnetic connector side
** Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
* try to match as best as possible each differential pair (intrapair matching)
* Keep as best as possibile the same route for TX and RX traces
* If less than minimum gap is used, use a GND trace for improve trace separation

===== Case #2: PHY is not integrated on SOM and a RGMII PHY is used =====
This section refers to the case of:
* PHY not integrated on SOM 
* Gigabit PHY populated on carrier board and connected to SOM through RGMII interface.
This solution is implemented on [[NaonEVB-Mid]] for example.
====== Schematics ======
* Add series resistors (RPACK resistors recommended) to RGMII lines
* Properly decouple PHY Power Supplies rails
* Properly decouple every supply pin of Ethernet PHY
* Properly separate analog Supply Rails
====== PCB ======
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for RGMII interface    '''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Common mode impedance(ohm)||-||50||-
|-
| Gap than other ethernet diff pair ||4xwidth||-||-
|-
| Gap than other signals ||4xwidth||||-
|-
| Matching(mils)||-||-||200
|- 
| Via Mismatch||0||0||1
|-
|}
<br/>
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for Gigabit Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||-||100||-
|-
| Common Mode Impedance||-||50||-
|-
| Gap than TX and RX signals ||2xgap||2xgap||-
|-
| Gap than other signals ||2xgap||4xgap||-
|-
| Intra pair matching(mils)||0||10||10
|-
| Max PCB trace length ||3"||5"||-
|- 
| TX and RX via # mismatch*||0||0||1
|- 
|}
<nowiki>*</nowiki> Not mandatory but recommended.
<br/>
* Ground and VCC planes must be as large as possible
* Avoid plane split and voids
* Place bypass capacitor near every PHY supply pin
* Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
* Place PHY device at least 1" (25mm) distance far away from connector
* Keep MDIO clock signal isolated from other signals

===== Case #3: PHY is not integrated on SOM and a RMII PHY is used =====
This section refers to the case of
* PHY not integrated on SOM 
* 10/100 Ethernet PHY populate don carrier board and interfaced to SOM through RMII interface.
This solution is implemented for example in [[MayaEVB-Lite]] board.
====== Schematics ======
* If possible, place series resistor to RMII interface signals
* Properly decouple PHY Power Supplies rails
* Properly separate analog Supply Rails
* Properly decouple every supply pin of Ethernet PHY
* Use a standard RMII PHY that supports correct clock mode (see SOM specification for further details)
====== PCB ======
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for RMII interface    '''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Reccomended Common mode impedance(ohm)||-||50||-
|-
| Gap between other signal||2xW||||-
|-
|}
* Since RMII signals are not critical such as RGMII, is not necessary a strong matching between signal
* Avoid use of long traces
* Avoid stubs
* Keep as best as possibile the same routing for all RMII traces
<br/>
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for Ethernet Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||-||100||-
|-
| Common Mode Impedance||-||50||-
|-
| Gap than other TX and RX signals ||2xgap||2xgap||-
|-
| Gap than other signals ||2xgap||4xgap||-
|-
| Intra pair matching(mils)*||0||25||150
|- 
| TX and RX via # mismatch*||0||0||1
|- 
|}
<nowiki>*</nowiki> Not mandatory but recommended.
<br/>
* Ground and VCC planes must be as large as possible
* Avoid plane split and voids
* Place bypass capacitor near every PHY supply pin
* Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
* Place PHY device at least 1" (25mm) distance far away connector
* Keep MDIO clock signal isolated from other signals
<br/>

==== USB ====
===== Schematics =====
* Create schematic in accordance with '''DAVE Embedded Systems''' system-on-modules (SOM) USB specification ( see SOM detailed pages )
===== PCB =====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for USB Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||80||90||100
|-
| Common Mode Impedance||40,5||45||49.5
|-
| Gap than other signals||3xgap||5xgap||-
|-
| Intra pair matching(mils)||0||25||150
|-
| Max allowed stubs ||-||-||0
|-
| Max traces length ||-||-||note 1
|-
| Max allowed plane split under traces ||-||-||0
|-  
|}
'''note 1''' see SOM detailed specifications
* If a stub is unavoidable in the design, no stub should be greater than 200 mils.
* Place a continuos reference plane underneath differential pair
==== HDMI ====
===== Schematics =====
* Add a Transmitter Port Protection to HDMI lines
* Use certified HDMI connector
* Connector shield must be properly connected
===== PCB =====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for HDMI Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||85||100||115
|-
| Gap than other signals||3xgap||5xgap||-
|-
| Intra pair matching(mils) at 225MHz clock||0||20||250
|-
| Inter pair matching(mils) at 225MHz clock||0||250||1"
|-
| Max allowed stubs ||-||-||0
|-
| Max allowed plane split under traces ||-||-||0
|-  
|}
* Place a continuos reference plane underneath differential pair
* Try to match lines as best as possible
==== SATA ====
===== Schematics =====
* Use certified SATA connector
===== PCB =====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for SATA Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance(ohm)||80||100||120
|-
| Common Mode Impedance(ohm)||51||60||69
|-
| Gap than other signals||2xgap||-||-
|-
| Intra pair matching(mils||-||-||note 1 
|-
| Inter pair matching(mils)||-||-||note 1 
|-
| Max allowed stubs ||-||-||0
|-
| Max allowed plane split under traces ||-||-||0
|-
| Max allowed length||-||-||note 1  
|}
'''note 1''' see SOM detailed specifications
* Place a continuos reference plane underneath differential pair
* Minimized vias use
* No strong matching required between TX and RX, but keep same route for every differential pair

==== PCI Express ====

===== PCB =====

{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for PCI Express Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance [Ohm]||-||100||-
|-
| Common Mode Impedance [Ohm]||-||60||-
|-
| Gap than other signals (reccomended)||-||2xgap||-
|-
| Intra pair matching [mils]*||-||-||10
|-
| Max Total Length [in]*||-||-||12
|-
| Maximum allowed stub||-||-||0
|-
| Max allowed vias||-||-||6
|}

* * Including SoM trace length
* Preferred underneath plane over entire trace length GND.

==== LVDS ====

===== PCB =====

{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for LVDS Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance [Ohm]||85||100||115
|-
| Common Mode Impedance [Ohm]||46.75||55||63.25
|-
| Gap than other signals (reccomended)||-||2xgap||-
|-
| Intra pair skew [mils]*||-||-||5
|-
| Inter pair skew [mils]**||-||400||-
|-
| Maximum allowed stub||-||-||0
|-
|}

* Prefer to route traces on TOP layer, referring them to a continuos GND plane.
* * Not includes SOM's length. 
* ** Typical value can be relaxed depending on LVDS clock frequency

==== LCD Interface ====
===== Schematics =====
* Please refer to '''DAVE Embedded Systems''' system-on-modules (SOM) carrier board documentationfor further information
* Predispose series resistor terminator (RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
* Series resistor value may vary depending by PCB and schematic

===== PCB =====
* If possible, use 50ohm common mode lines
* Match LCD parallel signals in accordance with Pixel Clock frequency (further details in SOM specifications)
* Avoid use of long traces connection (max 10" on PCB)
* Avoid stubs
==== VIN Interface ====
===== Schematics =====
* Please refer to '''DAVE Embedded Systems''' system-on-modules (SOM) carrier board documentation for further information
* Predispose series resistor terminator (RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
* Series resistor value may vary depending PCB and schematic
===== PCB =====
* If possible, use 50ohm common mode lines
* Match VIN parallel signals in accordance with Pixel Clock frequency (further details in SOM specifications)
* Avoid use of long traces connection (max 10" on PCB)
* Avoid stubs
==== TVOUT ====
===== Schematics =====
* Please refer to '''DAVE Embedded Systems''' system-on-modules (SOM) carrier board documentation for further information 
===== PCB =====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for SATA Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Common Mode Impedance(ohm)||-||75||-
|-
| Gap than other signals||2xwidth||-||-
|}
* Keep analog TVOUT signal far from noise signals
==== I2C Interface ====
===== Schematics =====
* Predispose properly pullup resistors on line in accordance with '''DAVE Embedded Systems''' system-on-modules (SOM)
* Do not overload I2C lines with too much devices
* Ensure that I2C devices are being properly initialized during power up
===== PCB =====
* Isolate I2C clock from noise sensitive signals
* Avoid stub
==== SD/MMC Interface ====

{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''     '''
| align="center" style="background:#f0f0f0;"|''' Min '''
| align="center" style="background:#f0f0f0;"|''' Typ '''
| align="center" style="background:#f0f0f0;"|''' Max '''
|- 
| Common Mode impedance SOM(ohm)||align="center"|-||align="center"|50||align="center"|60
|- 
| Matching required*||align="center"|-||align="center"|-||align="center"|-
|-
| Max allowed parallel routing(mils)||align="center"|-||align="center"|-||align="center"|1000
|-
| Max trace Length**||align="center"|-||align="center"|-||align="center"|-
|-
| Max # of vias allowed||align="center"|-||align="center"|-||align="center"|-
|-
|}
<nowiki>*</nowiki>This is not mandatory, however it is suggested in case trace length exceeds 10cm

<nowiki>**</nowiki>Overall trace length - i.e. Bora + carrier board - should not exceed 10cm. If this is not possible, try to avoid parallel routing in order to reduce crosstalk, and refer them to a ground plane.

==== CAN Interface ====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''     '''
| align="center" style="background:#f0f0f0;"|''' Min '''
| align="center" style="background:#f0f0f0;"|''' Typ '''
| align="center" style="background:#f0f0f0;"|''' Max '''
|-
| Differential Mode impedance(ohm)||align="center"|108||align="center"|120||align="center"|132
|-
| Matching required||align="center"|-||align="center"|-||align="center"|-
|-
| Min Interpair spacing||align="center"|-||align="center"|4xgap||align="center"|-
|-
| Max allowed parallel routing(mils)||align="center"|-||align="center"|-||align="center"|-
|-
| Max trace Length||align="center"|-||align="center"|-||align="center"|-
|-
| Max via allowed||align="center"|-||align="center"|-||align="center"|-
|-
|}

===Functional guidelines===
====Sudden power off management====
From the architectural standpoint, modern embedded systems often resemble traditional PCs. For example:
* they implement a rich set of I/O interfaces (large displays, Ethernet ports, USB ports, SDIO sockets etc.)
* they likely run complex operating systems that derive from desktop world (linux, Android, Windows CE etc.)
* they implement complex storage schemes (raw NAND, SSD, eMMC etc.).
One of the main difference between such systems and PCs is that the formers are - if appropriately designed - inherently resilient to sudden power fails.
In any case, system designer should take into account these events and decide if and how manage them explicitly. Here are some typical techniques used to deal with this situation:
* in case the system is used by human operators, the use of clean shutdown - triggered by the user himself - should be encouraged to prevent sudden power off. Technically speaking, this can be done via GUI (soft button) or mechanical device (push buttons and alike). In the latter case, push button controllers such as [http://www.linear.com/product/LTC2954 Linear LTC2954] can be very useful to implement this feature
* in case no human operators interact with the system, more complex solutions might be required. This strategy is strongly dependent on hardware characteristics of SOM and must be approached on a case-by-case basis.

===Thermal Management===

Heat is generated by all semiconductors while operating and it is dissipated into the surrounding environment. This amount of heat is a function of the power consumed and the thermal resistance of the device package. Every silicon device on an electronic board must work within the limits of its operating temperature parameters (eg, the junction temperature) as specified by the silicon vendor.

Failure to maintain the temperature within safe ranges reduces operating lifetime, reliability, and performances and may cause irreversible damage to the system. Therefore, the product design cycle should include thermal analysis to verify that the device works within its functional limits. If the temperature is too high, component or system-level thermal enhancements are required to dissipate the heat from the system. 

For detailed information, please refer to the following documents:

* [[Thermal management (Naon)]]
* [http://processors.wiki.ti.com/index.php/AM335x_Thermal_Considerations AM335x Thermal Considerations]
<section end=Body/>