Difference between revisions of "Bora Embedded Linux Kit (BELK)"

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{{Applies To Bora}}
 
{{Applies To Bora}}
 
{{InfoBoxBottom}}
 
{{InfoBoxBottom}}
 +
 +
{{ImportantMessage|text='''For BELK 3.0.2 or older, the boot process was based on the FSBL+second-stage bootloader (U-Boot) combination. From BELK 4.0.0 on, the boot process is based on the first-stage bootloader (U-Boot SPL)+second-stage bootloader (U-Boot) combination.'''
 +
}}
 +
  
 
==Introduction==
 
==Introduction==
Line 8: Line 12:
  
 
Bora Embedded Linux Kit (BELK for short) provides all the necessary components required to set up the developing environment for:
 
Bora Embedded Linux Kit (BELK for short) provides all the necessary components required to set up the developing environment for:
* configuring the system (PS and PL) at hardware level
+
* building the first-stage bootloader:
* build the first-stage bootloader (FSBL)
+
** FSBL for BELK 3.0.2 or older
* building the second stage bootloader (U-Boot)
+
** U-boot SPL for BELK 4.0.0 or newer
 +
* building the second-stage bootloader (U-Boot)
 
* building and running Linux operating system on Bora-based systems
 
* building and running Linux operating system on Bora-based systems
* building Linux applications that will run on the target
+
* building Linux applications that will run on the target.
 
 
'''DAVE Embedded Systems''' provides all the customization required (in particular at bootloader and Linux kernel levels) to enable customers use the standard Zynq-7000 development tools for building all the firmware/software components that will run on the target system.
 
  
 +
'''DAVE Embedded Systems''' provides all the customization required (in particular at bootloader and Linux kernel levels) to enable customers to use the standard Zynq-7000 development tools for building all the firmware/software components that will run on the target system.
  
==Logical structure of Bora Embedded Linux Kit (BELK)==
+
==Kit content==
To understand the structure of BELK, it is necessary to describe the basic organization of Xilinx Vivado Design Suite/Xilinx SDK and to recall briefly the recent history of development tools provided by Xilinx.
 
  
===A little bit of history===
+
{| class="wikitable" style="margin: auto;"
At the time of this writing (October 2013) Xilinx is migrating from mature ISE 14.x Design Suite - that should be the last series of this suite - to the new Vivado environment. Both are composed by several programs and some of these are in common. From the general standpoint, the main difference between ISE and Vivado - even if ISE does support Zynq - is that the latter has been expressively conceived to support newer SoC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as the default environment for BELK would seem the natural choice. However, the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suite. Plus Vivado is still a little bit "green" and several bug fixes and improvements are introduced by every new release.
 
 
 
Since Bora was presented in 2013 and because this product addresses long longevity markets such as industrial and biomedical, '''DAVE Embedded Systems''' chose to build BELK upon Vivado that undoubtedly represents today the future of Xilinx development environments.
 
 
 
===Structure of BELK reference designs===
 
 
 
The typical linux-based Zynq design is composed by the following parts:
 
* FSBL
 
* U-Boot
 
* device tree file
 
* Linux kernel
 
* Root file system
 
* Executable image of core #1 (in case of AMP systems)
 
* FPGA bitstream.
 
 
 
Generally speaking, these parts - in the binary/sinthesized form - are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However in real world products, this may be too rigid because developers may want to handle these parts separately and independently.
 
 
 
 
 
===Basic structure of Vivado Design Suite and integration into BELK===
 
Vivado/SDK (1) can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA-related tools such as Floorplanner and pure-software development tools such as SDK.
 
The ambitious objective is to provide a complete, user friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities (2). As usual this ease of use comes at the expence of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason BELK has been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to '''push the modularization and the maintainability of the projects to the maximum possible extent'''.
 
 
 
The following pictures are retrieved from BELK Quick Start Guide and shows respectively the Vivado/SDK default development flow and how this has been integrated in the BELK infrastructure.
 
 
 
[[File:Belk-vivado-sdk-development-flow.png|thumbnail|center|300px|Vivado/SDK development flow]]
 
[[File:Belk-vivado-sdk-integration.png|thumbnail|center|300px|Vivado/SDK integration into BELK]]
 
 
 
 
 
(1) The Software Development Kit (SDK) is the Xilinx Integrated Design Environment for creating embedded applications on Zynq™-7000 All Programmable SoCs. SDK is the first application IDE to deliver true homogenous and heterogenous multi-processor design and debug, it is optionally included with the Vivado Design Suite or ISE Design Suite, or available as a separate free download for application developers.
 
 
 
(2) Nevertheless FPGA developers will find all the traditional tools that allow complete control of FPGA fabric.
 
 
 
==Kit Contents==
 
 
 
{| class="wikitable"  
 
 
|-
 
|-
 
!Component
 
!Component
Line 61: Line 29:
 
!Notes
 
!Notes
 
|-
 
|-
|style="text-align: center;" | [[File:Bora5-small.jpg|60px]]
+
| style="text-align: center;" | [[File:Bora5-small.jpg|60px]]
|[[Bora_SOM | Bora SOM]]<br>CPU: Xilinx Zynx 7000
+
|[[:Category:Bora|Bora]] SOM (p/n DBRF5110C1R)
|Please refer to [[Hardware Manual (Bora) | Bora Hardware Manual]]
+
*SoC: Xilinx XC7Z030 (866Mhz, Speed "-3", Tj 0-100°C)
 +
*SDRAM: 1 GB DDR3
 +
*NOR: bootable SPI flash 16 MB
 +
*NAND: 1GB (SLC)
 +
|
 +
* For more details, please refer to the[[Hardware Manual (Bora) | Bora Hardware Manual]]
 +
* By default, ARM cores frequency is set to 667 MHz and the [[Creating and building example Vivado project (BELK/BXELK)|example Vivado project]] is implemented for a "-1" device. This choice makes the software released with the kit compatible with possible variants based on different SoM models. In this regard, see also the [[#Order codes|order codes section]].
 
|-
 
|-
|style="text-align: center;" | [[File:Boraevb-02.png|80px]]
+
| style="text-align: center;" | [[File:Boraevb-02.png|80px]]
|BoraEVB Carrier board
+
|BORA Carrier board
|Please refer to [[BoraEVB | BoraEVB]] page
+
|Se also the[[BoraEVB | BoraEVB]] page
 
|-
 
|-
|style="text-align: center;" | [[File:Alimentatore.jpg|40px]]
+
| style="text-align: center;" | [[File:Alimentatore.jpg|40px]]
 
|AC/DC Single Output Wall Mount adapter<br>Output: +12V – 2.0 A
 
|AC/DC Single Output Wall Mount adapter<br>Output: +12V – 2.0 A
 
|Please refer to Belk Quick Start Guide
 
|Please refer to Belk Quick Start Guide
 
|-
 
|-
|style="text-align: center;" | [[File:ProdSDC-MBLY-thumb.png|50px]]
+
| style="text-align: center;" | [[File:ProdSDC-MBLY-thumb.png|50px]]
 
|MicroSDHC card with SD adapter and USB adapter
 
|MicroSDHC card with SD adapter and USB adapter
 
|Please refer to Belk Quick Start Guide
 
|Please refer to Belk Quick Start Guide
Line 79: Line 53:
 
|}
 
|}
  
 
+
===Order codes===
== BELK software components ==
+
{| class="wikitable" style="margin: auto;"
 
+
|+
'''DAVE Embedded Systems''' adds to the latest Linux BSP from Xilinx the customization required to support the Bora platform, in particular at bootloader and linux kernel levels.
+
!Order code
 
 
The following table reports the XELK releases information.
 
{| class="wikitable"
 
!
 
!colspan="5" | BELK version
 
|-
 
|Release number
 
|1.0.0
 
|1.1.0
 
|2.0.0
 
|2.1.0
 
|2.2.0
 
|-
 
|Status
 
|Released
 
|Released
 
|Released
 
|Released
 
|Released
 
|-
 
|Release date
 
|July 2013
 
|November 2013
 
|May 2014
 
|August 2014
 
|September 2015
 
|-
 
|'''Release notes'''
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 1.0.0 | Ver 1.0.0]]
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 1.1.0 | Ver 1.1.0]]
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 2.0.0 | Ver 2.0.0]]
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 2.1.0 | Ver 2.1.0]]
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK 2.2.0 | Ver 2.2.0]]
 
|-
 
|SOM PCB version
 
|CS020313A
 
|CS020313A
 
|CS020313B
 
|CS020313B
 
|CS020313B
 
|--
 
|Supported carrier boards
 
|[[BoraEVB-Lite]]
 
|[[BoraEVB-Lite]]
 
|[[BoraEVB]]
 
|[[BoraEVB]]
 
|[[BoraEVB]]
 
|-
 
|U-Boot version
 
|2013.04-belk-1.0.0
 
|2013.04-belk-1.1.0
 
|2013.04-belk-2.0.0
 
|2013.04-belk-2.1.0
 
|2014.07-belk-2.2.0
 
|-
 
|Linux version
 
|3.9.0-bora-1.0.0
 
|3.9.0-bora-1.1.0
 
|3.9.0-bora-2.0.0
 
|3.9.0-bora-2.1.0
 
|3.17.0-bora-2.2.0
 
|-
 
|Drivers
 
|valign="top" | -
 
|valign="top" | -
 
|valign="top" | Gigabit Eth #0<br>UART<br>NOR<br>NAND<br>SD/MMC<br>USB Host/Device<br>RTC<br>CAN<br>I2C
 
|valign="top" | Gigabit Eth #0<br>UART<br>NOR<br>NAND<br>SD/MMC<br>USB Host/Device<br>RTC<br>CAN<br>I2C
 
|valign="top" | Gigabit Eth #0<br>UART<br>NOR<br>NAND<br>SD/MMC<br>USB Host/Device<br>RTC<br>CAN<br>I2C<br>[[ConfigID_and_UniqueID | ConfigID]]
 
|-
 
|Vivado version
 
|valign="top" | 2013.2
 
|valign="top" | 2013.3
 
|valign="top" | 2013.3
 
|valign="top" | 2013.3
 
|valign="top" | 2014.4
 
|-
 
|Build System
 
|valign="top" | -
 
|valign="top" | -
 
|valign="top" | -
 
|valign="top" | Yocto Daisy (1.6)
 
|valign="top" | Yocto Daisy (1.6)
 
|-
 
|}
 
 
 
 
 
=== How to update BELK ===
 
 
 
{{ImportantMessage|text=It's recommended to use the latest available BELK version. Please refer to [[Bora_Embedded_Linux_Kit_(BELK)#Release_notes | Release notes]] for further information.}}
 
 
 
==== Updating git repositories ====
 
 
 
In BELK, the following source trees are clones of '''DAVE Embedded Systems''' public git repositories:
 
 
 
{| class="wikitable"  
 
|-
 
!| Component
 
!GIT Remote
 
|-
 
|Vivado project
 
|git@git.dave.eu:dave/bora/bora.git
 
|-
 
|Linux
 
|git@git.dave.eu:dave/bora/linux-xlnx.git
 
|-
 
|U-Boot
 
|git@git.dave.eu:dave/bora/u-boot-xlnx.git
 
|-
 
|}
 
 
 
This means that these components can be kept in sync and up to date with '''DAVE Embedded Systems''' repositories.
 
 
 
==== RSA key generation ====
 
 
 
Please follow the procedure reported below to generate the RSA ssh key:
 
 
 
* select your username (ad es. username@myhost.com)
 
* start your Linux development server machine
 
* start a shell session
 
* make sure the '''ssh''' client components are installed
 
* enter the .ssh subdirectory into your home directory: <code>cd ~/.ssh/</code>
 
* launch the following command: <br><pre>ssh-keygen -t rsa -C "username@myhost.com" -f username@myhost.com</pre>
 
* this command creates the files <code>~/.ssh/username@myhost.com</code> ('''private key''') and <code>~/.ssh/username@myhost.com.pub</code> ('''public key''')
 
* edit your <code>~/.ssh/config</code> adding the following lines:
 
 
 
<pre>
 
Host git.dave.eu
 
    User git
 
    Hostname git.dave.eu
 
    PreferredAuthentications publickey
 
    IdentityFile ~/.ssh/username@myhost.com
 
</pre>
 
 
 
Please send the public key file to the following email support addresses:
 
 
 
* [mailto:support-bora@dave.eu support-bora@dave.eu]
 
 
 
with the request for the creation of a new public git account associated to your username. The support team will enable the account and send you a confirmation as soon as possible.
 
 
 
==== Updating the repositories from BELK 2.1.0 to BELK 2.2.0 ====
 
 
 
{{ImportantMessage|text=To '''update the repositories from BELK 2.1.0 to BELK 2.2.0''', the following commands should be used:}}
 
 
 
<pre>
 
git fetch origin
 
git checkout -b <new_branch_name> origin/bora
 
</pre>
 
 
 
==== Synchronizing the repositories ====
 
 
 
When the account is enabled, you can synchronize a source tree entering the repository directory and launching the <code>git fetch</code> command. Please note that <code>git fetch</code> doesn't merge the commits on the current branch. To do that, you should run the <code>git merge</code> command or replace the ''fetch-merge'' process with a single <code>git pull</code> command. Please note that the recommended method is the ''fetch-merge'' process. For further information on Git, please refer to [http://git-scm.com/documentation Git Documentation].
 
 
 
=== Release notes ===
 
 
 
==== BELK 2.2.0 ====
 
 
 
Updates:
 
# Switched to Vivado 2014.4
 
# Added “board part” for the BORA SOM, which includes all the settings of the Zynq PS for BORA, allowing users to manage projects from the Vivado GUI (and not only using the CLI).
 
# Added [[ConfigID_and_UniqueID | ConfigID]]
 
# Updated U-Boot and Linux versions
 
 
 
===== Known Limitations =====
 
 
 
{| class="wikitable"  
 
|-
 
!Issue
 
 
!Description
 
!Description
 
|-
 
|-
| Kernel command line
+
|BELK-L-S
| User should remove '''mem=xxx''' from kernel command line to avoid system hang during boot. This is fixed in current u-boot default environment
+
|This code refers to the default configuration detailed above
|-
 
| Yocto ubi-utils command line
 
| Some Yocto ubi-utils command line are in non standard format. For ''ubimkvol'' and ''ubirmvol'' the UBI device must be the last argument (e.g. ubimkvol -m -N belk /dev/ubi0)
 
|-
 
|External DDR3 bank
 
|The DDR3 SDRAM bank on the BoraEVB is not supported in this BELK version.
 
|-
 
|ETH1 interface
 
|The additional Gigabit Ethernet interface (ETH1) is not supported in this BELK version.
 
|-
 
|RTC
 
|Date/time retention is limited to about 4 hours.
 
|-
 
|u-boot default environment
 
|Default u-boot environment has a syntax error on ''sdboot'' command. This is already fixed in <code>bora-next</code> branch, release <code>belk-2.2.1-rc1</code>, available on u-boot repository.
 
 
|-
 
|-
 +
|BELK-L-S-D
 +
|This variant is like BELK-L-S, except the SOM, which is DBRD4110I2R.
 
|}
 
|}
  
==== BELK 2.1.0 ====
+
==Logical structure of Bora Embedded Linux Kit (BELK)==
 +
Please refer to [[Logical_structure_of_Bora_and_BoraX_Embedded_Linux_Kits_(BELK/BXELK)|this page]].
  
Updates:
+
== BELK software components ==
# Fix and performance improvement on u-boot network interface
+
Please refer to [[BELK/BXELK_software_components|this page]].
# Fix SD card hotplug issue in Linux
 
# First [[Building_the_software_components_via_Yocto_(BELK)|Yocto Daisy (1.6) BSP Release]]
 
 
 
===== Known Limitations =====
 
 
 
{| class="wikitable"
 
|-
 
!Issue
 
!Description
 
|-
 
| ETH0 interface
 
| Primary Gigabit Ethernet Interface (ETH0) is not working correctly at 10Mbps<br>
 
|-
 
| Kernel command line
 
| User should remove '''mem=xxx''' from kernel command line to avoid system hang during boot
 
|-
 
| Yocto ubi-utils command line
 
| Some Yocto ubi-utils command line are in non standard format. For ''ubimkvol'' and ''ubirmvol'' the UBI device must be the last argument (e.g. ubimkvol -m -N belk /dev/ubi0)
 
|-
 
|External DDR3 bank
 
|The DDR3 SDRAM bank on the BoraEVB is not supported in this BELK version.
 
|-
 
|ETH1 interface
 
|The additional Gigabit Ethernet interface (ETH1) is not supported in this BELK version.
 
|-
 
|RTC
 
|Date/time retention is limited to about 4 hours.
 
|-
 
|}
 
 
 
==== BELK 2.0.0 ====
 
 
 
Updates:
 
# Added support for the BoraEVB carrier board
 
# Updated supported drivers list (please refer to [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | BELK_software_components]])
 
 
 
===== Known Limitations =====
 
 
 
The following table reports the known limitations of this BELK release:
 
 
 
{| class="wikitable"
 
|-
 
!Issue
 
!Description
 
|-
 
|External DDR3 bank
 
|The DDR3 SDRAM bank on the BoraEVB is not supported in this BELK version.
 
|-
 
|ETH1 interface
 
|The additional Gigabit Ethernet interface (ETH1) is not supported in this BELK version.
 
|-
 
|RTC
 
|Date/time retention is limited to about 4 hours.
 
|-
 
|}
 
 
 
==== BELK 1.1.0 ====
 
 
 
Updates:
 
# Switched to Vivado 2013.3
 
# Added application note "AMP on Bora"
 
 
 
==== BELK 1.0.0 ====
 
  
First official release
+
==Quick start guide==
 +
Please refer to [[BELK/BXELK_Quick_Start_Guide|this page]].
 +
==Physical devices mapping==
 +
Please refer to [[Physical_devices_mapping_(BELK/BXELK)|this page]].
 +
==Advanced topics==
 +
===Debugging with Eclipse===
 +
Please refer to [[Debugging with Eclipse (MVM)|this page]].
 +
===ConfigID feature===
 +
Please refer to [[ConfigID_management_(BELK/BXELK)|this page]].
  
 
== Related Documents ==
 
== Related Documents ==
Line 346: Line 86:
 
* [[Hardware Manual (Bora) | Bora Hardware Manual]]
 
* [[Hardware Manual (Bora) | Bora Hardware Manual]]
 
* [[BoraEVB-Lite | BoraEVB-Lite]]
 
* [[BoraEVB-Lite | BoraEVB-Lite]]
* [[BoraEVB | BoraEVB]]
+
* [[BoraEVB | BORAEVB]]
* Belk Quick Start Guide (available for BELK kit owners)
+
* [[BELK/BXELK Quick Start Guide]]
* [[Application_Notes_(Bora) | Application Notes]]
+
* [[FAQs_(Bora) | BORA FAQs]]
* [[FAQs_(Bora) | Bora FAQs]]
 

Revision as of 13:20, 15 December 2020

Info Box
Bora5-small.jpg Applies to Bora


200px-Emblem-important.svg.png

For BELK 3.0.2 or older, the boot process was based on the FSBL+second-stage bootloader (U-Boot) combination. From BELK 4.0.0 on, the boot process is based on the first-stage bootloader (U-Boot SPL)+second-stage bootloader (U-Boot) combination.


Introduction[edit | edit source]

Belk 01.png

Bora Embedded Linux Kit (BELK for short) provides all the necessary components required to set up the developing environment for:

  • building the first-stage bootloader:
    • FSBL for BELK 3.0.2 or older
    • U-boot SPL for BELK 4.0.0 or newer
  • building the second-stage bootloader (U-Boot)
  • building and running Linux operating system on Bora-based systems
  • building Linux applications that will run on the target.

DAVE Embedded Systems provides all the customization required (in particular at bootloader and Linux kernel levels) to enable customers to use the standard Zynq-7000 development tools for building all the firmware/software components that will run on the target system.

Kit content[edit | edit source]

Component Description Notes
Bora5-small.jpg Bora SOM (p/n DBRF5110C1R)
  • SoC: Xilinx XC7Z030 (866Mhz, Speed "-3", Tj 0-100°C)
  • SDRAM: 1 GB DDR3
  • NOR: bootable SPI flash 16 MB
  • NAND: 1GB (SLC)
  • For more details, please refer to the Bora Hardware Manual
  • By default, ARM cores frequency is set to 667 MHz and the example Vivado project is implemented for a "-1" device. This choice makes the software released with the kit compatible with possible variants based on different SoM models. In this regard, see also the order codes section.
Boraevb-02.png BORA Carrier board Se also the BoraEVB page
Alimentatore.jpg AC/DC Single Output Wall Mount adapter
Output: +12V – 2.0 A
Please refer to Belk Quick Start Guide
ProdSDC-MBLY-thumb.png MicroSDHC card with SD adapter and USB adapter Please refer to Belk Quick Start Guide

Order codes[edit | edit source]

Order code Description
BELK-L-S This code refers to the default configuration detailed above
BELK-L-S-D This variant is like BELK-L-S, except the SOM, which is DBRD4110I2R.

Logical structure of Bora Embedded Linux Kit (BELK)[edit | edit source]

Please refer to this page.

BELK software components[edit | edit source]

Please refer to this page.

Quick start guide[edit | edit source]

Please refer to this page.

Physical devices mapping[edit | edit source]

Please refer to this page.

Advanced topics[edit | edit source]

Debugging with Eclipse[edit | edit source]

Please refer to this page.

ConfigID feature[edit | edit source]

Please refer to this page.

Related Documents[edit | edit source]