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BoraXEVB

7,364 bytes added, 09:13, 21 February 2020
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{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
|-
| rowspan="2" |Bora Lite
|style="text-align: center;" | 7007S/7010(CLG400 package)| style="text-align: center;" |HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" |User defined
|-
|style="text-align: center;" | 7014S/7020(CLG400 package)| style="text-align: center;" |HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" |User defined
|}
[1]
==SoM's signals mapping==
===Bora Lite===
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routingfor PL banks. Here '''it is assumed to use an adapter with default mounting options'''.
{| class="wikitable"
!Note
|-
| rowspan="5054" |34| rowspan="2" |IO_0_34| rowspan="2" |'''IO_0_VRN_34'''|J31.2|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27D.H2|FMC conn.|-| rowspan="2" |IO_25_34|rowspan="2" |'''IO_25_VRP_35'''|J31.4|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27B.D1|FMC conn.|-|IO_L10N_T1_34|IO_L10N_T1_34|J27D.H26|FMC conn.
|
|
|
|-
|IO_25_34IO_L10P_T1_34|IO_L10P_T1_34|J27D.H25|FMC conn.
|
|
|
|-
|IO_L11N_T1_SRCC_34
|IO_L11N_T1_SRCC_34
|J27D.G3
|FMC conn.
|
|
|
|-
|IO_L10N_T1_34IO_L11P_T1_SRCC_34|IO_L11P_T1_SRCC_34|J27D.G2|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_34
|IO_L12N_T1_MRCC_34
|J27D.H5
|FMC conn.
|
|
|
|-
|IO_L10P_T1_34IO_L12P_T1_MRCC_34|IO_L12P_T1_MRCC_34|J27D.H4|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_34
|'''IO_L13N_T1_MRCC_34'''
|J27D.G7
|FMC conn.
|
|
|
|-
|IO_L11N_T1_SRCC_34IO_L13P_T2_MRCC_34|'''IO_L13P_T1_MRCC_34'''|J27D.G6|FMC conn.
|
|
|
|-
|IO_L14N_T2_SRCC_34
|IO_L14N_T2_SRCC_34
|J27B.D9
|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_34IO_L14P_T2_SRCC_34|IO_L14P_T2_SRCC_34|J27B.D8|FMC conn.
|
|
|
|-
|IO_L15N_T2_DQS_34
|IO_L15N_T2_DQS_34
|J27B.D21
|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_34IO_L15P_T2_DQS_34|IO_L15P_T2_DQS_34|J27B.D20|FMC conn.
|
|
|
|-
|IO_L16N_T2_34
|IO_L16N_T2_34
|J27B.C23
|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_34IO_L16P_T2_34|IO_L16P_T2_34|J27B.C22|FMC conn.
|
|
|
|-
|IO_L17N_T2_34
|IO_L17N_T2_34
|J27D.G22
|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_34IO_L17P_T2_34|IO_L17P_T2_34|J27D.G21|FMC conn.
|
|
|
|-
|IO_L18N_T2_34
|IO_L18N_T2_34
|J27D.H20
|FMC conn.
|
|
|
|-
|IO_L13P_T2_MRCC_34IO_L18P_T2_34|IO_L18P_T2_34|J27D.H19|FMC conn.
|
|
|
|-
| rowspan="2" |IO_L19N_T3_VREF_34
| rowspan="2" |IO_L19N_T3_VREF_34
|J27D.G19
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP21
|TP SMD
|-
|IO_L19P_T3_34
|n/a
|n/a
|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L14N_T2_SRCC_34IO_L1N_T0_34|IO_L1N_T0_34|J27B.C19|FMC conn.
|
|
|
|-
|IO_L1P_T0_34
|IO_L1P_T0_34
|J27B.C18
|FMC conn.
|
|
|
|-
|IO_L14P_T2_SRCC_34IO_L20N_T3_34|IO_L20N_T3_34|J27B.D18|FMC conn.
|
|
|
|-
|IO_L20P_T3_34
|IO_L20P_T3_34
|J27B.D17
|FMC conn.
|
|
|
|-
|IO_L15N_T2_DQS_34IO_L21N_T3_DQS_34|IO_L21N_T3_DQS_34|J27D.H17|FMC conn.
|
|
|
|-
|IO_L21P_T3_DQS_34
|IO_L21P_T3_DQS_34
|J27D.H16
|FMC conn.
|
|
|
|-
|IO_L15P_T2_DQS_34IO_L22N_T3_34|IO_L22N_T3_34|J27D.G16|FMC conn.
|
|
|
|-
|IO_L22P_T3_34
|IO_L22P_T3_34
|J27D.G15
|FMC conn.
|
|
|
|-
|IO_L16N_T2_34IO_L23N_T3_34|IO_L23N_T3_34|J27B.C11|FMC conn.
|
|
|
|-
|IO_L23P_T3_34
|IO_L23P_T3_34
|J27B.C10
|FMC conn.
|
|
|
|-
|IO_L16P_T2_34IO_L24N_T3_34|IO_L24N_T3_34|J27D.H23|FMC conn.
|
|
|
|-
|IO_L24P_T3_34
|IO_L24P_T3_34
|J27D.H22
|FMC conn.
|
|
|
|-
|IO_L17N_T2_34IO_L2N_T0_34|IO_L2N_T0_34|J27B.C15|FMC conn.
|
|
|
|-
|IO_L2P_T0_34
|IO_L2P_T0_34
|J27B.C14
|FMC conn.
|
|
|
|-
|IO_L17P_T2_34IO_L3N_T0_DQS_34|IO_L3N_T0_DQS_34|J27D.G13|FMC conn.
|
|
|
|-
|IO_L3P_T0_DQS_PUDC_B_34
(10K pull-up on SoM)
|IO_L3P_T0_DQS_PUDC_B_34
|J27D.G12
|FMC conn.
|
|
|
|-
|IO_L18N_T2_34IO_L4N_T0_34|IO_L4N_T0_34|J27D.G10|FMC conn.
|
|
|
|-
|IO_L4P_T0_34
|IO_L4P_T0_34
|J27D.G9
|FMC conn.
|
|
|
|-
|IO_L18P_T2_34IO_L5N_T0_34|IO_L5N_T0_34|J27D.H11|FMC conn.
|
|
|
|-
|IO_L5P_T0_34
|IO_L5P_T0_34
|J27D.H10
|FMC conn.
|
|
|
|-
|IO_L19N_T3_VREF_34rowspan="2" |IO_L6N_T0_VREF_34| rowspan="2" |IO_L6N_T0_VREF_34|J27B.D15|FMC conn.
|
|
|
|-
|TP22
|TP SMD
|
|
|
|-
|IO_L19P_T3_34IO_L6P_T0_34|n/a|n/a|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L7N_T1_34
|IO_L7N_T1_34
|J27D.H8
|FMC conn.
|
|
|
|-
|IO_L1N_T0_34IO_L7P_T1_34|IO_L7P_T1_34|J27D.H7|FMC conn.
|
|
|
|-
|IO_L8N_T1_34
|IO_L8N_T1_34
|J27D.H14
|FMC conn.
|
|
|
|-
|IO_L1P_T0_34IO_L8P_T1_34|IO_L8P_T1_34|J27D.H13|FMC conn.
|
|
|
|-
|IO_L9N_T1_DQS_34
|IO_L9N_T1_DQS_34
|J27B.D12
|FMC conn.
|
|
|
|-
|IO_L20N_T3_34IO_L9P_T1_DQS_34|IO_L9P_T1_DQS_34|J27B.D11|FMC conn.
|
|
|
|-
|
|
|-
|IO_L20P_T3_34
|
|
|
|-
|IO_L21N_T3_DQS_34rowspan="54" |35| rowspan="2" |IO_0_35| rowspan="2" |'''IO_0_VRN_35'''|J27C.F1|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.1|Header|-| rowspan="2" |IO_25_35| rowspan="2" |'''IO_25_VRP_35'''|J27E.K13|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.3|Header|-|IO_L10N_T1_AD11N_35|IO_L10N_T1_AD11N_35|J27D.G34|FMC conn.|FPGA_BANK35_AD11N|JP32.3|Header|-|IO_L10P_T1_AD11P_35|IO_L10P_T1_AD11P_35|J27D.G33|FMC conn.|FPGA_BANK35_AD11P|JP32.1|Header|-|IO_L11N_T1_SRCC_35|IO_L11N_T1_SRCC_35|J27E.J3|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_35
|IO_L11P_T1_SRCC_35
|J27E.J2
|FMC conn.
|
|
|
|-
|IO_L21P_T3_DQS_34IO_L12N_T1_MRCC_35|IO_L12N_T1_MRCC_35|J27E.K5|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_35
|IO_L12P_T1_MRCC_35
|J27E.K4
|FMC conn.
|
|
|
|-
|IO_L22N_T3_34IO_L13N_T2_MRCC_35|IO_L13N_T2_MRCC_35|J27C.F5|FMC conn.
|
|
|
|-
|IO_L22P_T3_34IO_L13P_T2_MRCC_35|IO_L13P_T2_MRCC_35|J27C.F4|FMC conn.
|
|
|
|-
|IO_L23N_T3_34IO_L14N_T2_AD4N_SRCC_35|IO_L14N_T2_AD4N_SRCC_35|J27C.E3|FMC conn.|FPGA_BANK35_AD4N|JP30.16|Header|-|IO_L14P_T2_AD4P_SRCC_35|IO_L14P_T2_AD4P_SRCC_35|J27C.E2|FMC conn.|FPGA_BANK35_AD4P|JP30.14|Header|-|IO_L15N_T2_DQS_AD12N_35|IO_L15N_T2_DQS_AD12N_35|J27D.H38|FMC conn.|FPGA_BANK35_AD12N|JP32.8|Header|-|IO_L15P_T2_DQS_AD12P_35|IO_L15P_T2_DQS_AD12P_35|J27D.H37|FMC conn.|FPGA_BANK35_AD12P|JP32.6|Header|-|IO_L16N_T2_35|IO_L16N_T2_35|J27D.G37|FMC conn.
|
|
|
|-
|IO_L23P_T3_34IO_L16P_T2_35|IO_L16P_T2_35|J27D.G36|FMC conn.
|
|
|
|-
|IO_L17N_T2_AD5N_35
|IO_L17N_T2_AD5N_35
|J27E.K8
|FMC conn.
|FPGA_BANK35_AD5N
|JP31.1
|Header
|-
|IO_L17P_T2_AD5P_35
|IO_L17P_T2_AD5P_35
|J27E.K7
|FMC conn.
|FPGA_BANK35_AD5P
|JP30.15
|Header
|-
|IO_L18N_T2_AD13N_35
|IO_L18N_T2_AD13N_35
|J27E.J7
|FMC conn.
|FPGA_BANK35_AD13N
|JP32.9
|Header
|-
|IO_L18P_T2_AD13P_35
|IO_L18P_T2_AD13P_35
|J27E.J6
|FMC conn.
|FPGA_BANK35_AD13P
|JP32.7
|Header
|-
| rowspan="2" |IO_L19N_T3_VREF_35
| rowspan="2" |IO_L19N_T3_VREF_35
|J27C.F8
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP24
|TP SMD
|-
|IO_L19P_T3_35
|IO_L19P_T3_35
|J27C.F7
|FMC conn.
|
|
|
|-
|IO_L24N_T3_34IO_L1N_T0_AD0N_35|IO_L1N_T0_AD0N_35|J27D.G25|FMC conn.|FPGA_BANK35_AD0P|JP30.4|Header|-|IO_L1P_T0_AD0P_35|IO_L1P_T0_AD0P_35|J27D.G24|FMC conn.|FPGA_BANK35_AD0N|JP30.2|Header|-|IO_L20N_T3_AD6N_35|IO_L20N_T3_AD6N_35|J27C.E7|FMC conn.|FPGA_BANK35_AD6N|JP31.6|Header|-|IO_L20P_T3_AD6P_35|IO_L20P_T3_AD6P_35|J27C.E6|FMC conn.|FPGA_BANK35_AD6P|JP31.4|Header|-|IO_L21N_T3_DQS_AD14N_35|IO_L21N_T3_DQS_AD14N_35|J27E.K11|FMC conn.|FPGA_BANK35_AD14N|JP32.14|Header|-|IO_L21P_T3_DQS_AD14P_35|IO_L21P_T3_DQS_AD14P_35|J27E.K10|FMC conn.|FPGA_BANK35_AD14P|JP32.12|Header|-|IO_L22N_T3_AD7N_35|IO_L22N_T3_AD7N_35|J27E.J10|FMC conn.|FPGA_BANK35_AD7N|JP31.7|Header|-|IO_L22P_T3_AD7P_35|IO_L22P_T3_AD7P_35|J27E.J9|FMC conn.|FPGA_BANK35_AD7P|JP31.5|Header|-|IO_L23N_T3_35|IO_L23N_T3_35|J27C.F11|FMC conn.
|
|
|
|-
|IO_L24P_T3_34IO_L23P_T3_35|IO_L23P_T3_35|J27C.F10|FMC conn.
|
|
|
|-
|IO_L2N_T0_34IO_L24N_T3_AD15N_35|IO_L24N_T3_AD15N_35|J27C.E10|FMC conn.|FPGA_BANK35_AD15N|JP32.15|Header|-|IO_L24P_T3_AD15P_35|IO_L24P_T3_AD15P_35|J27C.E9|FMC conn.|FPGA_BANK35_AD15P|JP32.13|Header|-|IO_L2N_T0_AD8N_35|IO_L2N_T0_AD8N_35|J27B.D24|FMC conn.|FPGA_BANK35_AD8N|JP31.12|Header|-|IO_L2P_T0_AD8P_35|IO_L2P_T0_AD8P_35|J27B.D23|FMC conn.|FPGA_BANK35_AD8P|JP31.10|Header|-|IO_L3N_T0_DQS_AD1N_35|IO_L3N_T0_DQS_AD1N_35|J27D.H29|FMC conn.|FPGA_BANK35_AD1N|JP30.5|Header|-|IO_L3P_T0_DQS_AD1P_35|IO_L3P_T0_DQS_AD1P_35|J27D.H28|FMC conn.|FPGA_BANK35_AD1P|JP30.3|Header|-|IO_L4N_T0_35|IO_L4N_T0_35|J27D.G28|FMC conn.
|
|
|
|-
|IO_L2P_T0_34IO_L4P_T0_35|IO_L4P_T0_35|J27D.G27|FMC conn.
|
|
|
|-
|IO_L5N_T0_AD9N_35
|IO_L5N_T0_AD9N_35
|J27B.D27
|FMC conn.
|FPGA_BANK35_AD9N
|JP31.13
|Header
|-
|IO_L5P_T0_AD9P_35
|IO_L5P_T0_AD9P_35
|J27B.D26
|FMC conn.
|FPGA_BANK35_AD9P
|JP31.11
|Header
|-
| rowspan="2" |IO_L6N_T0_VREF_35
| rowspan="2" |IO_L6N_T0_VREF_35
|J27B.C27
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP23
|TP SMD
|-
|IO_L6P_T0_35
|IO_L6P_T0_35
|J27B.C26
|FMC conn.
|
|
|
|-
|IO_L3N_T0_DQS_34IO_L7N_T1_AD2N_35|IO_L7N_T1_AD2N_35|J27D.H32|FMC conn.|FPGA_BANK35_AD2N|JP30.10|Header|-|IO_L7P_T1_AD2P_35|IO_L7P_T1_AD2P_35|J27D.H31|FMC conn.|FPGA_BANK35_AD2P|JP30.8|Header|-|IO_L8N_T1_AD10N_35|IO_L8N_T1_AD10N_35|J27D.G31|FMC conn.|FPGA_BANK35_AD10N|JP32.2|Header|-|IO_L8P_T1_AD10P_35|IO_L8P_T1_AD10P_35|J27D.G30|FMC conn.|FPGA_BANK35_AD10P|JP31.16|Header|-|IO_L9N_T1_DQS_AD3N_35|IO_L9N_T1_DQS_AD3N_35|J27D.H35|FMC conn.|FPGA_BANK35_AD3N|JP30.11|Header|-|IO_L9P_T1_DQS_AD3P_35|IO_L9P_T1_DQS_AD3P_35|J27D.H34|FMC conn.|FPGA_BANK35_AD3P|JP30.9|Header|-
|
|
|
|
|
|
|-
|IO_L3P_T0_DQS_PUDC_B_34
|
|
|
|-
|IO_L4N_T0_34rowspan="26" |13'''(not available on Zynq 7007S and 7010)'''|IO_L11P_T1_SRCC_13|'''IO_L23P_T3_13'''|JP17.3|PMOD [A]
|
|
|
|-
|IO_L4P_T0_34IO_L11N_T1_SRCC_13|'''IO_L23N_T3_13'''|JP17.4|PMOD [A]
|
|
|
|-
|IO_L5N_T0_34IO_L12P_T1_MRCC_13|'''IO_L9P_T1_DQS_13'''|JP17.2|PMOD [A]|IO_L9P_T1_DQS_13|J30.1|ONE PIECE
|-
|IO_L5P_T0_34IO_L12N_T1_MRCC_13|'''IO_L9N_T1_DQS_13'''|JP17.1|PMOD [A]|IO_L9N_T1_DQS_13|J30.3|ONE PIECE
|-
|IO_L6N_T0_VREF_34IO_L13P_T2_MRCC_13|'''IO_L7P_T1_13'''|JP17.7|PMOD [A]|IO_L7P_T1_13|J30.24|ONE PIECE
|-
|IO_L6P_T0_34IO_L13N_T2_MRCC_13|'''IO_L7N_T1_13'''|JP17.8|PMOD [A]|IO_L7N_T1_13|J30.26|ONE PIECE|-|IO_L14P_T2_SRCC_13|'''IO_L15P_T2_DQS_13'''|n/a|ETH1_RXCK|IO_L15P_T2_DQS_13|J30.25|ONE PIECE
|-
|IO_L7N_T1_34IO_L14N_T2_SRCC_13|'''IO_L15N_T2_DQS_13'''|n/a|ETH1_RXCTL|IO_L15N_T2_DQS_13|J30.27|ONE PIECE
|-
|IO_L7P_T1_34IO_L15P_T2_DQS_13|'''IO_L5P_T0_13'''|JP17.6|PMOD [A]|IO_L5P_T0_13|J30.20|ONE PIECE
|-
|IO_L8N_T1_34IO_L15N_T2_DQS_13|'''IO_L5N_T0_13'''|JP17.5|PMOD [A]|IO_L5N_T0_13|J30.18|ONE PIECE|-|IO_L16N_T2_13|IO_L16N_T2_13|n/a|ETH1_TXCTL|IO_L16N_T2_13|J30.31|ONE PIECE|-|IO_L16P_T2_13|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE
|-
|IO_L8P_T1_34IO_L17N_T2_13|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE
|-
|IO_L9N_T1_DQS_34IO_L17P_T2_13|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE
|-
|IO_L9P_T1_DQS_34IO_L18N_T2_13|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE
|-
|IO_L18P_T2_13|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE|-|IO_L19N_T3_VREF_13|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE|-|IO_L19P_T3_13|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|J30.41|ONE PIECE|-|IO_L20N_T3_13|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE|-|IO_L20P_T3_13|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE
|-
|35|IO_0_35IO_L21N_T3_DQS_13|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE
|-
|IO_L21P_T3_DQS_13|IO_25_35|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE
|-
|IO_L22N_T3_13|IO_L10N_T1_AD11N_35||||IO_L22N_T3_13
|
|
|IO_L22N_T3_13
|J30.55
|ONE PIECE
|-
|IO_L22P_T3_13|IO_L10P_T1_AD11P_35|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE
|-
|
|IO_L11N_T1_SRCC_35
|
|
|
|
|
|
|-
|
|IO_L11P_T1_SRCC_35
|
|
|
|
|
|
|-
|
|IO_L12N_T1_MRCC_35
|
|
|
|
|
|
|-
|
|IO_L12P_T1_MRCC_35
|
|
|
|
|
|
|-
|
|IO_L13N_T2_MRCC_35
|
|
|
|
|
|
|-
|
|IO_L13P_T2_MRCC_35
|
|
|
|
|
|
|-
|
|IO_L14N_T2_AD4N_SRCC_35
|
|
|
|
|
|
|-
|
|IO_L14P_T2_AD4P_SRCC_35
|
|
|
|
|
|
|-
|
|IO_L15N_T2_DQS_AD12N_35
|
|
|
|
|
|
|-
|
|IO_L15P_T2_DQS_AD12P_35
|
|
|
|
|
|
|-
|
|IO_L16N_T2_35
|
|
|
|
|
|
|-
|
|IO_L16P_T2_35
|
|
|
|
|
|
|-
|
|IO_L17N_T2_AD5N_35
|
|
|
|
|
|
|-
|
|IO_L17P_T2_AD5P_35
|
|
|
|
|
|
|-
|
|IO_L18N_T2_AD13N_35
|
|
|
|
|
|
|-
|
|IO_L18P_T2_AD13P_35
|
|
|
|
|
|
|-
|
|IO_L19N_T3_VREF_35
|
|
|
|
|
|
|-
|
|IO_L19P_T3_35
|
|
|
|
|
|
|-
|
|IO_L1N_T0_AD0N_35
|
|
|
|
|
|
|-
|
|IO_L1P_T0_AD0P_35
|
|
|
|
|
|
|-
|
|IO_L20N_T3_AD6N_35
|
|
|
|
|
|
|-
|
|IO_L20P_T3_AD6P_35
|
|
|
|
|
|
|-
|
|IO_L21N_T3_DQS_AD14N_35
|
|
|
|
|
|
|-
|
|IO_L21P_T3_DQS_AD14P_35
|
|
|
|
|
|
|-
|
|IO_L22N_T3_AD7N_35
|
|
|
|
|
|
|-
|
|IO_L22P_T3_AD7P_35
|
|
|
|
|
|
|-
|
|IO_L23N_T3_35
|
|
|
|
|
|
|-
|
|IO_L23P_T3_35
|
|
|
|
|
|
|-
|
|IO_L24N_T3_AD15N_35
|
|
|
|
|
|
|-
|
|IO_L24P_T3_AD15P_35
|
|
|
|
|
|
|-
|
|IO_L2N_T0_AD8N_35
|
|
|
|
|
|
|-
|
|IO_L2P_T0_AD8P_35
|
|
|
|
|
|
|-
|
|IO_L3N_T0_DQS_AD1N_35
|
|
|
|
|
|
|-
|
|IO_L3P_T0_DQS_AD1P_35
|
|
|
|
|
|
|-
|
|IO_L4N_T0_35
|
|
|
|
|
|
|-
|
|IO_L4P_T0_35
|
|
|
|
|
|
|-
|
|IO_L5N_T0_AD9N_35
|
|
|
|
|
|
|-
|
|IO_L5P_T0_AD9P_35
|
|
|
|
|
|
|-
|
|IO_L6N_T0_VREF_35
|
|
|
|
|
|
|-
|
|IO_L6P_T0_35
|
|
|
|
|
|
|-
|
|IO_L7N_T1_AD2N_35
|
|
|
|
|
|
|-
|
|IO_L7P_T1_AD2P_35
|
|
|
|
|
|
|-
|
|IO_L8N_T1_AD10N_35
|
|
|
|
|
|
|-
|
|IO_L8P_T1_AD10P_35
|
|
|
|
|
|
|-
|
|IO_L9N_T1_DQS_AD3N_35
|
|
|
|
|
|
|-
|
|IO_L9P_T1_DQS_AD3P_35
|
|
|
|
|
|
|-
|
|
|
|
|
|
|
|
|-
|13
|IO_L11P_T1_SRCC_13
|IO_L23P_T3_13
|JP17.3
|PMOD [A]
|IO_L11P_T1_SRCC_13
|J26.12
|LVDS
|-
|13
|IO_L11N_T1_SRCC_13
|IO_L23N_T3_13
|JP17.4
|PMOD [A]
|IO_L11N_T1_SRCC_13
|J26.11
|LVDS
|-
|13
|IO_L12P_T1_MRCC_13
|IO_L9P_T1_DQS_13
|JP17.2
|PMOD [A]
|IO_L12P_T1_MRCC_13
|J26.6
|LVDS
|-
|13
|IO_L12N_T1_MRCC_13
|IO_L9N_T1_DQS_13
|JP17.1
|PMOD [A]
|IO_L12N_T1_MRCC_13
|J26.5
|LVDS
|-
|13
|IO_L13P_T2_MRCC_13
|IO_L7P_T1_13
|JP17.7
|PMOD [A]
|IO_L13P_T2_MRCC_13
|J26.15
|LVDS
|-
|13
|IO_L13N_T2_MRCC_13
|IO_L7N_T1_13
|JP17.8
|PMOD [A]
|IO_L13N_T2_MRCC_13
|J26.14
|LVDS
|-
|13
|IO_L14P_T2_SRCC_13
|IO_L15P_T2_DQS_13
|n/a
|ETH1_RXCK
| colspan="3" |n/a
|-
|13
|IO_L14N_T2_SRCC_13
|IO_L15N_T2_DQS_13
|n/a
|ETH1_RXCTL
| colspan="3" |n/a
|-
|13
|IO_L15P_T2_DQS_13
|IO_L5P_T0_13
|JP17.6
|PMOD [A]
|IO_L14P_T2_SRCC_13
|J26.9
|LVDS
|-
|13
|IO_L15N_T2_DQS_13
|IO_L5N_T0_13
|JP17.5
|PMOD [A]
|IO_L14N_T2_SRCC_13
|J26.8
|LVDS
|-
| rowspan="2" |13
| rowspan="2" |IO_L6N_T0_VREF_13
| rowspan="2" |IO_L6N_T0_VREF_13|JP23.3|PMOD [B]| rowspan="2" |IO_0_13IO_L6N_T0_VREF_13| rowspan="2" |J26J30.1730| rowspan="2" |LVDSONE PIECE
|-
|n/a
|}
There ==== BoraXEVB unavailable signals ====Some BoraXEVB signals are also some Carrier signals unavailable for the Boralite when it is mated with Bora Lite SoM. The following signals are '''not ''' routed to the SoM due to the limited pin counte count of the SODIMM connector.
{| class="wikitable"
|+
BoraXEVB's signal that are not available when mated with Bora Lite SoM
!Bank
!Carrier's signal
|500
|NAND_CLE/VCFG0
|-
|
|
|}
U0001
Bureaucrats, dave_user, Administrators
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