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{{InfoBoxTop}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
|-
|}
==Block DiagramConnectors pinout ==
=== J1,J2 and J3 ===The following picture shows pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress EVB block diagram: module]].
{| class="wikitable"
|-
!IssuePin# !DescriptionPin name!Function!Notes
|-
|-
|2 , 3 || DGND || Ground || -
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[:Category:BoraLite |BoraLite]] SOM module
=== WatchDog Settings - S1, S2 and S3 ===
|-
|}
=== JTAG ===
JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. === BANK13 VDDIO selector = JTAG XILINX - JP25 J13 ====JP25 J13 is a 1214-pin 6x2x2.54 7x2x2 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGND|| - || -|-|2 || LDO_B13_1V63.3V|| adds +1.6V to VDDIO_BANK13 - || -
|-
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
!Pin name
!Function
!Notes
|-
|1 || 3.3V|| - || -|-|2 || LDO_B35_1V63.3V|| adds +1- || -|-|3, 11, 17, 19 || N.C.6V to VDDIO_BANK35 || - || -
|-
|4 , 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_800mVDGND|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 5 || LDO_B35_400mVJTAG_TDI|| adds +400mV to VDDIO_BANK35 - || -
|-
|8 7 || LDO_B35_200mVJTAG_TMS|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 9 || LDO_B35_100mVJTAG_TCK|| adds +100mV to VDDIO_BANK35 - || -
|-
|12 13 || LDO_B35_50mVJTAG_TDO|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 15 || DGNDJTAG_TRSTn|| - || -
|-
|}
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 || VADJ_FB (51K1)|| selects 1.8V VADJ |3| -UART_EXT_TX|-Transmit line|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -Connected to protection diode array
|-
|10 5|DGND| VADJ_FB (100K)Ground|| selects 1.2V VADJ || -
|-
|12 || RFU|7, 8| Reserved || -N.C.|-N.C.|1, 3, 5, 7, 9, 11 || DGND|| - || -Connected to protection diode array
|-
|}
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
{| class=== JTAG ==="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 ||USB_OTG_VBUS || - || -JTAG port is available as two different mechanical connectors:|-* |2.00mm||USBM1 || - || -|-|3 ||USBP1 || - || -pitch 7x2 header (Xilinx standard)* 2.54mm|-|4 ||OTG_ID || - || -|-|5 ||USB_OTG_DGND || - || -|-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations|6, 7, depending on bootstrap signals. In case split mode is selected8, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.9 ||USB_OTG_SHIELD || - || -* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.|-|} === MicroSD - J21 ===
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|4 3 || JTAG_TMSPS_SD0_CMD||| - || -
|-
|6 4 || JTAG_TCK3.3V||| - || -
|-
|8 5 || JTAG_TDOPS_SD0_CLK||| - || -|-|6, 9, 10, 11, 12 ||DGND||| - || -
|-
|10 7 || JTAG_TDIPS_SD0_DAT0||| - || -
|-
|12 8 || N.C.PS_SD0_DAT1||| - || -
|-
|14 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
==== JTAG ARM DWM (DAVE Wifi/BT module) socket - J18 =J23 ===J18 J23 is a 2052991-pin 10x2x20308 connector type (30 pins, vertical, 0.54 pitch vertical header50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 , 2 || 3.3V5V || - || -
|-
|2 3, 4 || 3.3V|| - || -
|-
|35, 116, 17<br> 9, 10,<br>19 || N.C.DGND || - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 207 || DGNDDWM_SD_CMD || - || -
|-
|5 8 || JTAG_TDIDWM_SD_CLK || - || -
|-
|7 11 || JTAG_TMSDWM_SD_DAT0 || - || -
|-
|9 12, 14,<br>16, 18,<br>20, 22 || JTAG_TCKN.C. || - || -
|-
|13 || JTAG_TDODWM_SD_DAT1 || - || -
|-
|15 || JTAG_TRSTnDWM_SD_DAT2 || - || -|-|17 ||DWM_SD_DAT3 || - || -|-|21 ||DWM_UART_RX || - || -|-|23 ||DWM_UART_CTS || - || -|-|24 ||DWM_BT_F5 || - || -|-|25 ||DWM_UART_TX || - || -|-|26 ||DWM_BT_F2 || - || -|-|27 ||DWM_UART_RTS || - || -|-|28 ||DWM_WIFI_IRQ || - || -|-|29 ||DWM_BT_EN || - || -|-|30 ||DWM_WIFI_EN || - || -
|-
|}
=== UART1 CAN - J17 J24 === J17 J24 is a standard DB9 connector that routes 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the signals coming from the RS232 transceiver that CAN interface. This 2.5mm-pitch header is connected to compatible with commonly available IDC-10/DB9 flat cables. The following table reports the PS MIO signals pinout of the UART1 port.connector:
{| class="wikitable"
!Notes
|-
|1, 6, 4<br>7, 8,<br>9, 10 ||N.C.|N.C.|- || -
|-
|2, 5 |UART_EXT_RX|Receive lineCAN_SHIELD |Connected to protection diode array| - || -
|-
|3|UART_EXT_TX|Transmit lineCAN_L |Connected to protection diode array| - || -
|-
|54 |DGND|GroundCAN_H ||-|7, 8|N.C.|N.C.|Connected to protection diode array-
|-
|}
=== USB OTG Touch screen - J19 J25=== J19 J25 is a standard USB MICRO AB ZIF 4-pin 1.0mm pitch connector. It is connected that connects the touchscreen drive lines to the BORA touch screen controller on the BoORA Xpress USB 2.0 OTG peripheralEVB. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 ||USB_OTG_VBUS TSC_YP || - || -
|-
|2 ||USBM1 TSC_XP || - || -
|-
|3 ||USBP1 TSC_YM || - || -
|-
|4 ||OTG_ID TSC_XM || - || -
|-
=== MicroSD LVDS - J21 J26 === J21 J26 is a microSD memory card connectorvertical double row straight 20-pin 1. It is connected 25mm pitch header. This interface shows how to the BORA Xpress SOM through implement a bidirectional 1differential connection to an LCD screen.8VAs known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https:/3/wiki.3V voltageanalog.com/resources/tools-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8Vsoftware/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 , 2 ||PS_SD0_DAT23.3V_LCD || - || - |-|3, 4, 7, 10,<br>13, 16, 19 ||DGND || Ground || -
|-
|2 5 ||PS_SD0_DAT3|LCD_LVDS_D0- || - || -
|-
|3 6 ||PS_SD0_CMD|LCD_LVDS_D0+ || - || -
|-
|4 8 ||3.3V|LCD_LVDS_D1- || - || -
|-
|5 9 ||PS_SD0_CLK|LCD_LVDS_D1+ || - || -
|-
|6, 9, 10, 11, 12 ||DGND|LCD_LVDS_D2- || - || -
|-
|7 12 ||PS_SD0_DAT0|LCD_LVDS_D2+ || - || -
|-
|8 14 ||PS_SD0_DAT1|LCD_LVDS_CLK- || - || -
|-
|13 15 |3.3V|LCD_LVDS_CLK+ || - || ||Pull up to 3.3V with 10K Ohm -
|-
|17 ||LCD_P17 || - || -|-|18 ||LCD_P18 || - || -|-|20 ||LCD_P20 || - || -|-|21,22 ||DGND || Ground || Shield|-|} === DWM FPGA Mezzanine Card (DAVE Wifi/BT moduleFMC) socket Connector - J23 J27 ===J23 J27 is a 52991400 pins ANSI/VITA 57.1-0308 2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector type (30 pins, vertical, 0.50mm picth). This socket connects the At this [[Wireless_Module_(DWM) :File:BoraXEVB-FMC-routing.zip| DWM Wireless Modulelink]] (optional) to a spreadsheet providing the BORA Xpress EVBsame information is available for download. The following table reports the pinout For more information about I/O voltage of the single-ended signals available on FMC connector:, please refer to [[#PL's I/O voltage selections|this section]]. ==== HPC Row A ====
{| class="wikitable"
!Notes
|-
|1, 2 A1||5V DGND|| - GND|| -
|-
|3, 4 A2||3.3V MGTxRXP1|| - DP1_M2C_P|| -
|-
|5, 6,<br> 9, 10,<br>19 A3||DGND MGTxRXN1|| - DP1_M2C_N|| -
|-
|7 A4||DWM_SD_CMD DGND|| - GND|| -
|-
|8 A5||DWM_SD_CLK DGND|| - GND|| -
|-
|11 A6||DWM_SD_DAT0 MGTxRXP2||DP2_M2C_P||| - | A7||MGTxRXN2||DP2_M2C_N|| -
|-
|12, 14,<br>16, 18,<br>20, 22 A8||N.C. DGND|| - GND|| -
|-
|13 A9||DWM_SD_DAT1 DGND|| - GND|| -
|-
|15 A10||DWM_SD_DAT2 MGTxRXP3|| - DP3_M2C_P|| -
|-
|17 A11||DWM_SD_DAT3 MGTxRXN3|| - DP3_M2C_N|| -
|-
|21 A12||DWM_UART_RX DGND|| - GND|| -
|-
|23 A13||DWM_UART_CTS DGND|| - GND|| -
|-
|24 A14||DWM_BT_F5 <span style="color:#ff0000">not connected</span>|| - DP4_M2C_P|| -
|-
|25 A15||DWM_UART_TX <span style="color:#ff0000">not connected</span>|| - DP4_M2C_N|| -
|-
|26 A16||DWM_BT_F2 DGND|| - GND|| -
|-
|27 A17||DWM_UART_RTS DGND|| - GND|| -
|-
|28 A18||DWM_WIFI_IRQ <span style="color:#ff0000">not connected</span>|| - DP5_M2C_P|| -
|-
|29 A19||DWM_BT_EN <span style="color:#ff0000">not connected</span>|| - DP5_M2C_N|| -
|-
|30 A20||DWM_WIFI_EN DGND|| - GND|| -
|-
|} === CAN - J24 ===J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector: {A21||DGND||GND|| class="wikitable"
|-
|-
|1, 6,<br>7, 8,<br>9, 10 A23||N.C. MGTxTXN1|| - DP1_C2M_N|| -
|-
|2, 5 A24||CAN_SHIELD DGND|| - GND|| -
|-
|3 A25||CAN_L DGND|| - GND|| -
|-
|4 A26||CAN_H MGTxTXP2|| - DP2_C2M_P|| -
|-
|} === Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector: {A27||MGTxTXN2||DP2_C2M_N|| class="wikitable"
|-
|-
|1 A29||TSC_YP DGND|| - GND|| -
|-
|2 A30||TSC_XP MGTxTXP3||DP3_C2M_P||| - | A31||MGTxTXN3||DP3_C2M_N||| -| A32||DGND||GND|||-| A33||DGND||GND|||-| A34||<span style="color:#ff0000">not connected</span>||DP4_C2M_P|||-| A35||<span style="color:#ff0000">not connected</span>||DP4_C2M_N|||-| A36||DGND||GND|||-| A37||DGND||GND||
|-
|3 A38||TSC_YM <span style="color:#ff0000">not connected</span>|| - DP5_C2M_P|| -
|-
|4 A39||TSC_XM <span style="color:#ff0000">not connected</span>|| - DP5_C2M_N|| -
|-
| A40||DGND||GND||
|}
=== LVDS - J26 = HPC Row B ====J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2 B1||3.3V_LCD RSVD|| - RES1|| -
|-
|3, 4, 7, 10,<br>13, 16, 19 B2||DGND || Ground GND|| -
|-
|5 B3||LCD_LVDS_D0- DGND|| - GND|| -
|-
|6 B4||LCD_LVDS_D0+ <span style="color:#ff0000">not connected</span>|| - DP9_M2C_P|| -
|-
|8 B5||LCD_LVDS_D1- <span style="color:#ff0000">not connected</span>|| - DP9_M2C_N|| -
|-
|9 B6||LCD_LVDS_D1+ DGND|| - GND|| -
|-
|11 B7||LCD_LVDS_D2- DGND|| - GND|| -
|-
|12 B8||LCD_LVDS_D2+ <span style="color:#ff0000">not connected</span>|| - DP8_M2C_P|| -
|-
|15 B9||LCD_LVDS_CLK+ <span style="color:#ff0000">not connected</span>|| - DP8_M2C_N|| -
|-
|17 B10||LCD_P17 DGND|| - GND|| -
|-
|18 B11||LCD_P18 DGND|| - GND|| -
|-
|20 B12||LCD_P20 <span style="color:#ff0000">not connected</span>|| - DP7_M2C_P|| -
|-
|21,22 B13||DGND <span style="color:#ff0000">not connected</span>|| Ground DP7_M2C_N|| Shield
|-
|} === FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipB14||DGND||GND|link]] a spreadsheet providing the same information is available for download. ==== HPC Row A ==== {| class="wikitable"
|-
|-
| A1B16||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_M2C_P||
|-
| A2B17||MGTxRXP1<span style="color:#ff0000">not connected</span>||DP1_M2C_PDP6_M2C_N||
|-
| A3B18||MGTxRXN1DGND||DP1_M2C_NGND||
|-
| A4B19||DGND||GND||
|-
| A5B20||DGNDMGTREFCLK1P||GNDGBTCLK1_M2C_P||
|-
| A6B21||MGTxRXP2MGTREFCLK1N||DP2_M2C_PGBTCLK1_M2C_N||
|-
| A7B22||MGTxRXN2DGND||DP2_M2C_NGND||
|-
| A8B23||DGND||GND||
|-
| A9B24||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_C2M_P||
|-
| A10B25||MGTxRXP3<span style="color:#ff0000">not connected</span>||DP3_M2C_PDP9_C2M_N||
|-
| A11B26||MGTxRXN3DGND||DP3_M2C_NGND||
|-
| A12B27||DGND||GND||
|-
| A13B28||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_C2M_P||
|-
| A14B29||<span style="color:#ff0000">not connected</span>||DP4_M2C_PDP8_C2M_N||
|-
| A15B30||<span style="color:#ff0000">not connected</span>DGND||DP4_M2C_NGND||
|-
| A16B31||DGND||GND||
|-
| A17B32||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_C2M_P||
|-
| A18B33||<span style="color:#ff0000">not connected</span>||DP5_M2C_PDP7_C2M_N||
|-
| A19B34||<span style="color:#ff0000">not connected</span>DGND||DP5_M2C_NGND||
|-
| A20B35||DGND||GND||
|-
| A21B36||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_C2M_P||
|-
| A22B37||MGTxTXP1<span style="color:#ff0000">not connected</span>||DP1_C2M_PDP6_C2M_N||
|-
| A23B38||MGTxTXN1DGND||DP1_C2M_NGND||
|-
| A24B39||DGND||GND||
|-
| A25B40||DGNDRSVD||GNDRES0|||} ==== LPC Row C ==== {| class="wikitable"
|-
|-
| A28C2||DGNDMGTxTXP0||GNDDP0_C2M_P||
|-
| A29C3||DGNDMGTxTXN0||GNDDP0_C2M_N||
|-
| A30C4||MGTxTXP3DGND||DP3_C2M_PGND||
|-
| A31C5||MGTxTXN3DGND||DP3_C2M_NGND||
|-
| A32C6||DGNDMGTxRXP0||GNDDP0_M2C_P||
|-
| A33C7||DGNDMGTxRXN0||GNDDP0_M2C_N||
|-
| A34C8||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_PGND||
|-
| A35C9||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_NGND||
|-
| A36C10||DGNDIO_L23P_T3_34||GNDLA06_P||
|-
| A37C11||DGNDIO_L23N_T3_34||GNDLA06_N||
|-
| A38C12||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_PGND||
|-
| A39C13||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_NGND||
|-
| A40C14||DGNDIO_L2P_T0_34||GNDLA10_P|||} ==== HPC Row B ==== {| class="wikitable"
|-
|-
| B1C16||RSVDDGND||RES1GND||
|-
| B2C17||DGND||GND||
|-
| B3C18||DGNDIO_L1P_T0_34||GNDLA14_P||
|-
| B4C19||<span style="color:#ff0000">not connected</span>IO_L1N_T0_34||DP9_M2C_PLA14_N||
|-
| B5C20||<span style="color:#ff0000">not connected</span>DGND||DP9_M2C_NGND||
|-
| B6C21||DGND||GND||
|-
| B7C22||DGNDIO_L16P_T2_34||GNDLA18_P_CC||
|-
| B8C23||<span style="color:#ff0000">not connected</span>IO_L16N_T2_34||DP8_M2C_PLA18_N_CC||
|-
| B9C24||<span style="color:#ff0000">not connected</span>DGND||DP8_M2C_NGND||
|-
| B10C25||DGND||GND||
|-
| B11C26||DGNDIO_L6P_T0_35||GNDLA27_P||
|-
| B12C27||<span style="color:#ff0000">not connected</span>IO_L6N_T0_VREF_35||DP7_M2C_PLA27_N||
|-
| B13C28||<span style="color:#ff0000">not connected</span>DGND||DP7_M2C_NGND||
|-
| B14C29||DGND||GND||
|-
| B15C30||DGNDI2C0_SCL||GNDSCL||
|-
| B16C31||<span style="color:#ff0000">not connected</span>I2C0_SDA||DP6_M2C_PSDA||
|-
| B17C32||<span style="color:#ff0000">not connected</span>DGND||DP6_M2C_NGND||
|-
| B18C33||DGND||GND||
|-
| B19C34||DGNDGA0||GNDGA0||
|-
| B20C35||MGTREFCLK1PFMC_12P0V||GBTCLK1_M2C_P12P0V||
|-
| B21C36||MGTREFCLK1NDGND||GBTCLK1_M2C_NGND||
|-
| B22C37||DGNDFMC_12P0V||GND12P0V||
|-
| B23C38||DGND||GND||
|-
| B24C39||<span style="color:#ff0000">not connected</span>FMC_3P3V||DP9_C2M_P3P3V||
|-
| B25C40||<span style="color:#ff0000">not connected</span>DGND||GND||DP9_C2M_N|} ==== LPC Row D ==== {|class="wikitable"
|-
|-
| B27D1||DGNDIO_25_VRP_34||GNDPG_C2M||
|-
| B28D2||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_PGND||
|-
| B29D3||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_NGND||
|-
| B30D4||DGNDMGTREFCLK0P||GNDGBTCLK0_M2C_P||
|-
| B31D5||DGNDMGTREFCLK0N||GNDGBTCLK0_M2C_N||
|-
| B32D6||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_PGND||
|-
| B33D7||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_NGND||
|-
| B34D8||DGNDIO_L14P_T2_SRCC_34||GNDLA01_P_CC||
|-
| B35D9||DGNDIO_L14N_T2_SRCC_34||GNDLA01_N_CC||
|-
| B36D10||<span style="color:#ff0000">not connected</span>DGND||DP6_C2M_PGND||
|-
| B37D11||<span style="color:#ff0000">not connected</span>IO_L9P_T1_DQS_34||DP6_C2M_NLA05_P||
|-
| B38D12||DGNDIO_L9N_T1_DQS_34||GNDLA05_N||
|-
| B39D13||DGND||GND||
|-
| B40D14||RSVDIO_L6P_T0_34||RES0LA09_P|||} ==== LPC Row C ==== {| class="wikitable"
|-
|-
| C1D16||DGND||GND||
|-
| C2D17||MGTxTXP0IO_L20P_T3_34||DP0_C2M_PLA13_P||
|-
| C3D18||MGTxTXN0IO_L20N_T3_34||DP0_C2M_NLA13_N||
|-
| C4D19||DGND||GND||
|-
| C5D20||DGNDIO_L15P_T2_DQS_34||GNDLA17_P_CC||
|-
| C6D21||MGTxRXP0IO_L15N_T2_DQS_34||DP0_M2C_PLA17_N_CC||
|-
| C7D22||MGTxRXN0DGND||DP0_M2C_NGND||
|-
| C8D23||DGNDIO_L2P_T0_AD8P_35||GNDLA23_P||
|-
| C9D24||DGNDIO_L2N_T0_AD8N_35||GNDLA23_N||
|-
| C10D25||IO_L23P_T3_34DGND||LA06_PGND||
|-
| C11D26||IO_L23N_T3_34IO_L5P_T0_AD9P_35||LA06_NLA26_P||
|-
| C12D27||DGNDIO_L5N_T0_AD9N_35||GNDLA26_N||
|-
| C13D28||DGND||GND||
|-
| C14D29||IO_L2P_T0_34JTAG_TCK||LA10_PTCK||
|-
| C15D30||IO_L2N_T0_34JTAG_TDI||LA10_NTDI||
|-
| C16D31||DGNDFMC_TDO_ZYNQ_TDI||GNDTDO||
|-
| C17D32||DGNDFMC_3P3VAUX||GND3P3VAUX||
|-
| C18D33||IO_L1P_T0_34JTAG_TMS||LA14_PTMS||
|-
| C19D34||IO_L1N_T0_34JTAG_TRSTn||LA14_NTRST_L||
|-
| C20D35||DGNDGA0||GNDGA1||
|-
| C21D36||DGNDFMC_3P3V||GND3P3V||
|-
| C22D37||IO_L16P_T2_34DGND||LA18_P_CCGND||
|-
| C23D38||IO_L16N_T2_34FMC_3P3V||LA18_N_CC3P3V||
|-
| C24D39||DGND||GND||
|-
| C25D40||DGNDFMC_3P3V||GND3P3V|||-} ==== HPC Row E ==== {| C26||IO_L6P_T0_35||LA27_P||class="wikitable"
|-
|-
| C28E1||DGND||GND||
|-
| C29E2||DGNDIO_L14P_T2_AD4P_SRCC_35||GNDHA01_P_CC||
|-
| C30E3||I2C0_SCLIO_L14N_T2_AD4N_SRCC_35||SCLHA01_N_CC||
|-
| C31E4||I2C0_SDADGND||SDAGND||
|-
| C32E5||DGND||GND||
|-
| C33E6||DGNDIO_L20P_T3_AD6P_35||GNDHA05_P||
|-
| C34E7||GA0IO_L20N_T3_AD6N_35||GA0HA05_N||
|-
| C35E8||FMC_12P0VDGND||12P0VGND||
|-
| C36E9||DGNDIO_L24P_T3_AD15P_35||GNDHA09_P||
|-
| C37E10||FMC_12P0VIO_L24N_T3_AD15N_35||12P0VHA09_N||
|-
| C38E11||DGND||GND||
|-
| C39E12||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHA13_P||
|-
| C40E13||DGND||GND<span style="color:#ff0000">not connected</span>||HA13_N|} ==== LPC Row D ==== {| class="wikitable"
|-
|-
| D1E15||IO_25_VRP_34<span style="color:#ff0000">not connected</span>||PG_C2MHA16_P||
|-
| D2E16||DGND<span style="color:#ff0000">not connected</span>||GNDHA16_N||
|-
| D3E17||DGND||GND||
|-
| D4E18||MGTREFCLK0P<span style="color:#ff0000">not connected</span>||GBTCLK0_M2C_PHA20_P||
|-
| D5E19||MGTREFCLK0N<span style="color:#ff0000">not connected</span>||GBTCLK0_M2C_NHA20_N||
|-
| D6E20||DGND||GND||
|-
| D7E21||DGND<span style="color:#ff0000">not connected</span>||GNDHB03_P||
|-
| D8E22||IO_L14P_T2_SRCC_34<span style="color:#ff0000">not connected</span>||LA01_P_CCHB03_N||
|-
| D9E23||IO_L14N_T2_SRCC_34DGND||LA01_N_CCGND||
|-
| D10E24||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_P||
|-
| D11E25||IO_L9P_T1_DQS_34<span style="color:#ff0000">not connected</span>||LA05_PHB05_N||
|-
| D12E26||IO_L9N_T1_DQS_34DGND||LA05_NGND||
|-
| D13E27||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_P||
|-
| D14E28||IO_L6P_T0_34<span style="color:#ff0000">not connected</span>||LA09_PHB09_N||
|-
| D15E29||IO_L6N_T0_VREF_34DGND||LA09_NGND||
|-
| D16E30||DGND<span style="color:#ff0000">not connected</span>||GNDHB13_P||
|-
| D17E31||IO_L20P_T3_34<span style="color:#ff0000">not connected</span>||LA13_PHB13_N||
|-
| D18E32||IO_L20N_T3_34DGND||LA13_NGND||
|-
| D19E33||DGND<span style="color:#ff0000">not connected</span>||GNDHB19_P||
|-
| D20E34||IO_L15P_T2_DQS_34<span style="color:#ff0000">not connected</span>||LA17_P_CCHB19_N||
|-
| D21E35||IO_L15N_T2_DQS_34DGND||LA17_N_CCGND||
|-
| D22E36||DGND<span style="color:#ff0000">not connected</span>||GNDHB21_P||
|-
| D23E37||IO_L2P_T0_AD8P_35<span style="color:#ff0000">not connected</span>||LA23_PHB21_N||
|-
| D24E38||IO_L2N_T0_AD8N_35DGND||LA23_NGND||
|-
| D25E39||DGNDFMC_VADJ||GNDVADJ||
|-
| D26E40||IO_L5P_T0_AD9P_35DGND||LA26_PGND|||} ==== HPC Row F ==== {| class="wikitable"
|-
|-
| D28F1||DGNDIO_0_VRN_35||GNDPG_M2C||
|-
| D29F2||JTAG_TCKDGND||TCKGND||
|-
| D30F3||JTAG_TDIDGND||TDIGND||
|-
| D31F4||FMC_TDO_ZYNQ_TDIIO_L13P_T2_MRCC_35||TDOHA00_P_CC||
|-
| D32F5||FMC_3P3VAUXIO_L13N_T2_MRCC_35||3P3VAUXHA00_N_CC||
|-
| D33F6||JTAG_TMSDGND||TMSGND||
|-
| D34F7||JTAG_TRSTnIO_L19P_T3_35||TRST_LHA04_P||
|-
| D35F8||GA0IO_L19N_T3_VREF_35||GA1HA04_N||
|-
| D36F9||FMC_3P3VDGND||3P3VGND||
|-
| D37F10||DGNDIO_L23P_T3_35||GNDHA08_P||
|-
| D38F11||FMC_3P3VIO_L23N_T3_35||3P3VHA08_N||
|-
| D39F12||DGND||GND||
|-
| D40F13||FMC_3P3V||3P3V<span style="color:#ff0000">not connected</span>||HA12_P|} ==== HPC Row E ==== {| class="wikitable"
|-
|-
| E1F15||DGND||GND||
|-
| E2F16||IO_L14P_T2_AD4P_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_P_CCHA15_P||
|-
| E3F17||IO_L14N_T2_AD4N_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_N_CCHA15_N||
|-
| E4F18||DGND||GND||
|-
| E5F19||DGND<span style="color:#ff0000">not connected</span>||GNDHA19_P||
|-
| E6F20||IO_L20P_T3_AD6P_35<span style="color:#ff0000">not connected</span>||HA05_PHA19_N||
|-
| E7F21||IO_L20N_T3_AD6N_35DGND||HA05_NGND||
|-
| E8F22||DGND<span style="color:#ff0000">not connected</span>||GNDHB02_P||
|-
| E9F23||IO_L24P_T3_AD15P_35<span style="color:#ff0000">not connected</span>||HA09_PHB02_N||
|-
| E10F24||IO_L24N_T3_AD15N_35DGND||HA09_NGND||
|-
| E11F25||DGND<span style="color:#ff0000">not connected</span>||GNDHB04_P||
|-
| E12F26||<span style="color:#ff0000">not connected</span>||HA13_PHB04_N||
|-
| E13F27||<span style="color:#ff0000">not connected</span>DGND||HA13_NGND||
|-
| E14F28||DGND<span style="color:#ff0000">not connected</span>||GNDHB08_P||
|-
| E15F29||<span style="color:#ff0000">not connected</span>||HA16_PHB08_N||
|-
| E16F30||<span style="color:#ff0000">not connected</span>DGND||HA16_NGND||
|-
| E17F31||DGND<span style="color:#ff0000">not connected</span>||GNDHB12_P||
|-
| E18F32||<span style="color:#ff0000">not connected</span>||HA20_PHB12_N||
|-
| E19F33||<span style="color:#ff0000">not connected</span>DGND||HA20_NGND||
|-
| E20F34||DGND<span style="color:#ff0000">not connected</span>||GNDHB16_P||
|-
| E21F35||<span style="color:#ff0000">not connected</span>||HB03_PHB16_N||
|-
| E22F36||<span style="color:#ff0000">not connected</span>DGND||HB03_NGND||
|-
| E23F37||DGND<span style="color:#ff0000">not connected</span>||GNDHB20_P||
|-
| E24F38||<span style="color:#ff0000">not connected</span>||HB05_PHB20_N||
|-
| E25F39||<span style="color:#ff0000">not connected</span>DGND||HB05_NGND||
|-
| E26F40||DGNDFMC_VADJ||GNDVADJ|||} ==== LPC Row G ==== {| class="wikitable"
|-
|-
| E28G1||<span style="color:#ff0000">not connected</span>DGND||HB09_NGND||
|-
| E29G2||DGNDIO_L11P_T1_SRCC_34||GNDCLK0_C2M_P||
|-
| E30G3||<span style="color:#ff0000">not connected</span>IO_L11N_T1_SRCC_34||HB13_PCLK0_C2M_N||
|-
| E31G4||<span style="color:#ff0000">not connected</span>DGND||HB13_NGND||
|-
| E32G5||DGND||GND||
|-
| E33G6||<span style="color:#ff0000">not connected</span>IO_L13P_T1_MRCC_34||HB19_PLA00_P_CC||
|-
| E34G7||<span style="color:#ff0000">not connected</span>IO_L13N_T1_MRCC_34||HB19_NLA00_N_CC||
|-
| E35G8||DGND||GND||
|-
| E36G9||<span style="color:#ff0000">not connected</span>IO_L4P_T0_34||HB21_PLA03_P||
|-
| E37G10||<span style="color:#ff0000">not connected</span>IO_L4N_T0_34||HB21_NLA03_N||
|-
| E38G11||DGND||GND||
|-
| E39G12||FMC_VADJIO_L3P_T0_DQS_PUDC_B_34||VADJLA08_P||
|-
| E40G13||DGNDIO_L3N_T0_DQS_34||GNDLA08_N|||} ==== HPC Row F ==== {| class="wikitable"
|-
|-
| F1G15||IO_0_VRN_35IO_L22P_T3_34||PG_M2CLA12_P||
|-
| F2G16||DGNDIO_L22N_T3_34||GNDLA12_N||
|-
| F3G17||DGND||GND||
|-
| F4G18||IO_L13P_T2_MRCC_35IO_L19P_T3_34||HA00_P_CCLA16_P||
|-
| F5G19||IO_L13N_T2_MRCC_35IO_L19N_T3_VREF_34||HA00_N_CCLA16_N||
|-
| F6G20||DGND||GND||
|-
| F7G21||IO_L19P_T3_35IO_L17P_T2_34||HA04_PLA20_P||
|-
| F8G22||IO_L19N_T3_VREF_35IO_L17N_T2_34||HA04_NLA20_N||
|-
| F9G23||DGND||GND||
|-
| F10G24||IO_L23P_T3_35IO_L1P_T0_AD0P_35||HA08_PLA22_P||
|-
| F11G25||IO_L23N_T3_35IO_L1N_T0_AD0N_35||HA08_NLA22_N||
|-
| F12G26||DGND||GND||
|-
| F13G27||<span style="color:#ff0000">not connected</span>IO_L4P_T0_35||HA12_PLA25_P||
|-
| F14G28||<span style="color:#ff0000">not connected</span>IO_L4N_T0_35||HA12_NLA25_N||
|-
| F15G29||DGND||GND||
|-
| F16G30||<span style="color:#ff0000">not connected</span>IO_L8P_T1_AD10P_35||HA15_PLA29_P||
|-
| F17G31||<span style="color:#ff0000">not connected</span>IO_L8N_T1_AD10N_35||HA15_NLA29_N||
|-
| F18G32||DGND||GND||
|-
| F19G33||<span style="color:#ff0000">not connected</span>IO_L10P_T1_AD11P_35||HA19_PLA31_P||
|-
| F20G34||<span style="color:#ff0000">not connected</span>IO_L10N_T1_AD11N_35||HA19_NLA31_N||
|-
| F21G35||DGND||GND||
|-
| F22G36||<span style="color:#ff0000">not connected</span>IO_L16P_T2_35||HB02_PLA33_P||
|-
| F23G37||<span style="color:#ff0000">not connected</span>IO_L16N_T2_35||HB02_NLA33_N||
|-
| F24G38||DGND||GND||
|-
| F25G39||<span style="color:#ff0000">not connected</span>FMC_VADJ||HB04_PVADJ||
|-
| F26G40||<span style="color:#ff0000">not connected</span>DGND||GND||HB04_N|} ==== LPC Row H ==== {|class="wikitable"
|-
|-
| F28H1||<span style="color:#ff0000">not connected</span>FMC_VREF_A_M2C||HB08_PVREF_A_M2C||
|-
| F29H2||<span style="color:#ff0000">not connected</span>FMC_PRSNT_M2C_L||HB08_NPRSNT_M2C_L||
|-
| F30H3||DGND||GND||
|-
| F31H4||<span style="color:#ff0000">not connected</span>IO_L12P_T1_MRCC_34||HB12_PCLK0_M2C_P||
|-
| F32H5||<span style="color:#ff0000">not connected</span>IO_L12N_T1_MRCC_34||HB12_NCLK0_M2C_N||
|-
| F33H6||DGND||GND||
|-
| F34H7||<span style="color:#ff0000">not connected</span>IO_L7P_T1_34||HB16_PLA02_P||
|-
| F35H8||<span style="color:#ff0000">not connected</span>IO_L7N_T1_34||HB16_NLA02_N||
|-
| F36H9||DGND||GND||
|-
| F37H10||<span style="color:#ff0000">not connected</span>IO_L5P_T0_34||HB20_PLA04_P||
|-
| F38H11||<span style="color:#ff0000">not connected</span>IO_L5N_T0_34||HB20_NLA04_N||
|-
| F39H12||DGND||GND||
|-
| F40H13||FMC_VADJIO_L8P_T1_34||VADJLA07_P|||} ==== LPC Row G ==== {| class="wikitable"
|-
|-
| G1H15||DGND||GND||
|-
| G2H16||IO_L11P_T1_SRCC_34IO_L21P_T3_DQS_34||CLK0_C2M_PLA11_P||
|-
| G3H17||IO_L11N_T1_SRCC_34IO_L21N_T3_DQS_34||CLK0_C2M_NLA11_N||
|-
| G4H18||DGND||GND||
|-
| G5H19||DGNDIO_L18P_T2_34||GNDLA15_P||
|-
| G6H20||IO_L13P_T1_MRCC_34IO_L18N_T2_34||LA00_P_CCLA15_N||
|-
| G7H21||IO_L13N_T1_MRCC_34DGND||LA00_N_CCGND||
|-
| G8H22||DGNDIO_L24P_T3_34||GNDLA19_P||
|-
| G9H23||IO_L4P_T0_34IO_L24N_T3_34||LA03_PLA19_N||
|-
| G10H24||IO_L4N_T0_34DGND||LA03_NGND||
|-
| G11H25||DGNDIO_L10P_T1_34||GNDLA21_P||
|-
| G12H26||IO_L3P_T0_DQS_PUDC_B_34IO_L10N_T1_34||LA08_PLA21_N||
|-
| G13H27||IO_L3N_T0_DQS_34DGND||LA08_NGND||
|-
| G14H28||DGNDIO_L3P_T0_DQS_AD1P_35||GNDLA24_P||
|-
| G15H29||IO_L22P_T3_34IO_L3N_T0_DQS_AD1N_35||LA12_PLA24_N||
|-
| G16H30||IO_L22N_T3_34DGND||LA12_NGND||
|-
| G17H31||DGNDIO_L7P_T1_AD2P_35||GNDLA28_P||
|-
| G18H32||IO_L19P_T3_34IO_L7N_T1_AD2N_35||LA16_PLA28_N||
|-
| G19H33||IO_L19N_T3_VREF_34DGND||LA16_NGND||
|-
| G20H34||DGNDIO_L9P_T1_DQS_AD3P_35||GNDLA30_P||
|-
| G21H35||IO_L17P_T2_34IO_L9N_T1_DQS_AD3N_35||LA20_PLA30_N||
|-
| G22H36||IO_L17N_T2_34DGND||LA20_NGND||
|-
| G23H37||DGNDIO_L15P_T2_DQS_AD12P_35||GNDLA32_P||
|-
| G24H38||IO_L1P_T0_AD0P_35IO_L15N_T2_DQS_AD12N_35||LA22_PLA32_N||
|-
| G25H39||IO_L1N_T0_AD0N_35DGND||LA22_NGND||
|-
| G26H40||DGNDFMC_VADJ||GNDVADJ|||} ==== HPC Row J ==== {| class="wikitable"
|-
|-
| G28J1||IO_L4N_T0_35DGND||LA25_NGND||
|-
| G29J2||DGNDIO_L11P_T1_SRCC_35||GNDCLK1_C2M_P||
|-
| G30J3||IO_L8P_T1_AD10P_35IO_L11N_T1_SRCC_35||LA29_PCLK1_C2M_N||
|-
| G31J4||IO_L8N_T1_AD10N_35DGND||LA29_NGND||
|-
| G32J5||DGND||GND||
|-
| G33J6||IO_L10P_T1_AD11P_35IO_L18P_T2_AD13P_35||LA31_PHA03_P||
|-
| G34J7||IO_L10N_T1_AD11N_35IO_L18N_T2_AD13N_35||LA31_NHA03_N||
|-
| G35J8||DGND||GND||
|-
| G36J9||IO_L16P_T2_35IO_L22P_T3_AD7P_35||LA33_PHA07_P||
|-
| G37J10||IO_L16N_T2_35IO_L22N_T3_AD7N_35||LA33_NHA07_N||
|-
| G38J11||DGND||GND||
|-
| G39J12||FMC_VADJ<span style="color:#ff0000">not connected</span>||VADJHA11_P||
|-
| G40J13||DGND||GND<span style="color:#ff0000">not connected</span>||HA11_N|} ==== LPC Row H ==== {| class="wikitable"
|-
|-
| H1J15||FMC_VREF_A_M2C<span style="color:#ff0000">not connected</span>||VREF_A_M2CHA14_P||
|-
| H2J16||FMC_PRSNT_M2C_L<span style="color:#ff0000">not connected</span>||PRSNT_M2C_LHA14_N||
|-
| H3J17||DGND||GND||
|-
| H4J18||IO_L12P_T1_MRCC_34<span style="color:#ff0000">not connected</span>||CLK0_M2C_PHA18_P||
|-
| H5J19||IO_L12N_T1_MRCC_34<span style="color:#ff0000">not connected</span>||CLK0_M2C_NHA18_N||
|-
| H6J20||DGND||GND||
|-
| H7J21||IO_L7P_T1_34<span style="color:#ff0000">not connected</span>||LA02_PHA22_P||
|-
| H8J22||IO_L7N_T1_34<span style="color:#ff0000">not connected</span>||LA02_NHA22_N||
|-
| H9J23||DGND||GND||
|-
| H10J24||IO_L5P_T0_34<span style="color:#ff0000">not connected</span>||LA04_PHB01_P||
|-
| H11J25||IO_L5N_T0_34<span style="color:#ff0000">not connected</span>||LA04_NHB01_N||
|-
| H12J26||DGND||GND||
|-
| H13J27||IO_L8P_T1_34<span style="color:#ff0000">not connected</span>||LA07_PHB07_P||
|-
| H14J28||IO_L8N_T1_34<span style="color:#ff0000">not connected</span>||LA07_NHB07_N||
|-
| H15J29||DGND||GND||
|-
| H16J30||IO_L21P_T3_DQS_34<span style="color:#ff0000">not connected</span>||LA11_PHB11_P||
|-
| H17J31||IO_L21N_T3_DQS_34<span style="color:#ff0000">not connected</span>||LA11_NHB11_N||
|-
| H18J32||DGND||GND||
|-
| H19J33||IO_L18P_T2_34<span style="color:#ff0000">not connected</span>||LA15_PHB15_P||
|-
| H20J34||IO_L18N_T2_34<span style="color:#ff0000">not connected</span>||LA15_NHB15_N||
|-
| H21J35||DGND||GND||
|-
| H22J36||IO_L24P_T3_34<span style="color:#ff0000">not connected</span>||LA19_PHB18_P||
|-
| H23J37||IO_L24N_T3_34<span style="color:#ff0000">not connected</span>||LA19_NHB18_N||
|-
| H24J38||DGND||GND||
|-
| H25J39||IO_L10P_T1_34<span style="color:#ff0000">not connected</span>||LA21_PVIO_B_M2C||
|-
| H26J40||IO_L10N_T1_34DGND||LA21_NGND|||} ==== HPC Row K ==== {| class="wikitable"
|-
|-
| H28K1||IO_L3P_T0_DQS_AD1P_35<span style="color:#ff0000">not connected</span>||LA24_PVREF_B_M2C||
|-
| H29K2||IO_L3N_T0_DQS_AD1N_35DGND||LA24_NGND||
|-
| H30K3||DGND||GND||
|-
| H31K4||IO_L7P_T1_AD2P_35IO_L12P_T1_MRCC_35||LA28_PCLK1_M2C_P||
|-
| H32K5||IO_L7N_T1_AD2N_35IO_L12N_T1_MRCC_35||LA28_NCLK1_M2C_N||
|-
| H33K6||DGND||GND||
|-
| H34K7||IO_L9P_T1_DQS_AD3P_35IO_L17P_T2_AD5P_35||LA30_PHA02_P||
|-
| H35K8||IO_L9N_T1_DQS_AD3N_35IO_L17N_T2_AD5N_35||LA30_NHA02_N||
|-
| H36K9||DGND||GND||
|-
| H37K10||IO_L15P_T2_DQS_AD12P_35IO_L21P_T3_DQS_AD14P_35||LA32_PHA06_P||
|-
| H38K11||IO_L15N_T2_DQS_AD12N_35IO_L21N_T3_DQS_AD14N_35||LA32_NHA06_N||
|-
| H39K12||DGND||GND||
|-
| H40K13||FMC_VADJIO_25_VRP_35||VADJHA10_P|||} ==== HPC Row J ==== {| class="wikitable"
|-
|-
| J1K15||DGND||GND||
|-
| J2K16||IO_L11P_T1_SRCC_35<span style="color:#ff0000">not connected</span>||CLK1_C2M_PHA17_P_CC||
|-
| J3K17||IO_L11N_T1_SRCC_35<span style="color:#ff0000">not connected</span>||CLK1_C2M_NHA17_N_CC||
|-
| J4K18||DGND||GND||
|-
| J5K19||DGND<span style="color:#ff0000">not connected</span>||GNDHA21_P||
|-
| J6K20||IO_L18P_T2_AD13P_35<span style="color:#ff0000">not connected</span>||HA03_PHA21_N||
|-
| J7K21||IO_L18N_T2_AD13N_35DGND||HA03_NGND||
|-
| J8K22||DGND<span style="color:#ff0000">not connected</span>||GNDHA23_P||
|-
| J9K23||IO_L22P_T3_AD7P_35<span style="color:#ff0000">not connected</span>||HA07_PHA23_N||
|-
| J10K24||IO_L22N_T3_AD7N_35DGND||HA07_NGND||
|-
| J11K25||DGND<span style="color:#ff0000">not connected</span>||GNDHB00_P_CC||
|-
| J12K26||<span style="color:#ff0000">not connected</span>||HA11_PHB00_N_CC||
|-
| J13K27||<span style="color:#ff0000">not connected</span>DGND||HA11_NGND||
|-
| J14K28||DGND<span style="color:#ff0000">not connected</span>||GNDHB06_P_CC||
|-
| J15K29||<span style="color:#ff0000">not connected</span>||HA14_PHB06_N_CC||
|-
| J16K30||<span style="color:#ff0000">not connected</span>DGND||HA14_NGND||
|-
| J17K31||DGND<span style="color:#ff0000">not connected</span>||GNDHB10_P||
|-
| J18K32||<span style="color:#ff0000">not connected</span>||HA18_PHB10_N||
|-
| J19K33||<span style="color:#ff0000">not connected</span>DGND||HA18_NGND||
|-
| J20K34||DGND<span style="color:#ff0000">not connected</span>||GNDHB14_P||
|-
| J21K35||<span style="color:#ff0000">not connected</span>||HA22_PHB14_N||
|-
| J22K36||<span style="color:#ff0000">not connected</span>DGND||HA22_NGND||
|-
| J23K37||DGND<span style="color:#ff0000">not connected</span>||GNDHB17_P_CC||
|-
| J24K38||<span style="color:#ff0000">not connected</span>||HB01_PHB17_N_CC||
|-
| J25K39||<span style="color:#ff0000">not connected</span>DGND||HB01_NGND||
|-
| J26K40||DGND<span style="color:#ff0000">not connected</span>||GNDVIO_B_M2C|||} === Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
|-
| J281, 4, 9, 12 ||<span style="color:#ff0000">not connected</span>DGND ||HB07_NGround ||-
|-
| J292 ||DGNDSPI0_CS0n ||GND- ||-
|-
| J303 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_SCLK/span>NAND_IO1 ||HB11_P- ||-
|-
| J315 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ0/span>NAND_ALE ||HB11_N- ||-
|-
| J326 ||DGNDNAND_CS0/SPI0_CS1 ||GND- ||-
|-
| J337 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ2/span>NAND_IO2 ||HB15_P- ||-
|-
| J348 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ1/span>NAND_WE ||HB15_N- ||-
|-
| J3510 ||DGNDZYNQ_SPI0_DQ3/NAND_IO0 ||GND- ||-
|-
| J3611 ||<span style="color:#ff0000">not connected</span>ZYNQ_NAND_RD_B ||HB18_P|||-| J37||<span style="color:#ff0000">not connected</span>||HB18_N|||-| J38||DGND||GND|||-| J39||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|-
|}
==== HPC Row K Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
| K11 ||<span style="color:#ff0000">not connected</span>MON_VCCPLL ||VREF_B_M2C- ||-
|-
| K22 ||DGNDMON_3.3V ||GND- ||-
|-
| K33 ||DGNDMON_XADC_VCC ||GND- ||-
|-
| K44 ||IO_L12P_T1_MRCC_35MON_1V2_ETH ||CLK1_M2C_P- ||-
|-
| K55 ||IO_L12N_T1_MRCC_35MON_FPGA_VDDIO_BANK35 ||CLK1_M2C_N- ||-
|-
| K66 ||DGNDMON_VDDQ_1V5 ||GND- ||-
|-
| K77 ||IO_L17P_T2_AD5P_35MON_FPGA_VDDIO_BANK34 ||HA02_P- ||-
|-
| K88 ||IO_L17N_T2_AD5N_35MON_1.8V ||HA02_N- ||-
|-
| K99 ||DGNDMON_FPGA_VDDIO_BANK13 ||GND- ||-
|-
| K1010 ||IO_L21P_T3_DQS_AD14P_35MON_1.0V ||HA06_P- ||-
|-
| K1111 ||IO_L21N_T3_DQS_AD14N_35MON_1.8V_IO ||HA06_N- ||-
|-
| K1212 ||DGNDMON_MGTAVCC ||GND- ||-
|-
| K1313 ||IO_25_VRP_35MON_MGTAVTT ||HA10_P- ||-
|-
| K1414 ||<span style="color:#ff0000">not connected</span>MON_MGTAVCCAUX ||HA10_N- ||-
|-
| K1515, 16 ||DGND||GNDGround ||-
|-
| K16|} ==== Ethernet GPIO - JP18 ====JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|<span styleclass="color:#ff0000wikitable">not connected</span>||HA17_P_CC||
|-
|-
| K181, 2, 5,<br>6, 16||DGND||GNDGround ||-
|-
| K193 ||<span style="color:#ff0000">not connected</span>CLK125_NDO||HA21_P- ||-
|-
| K204 ||<span style="color:#ff0000">not connected</span>ETH1_CLK125_NDO ||HA21_N- ||-
|-
| K217 ||DGNDETH_MDC ||GND- ||-
|-
| K228 ||<span style="color:#ff0000">not connected</span>ETH1_MDC ||HA23_P- ||-
|-
| K239 ||<span style="color:#ff0000">not connected</span>ETH_MDIO ||HA23_N- ||-
|-
| K2410 ||DGNDETH1_MDIO ||GND- ||-
|-
| K2511 ||<span style="color:#ff0000">not connected</span>ETH_INTn ||HB00_P_CC- ||-
|-
| K2612 ||<span style="color:#ff0000">not connected</span>ETH1_INTn ||HB00_N_CC- ||-
|-
| K2713 ||DGNDPS_MIO51_501 ||GND- ||-
|-
| K2814 ||<span style="color:#ff0000">not connected</span>ETH1_RESETn ||HB06_P_CC- ||-
|-
| K2915 ||<span style="color:#ff0000">not connected</span>PS_MIO50_501 ||HB06_N_CC- ||-
|-
| K30||DGND||GND|} ==== SPI,NAND - JP19 ====JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
|-
!Pin# !Pin name!Function!Notes|-|1, 11, 12|| K31DGND ||<span style="color:#ff0000">not connected</span>Ground || -|-|2 || NAND_BUSY||HB10_P- ||-
|-
| K323 ||<span style="color:#ff0000">not connected</span>ZYNQ_NAND_CLE ||HB10_N- ||-
|-
| K334 ||DGNDNAND_IO3 ||GND- ||-
|-
| K345 ||<span style="color:#ff0000">not connected</span>NAND_IO4 ||HB14_P- ||-
|-
| K356 ||<span style="color:#ff0000">not connected</span>NAND_IO5 ||HB14_N- ||-
|-
| K367 ||DGNDNAND_IO6 ||GND- ||-
|-
| K378 ||<span style="color:#ff0000">not connected</span>NAND_IO7 ||HB17_P_CC- ||-
|-
| K389 ||<span style="color:#ff0000">not connected</span>CONN_SPI_RSTn ||HB17_N_CC- ||-
|-
| K3910 ||DGNDMEM_WPn ||GND- ||-
|-
|}
=== Pin strip connectors === ==== SPIFPGA, WatchDog, RTC,NAND RST - JP13 JP22 ==== JP13 JP22 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, || FPGA_INIT_B|| - || -|-|2 || RTC_32KHZ || - || -|-|3 || FPGA_PROGRAM_B|| - || -|-|4|| RTC_RST || - || -|-|5 || FPGA_DONE || - || -|-|6 || RTC_INT/SQW || - || -|-|7, 9, 12 8 || DGND || Ground || -
|-
|2 9 || SPI0_CS0n WD_SET0 || - || -
|-
|3 10 || ZYNQ_SPI0_SCLK/NAND_IO1 SYS_RSTn || - || -
|-
|5 11 || ZYNQ_SPI0_DQ0/NAND_ALE WD_SET1 || - || -
|-
|6 12 || NAND_CS0/SPI0_CS1 PORSTn || - || -
|-
|7 13 || ZYNQ_SPI0_DQ2/NAND_IO2 WD_SET2 || - || -
|-
|8 14 || ZYNQ_SPI0_DQ1/NAND_WE MRSTn || - || -
|-
|10 15 || ZYNQ_SPI0_DQ3/NAND_IO0 PS_MIO15_500 || - || -
|-
|11 16 || ZYNQ_NAND_RD_B CB_PWR_GOOD || - || -
|-
|}
==== Voltage Monitor AUX PINs - JP15 JP29 ==== JP15 JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 || MON_VCCPLL EVB_1.8V || - || -
|-
|2 || MON_33.3V || - || -
|-
|3 || MON_XADC_VCC PS_I2C0_DAT|| - || -
|-
|4 || MON_1V2_ETH I2C0_SDA || - || -
|-
|5 || MON_FPGA_VDDIO_BANK35 PS_I2C0_CK || - || -
|-
|6 || MON_VDDQ_1V5 I2C0_SCL || - || -
|-
|7 , 8,<br>13 || MON_FPGA_VDDIO_BANK34 DGND || - Ground || -
|-
|8 9 || MON_1.8V EXT_VMON2_V1 || - || -Mount option
|-
|9 10, 16 || MON_FPGA_VDDIO_BANK13 XADC_AGND || - Analog Ground || -
|-
|10 11 || MON_1.0V EXT_VMON2_V2 || - || -Mount option
|-
|11 12 || MON_1.8V_IO XADC_VN_R || - || -
|-
|12 14 || MON_MGTAVCC XADC_VP_R || - || -
|-
|13 15 || MON_MGTAVTT INA_ALERT || - || -
|-
|14 || MON_MGTAVCCAUX || - || -} Please note that:|-|15, 16 || DGND || Ground || -* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA|-** resistive touch screen controller for LCD screen|}** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
JP30:
{| class="wikitable"
|-
!Notes
|-
|1, 2, 5,<br>6, 16|| DGND FPGA_BANK35_AD0N || Ground AD0_N || -Mount option
|-
|3 || CLK125_NDOFPGA_BANK35_AD1P || - AD1_P || -Mount option
|-
|4 || ETH1_CLK125_NDO FPGA_BANK35_AD0P || - AD0_P || -Mount option
|-
|7 5 || ETH_MDC FPGA_BANK35_AD1N || - AD1_N || -Mount option
|-
|8 || ETH1_MDC FPGA_BANK35_AD2P || - AD2_P || -Mount option
|-
|9 || ETH_MDIO FPGA_BANK35_AD3P || - AD3_P || -Mount option
|-
|10 || ETH1_MDIO FPGA_BANK35_AD2N || - AD2_N || -Mount option
|-
|11 ||ETH_INTn FPGA_BANK35_AD3N || - AD3_N || -Mount option
|-
|12 14 || ETH1_INTn FPGA_BANK35_AD4P || - AD4_P || -Mount option
|-
|13 15 || PS_MIO51_501 FPGA_BANK35_AD5P || - AD5_P || -Mount option
|-
|14 16 || ETH1_RESETn FPGA_BANK35_AD4N || - AD4_N || -Mount option
|-
|15 1, 6, 7,<br>12, 13 || PS_MIO50_501 DGND || - || -
|-
|}
{| class="wikitable"
|-
!Notes
|-
|1, 11, 12|| DGND FPGA_BANK35_AD5N || Ground AD5_N || -Mount option
|-
|2 4 || NAND_BUSYFPGA_BANK35_AD6P || - AD6_P || -Mount option
|-
|3 5 || ZYNQ_NAND_CLE FPGA_BANK35_AD7P || - AD7_P || -Mount option
|-
|4 6 || NAND_IO3 FPGA_BANK35_AD6N || - AD6_N || -Mount option
|-
|5 7 || NAND_IO4 FPGA_BANK35_AD7N || - AD7_N || -Mount option
|-
|6 10 || NAND_IO5 FPGA_BANK35_AD8P || - AD8_P || -Mount option
|-
|7 11 || NAND_IO6 FPGA_BANK35_AD9P || - AD9_P || -Mount option
|-
|8 12 || NAND_IO7 FPGA_BANK35_AD8N || - AD8_N || -Mount option
|-
|9 13 || CONN_SPI_RSTn FPGA_BANK35_AD9N || - AD9_N || -Mount option
|-
|10 16 || MEM_WPn FPGA_BANK35_AD10P || AD10_P || Mount option|-|2, 3, 8,<br>9, 14, 15 || DGND || - || -
|-
|}
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_INIT_BFPGA_BANK35_AD11P || - AD11_P || -Mount option
|-
|2 || RTC_32KHZ FPGA_BANK35_AD10N || - AD10_N || -Mount option
|-
|3 || FPGA_PROGRAM_BFPGA_BANK35_AD11N || - AD11_N || -Mount option
|-
|4 6 || RTC_RST FPGA_BANK35_AD12P || - AD12_P || -Mount option
|-
|5 7 || FPGA_DONE FPGA_BANK35_AD13P || - AD13_P || -Mount option
|-
|6 8 || RTC_INT/SQW FPGA_BANK35_AD12N || - AD12_N || -Mount option
|-
|7, 8 9 || DGND FPGA_BANK35_AD13N || Ground AD13_N || -Mount option
|-
|9 12 || WD_SET0 FPGA_BANK35_AD14P || - AD14_P || -Mount option
|-
|10 13 || SYS_RSTn FPGA_BANK35_AD15P || - AD15_P || -Mount option
|-
|11 14 || WD_SET1 FPGA_BANK35_AD14N || - AD14_N || -Mount option
|-
|12 15 || PORSTn FPGA_BANK35_AD15N || - AD15_N || -Mount option
|-
|13 4, 5, 10,<br>11, 16 || WD_SET2 DGND || - || -
|-
|14 || MRSTn || } === Digilent Pmod™ Compatible headers === Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - || allows to quickly connect several pre-built I/O modules to PL:|-** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812|15 || PS_MIO15_500 || - || ** http://www.maximintegrated.com/products/evkits/fpga-modules/|-* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector |16 || CB_PWR_GOOD || - || -|==== Digilent Pmod™ Compatible -|}JP17 ====
{| class="wikitable"
!Notes
|-
|1 || EVB_1.8V PMOD_A0 || - || -
|-
|2 || 3.3V PMOD_A4 || - || -
|-
|3 || PS_I2C0_DATPMOD_A1 || - || -
|-
|4 || I2C0_SDA PMOD_A5 || - || -
|-
|5 || PS_I2C0_CK PMOD_A2 || - || -
|-
|6 || I2C0_SCL PMOD_A6 || - || -
|-
|7, 8,<br>13 || DGND PMOD_A3 || Ground || -
|-
|9 8 || EXT_VMON2_V1 PMOD_A7 || - || Mount option-
|-
|9, 10, 16 || XADC_AGND DGND || Analog Ground || -
|-
|11 || EXT_VMON2_V2 || - || Mount option|-|, 12 || XADC_VN_R || - || -|-|14 || XADC_VP_R || - || -|-|15 || INA_ALERT 3.3V || - || -
|-
|}
{| class="wikitable"
|-
!Notes
|-
|2 1 || FPGA_BANK35_AD0N PMOD_B0 || AD0_N - || Mount option-
|-
|3 2 || FPGA_BANK35_AD1P PMOD_B4 || AD1_P - || Mount option-
|-
|4 3 || FPGA_BANK35_AD0P PMOD_B1 || AD0_P - || Mount option-
|-
|5 4 || FPGA_BANK35_AD1N PMOD_B5 || AD1_N - || Mount option-
|-
|8 5 || FPGA_BANK35_AD2P PMOD_B2 || AD2_P - || Mount option-
|-
|9 6 || FPGA_BANK35_AD3P PMOD_B6 || AD3_P - || Mount option-
|-
|10 7 || FPGA_BANK35_AD2N PMOD_B3 || AD2_N - || Mount option-
|-
|11 8 || FPGA_BANK35_AD3N PMOD_B7 || AD3_N - || Mount option-
|-
|14 9, 10 || FPGA_BANK35_AD4P DGND || AD4_P Ground || Mount option-
|-
|15 || FPGA_BANK35_AD5P || AD5_P || Mount option|-|16 || FPGA_BANK35_AD4N || AD4_N || Mount option|-|1, 6, 711,<br>12, 13 || DGND 3.3V || - || -
|-
|}
===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
==PL's I/O voltage selections==
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
*'''voltage selection must be done before powering up the board'''.
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
|-
|-
|rowspan="2" |BoraX| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1 .2 - 3.3V)|style="text-align: center;" | FPGA_BANK35_AD5N User defined|style="text-align: center;" | AD5_N HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | Mount optionUser defined
|-
|4 style="text-align: center;" |7030(SBG485 package)| FPGA_BANK35_AD6P style="text-align: center;" |HP(1.2 - 1.8V)| AD6_P style="text-align: center;" |User defined| Mount optionstyle="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined
|-
|5 rowspan="2" |Bora Lite| FPGA_BANK35_AD7P style="text-align: center;" |7007S/7010(CLG400 package)| AD7_P style="text-align: center;" |HR(1.2 - 3.3V)| Mount optionstyle="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined
|-
|6 style="text-align: center;" |7014S/7020(CLG400 package)| FPGA_BANK35_AD6N style="text-align: center;" |HR(1.2 - 3.3V)| AD6_N style="text-align: center;" |User defined| Mount style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance ===BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''. Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details. Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default optionfor BXELK)===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" |7 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP25.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD7N JP25.3-4! style="text-align: center; font-weight: bold;" |JP25.5-6! style="text-align: center; font-weight: bold;" | AD7_N JP25.7-8! style="text-align: center; font-weight: bold;" |JP25.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP25.11-12
|-
|10 style="text-align: center;" |1.2| FPGA_BANK35_AD8P style="text-align: center;" |open| AD8_P style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|11 style="text-align: center;" |1.5| FPGA_BANK35_AD9P style="text-align: center;" |open| AD9_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|12 style="text-align: center;" |1.8| FPGA_BANK35_AD8N style="text-align: center;" |open| AD8_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|13 style="text-align: center;" |2.5| FPGA_BANK35_AD9N style="text-align: center;" |'''closed'''| AD9_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|-
|16 style="text-align: center;" |3.3| FPGA_BANK35_AD10P style="text-align: center;" |'''closed'''| AD10_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #35 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style="text-align: center; font-weight: bold;" | JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|2, 3, 8,<br>9, 14, 15 style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" |open| DGND style="text-align: center;" |'''closed'''| style="text- align: center;" |open| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
|-
|-
| style="text-align: center;" |1 .8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" |open| FPGA_BANK35_AD11P style="text-align: center;" |open| AD11_P } ====Examples of valid combinations for Zynq 7015-based SOMs===={|class="wikitable" style="text-align: center;"| Mount option+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" |Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2 ! style="text-align: center; font-weight: bold;" |JP25.3-4! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD10N |JP25.5-6! style="text-align: center; font-weight: bold;" | AD10_N JP25.7-8! style="text-align: center; font-weight: bold;" |JP25.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP25.11-12
|-
|3 style="text-align: center;" |1.2| FPGA_BANK35_AD11N style="text-align: center;" |open| AD11_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|6 style="text-align: center;" |1.5| FPGA_BANK35_AD12P style="text-align: center;" |open| AD12_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|7 style="text-align: center;" |1.8| FPGA_BANK35_AD13P style="text-align: center;" |open| AD13_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|8 style="text-align: center;" |2.5| FPGA_BANK35_AD12N style="text-align: center;" |'''closed'''| AD12_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|-
|9 style="text-align: center;" |3.3| FPGA_BANK35_AD13N style="text-align: center;" |'''closed'''| AD13_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #35 (HR)
|-
! style="text-align: center; font-weight: bold;" |12 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP27.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD14P JP27.3-4! style="text-align: center; font-weight: bold;" |JP27.5-6! style="text-align: center; font-weight: bold;" | AD14_P JP27.7-8! style="text-align: center; font-weight: bold;" |JP27.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP27.11-12
|-
|13 style="text-align: center;" |1.2| FPGA_BANK35_AD15P style="text-align: center;" |open| AD15_P style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|14 style="text-align: center;" |1.5| FPGA_BANK35_AD14N style="text-align: center;" |open| AD14_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|15 style="text-align: center;" |1.8| FPGA_BANK35_AD15N style="text-align: center;" |open| AD15_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|4, style="text-align: center;" | 2.5, 10,<br>11, 16 | style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" |'''closed'''| DGND style="text-align: center;" |open| style="text- align: center;" |open| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
{| class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style= Digilent Pmod™ Compatible headers "text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}
{| class="wikitable"
!Notes
|-
|2 || LDO_B13_1V6|| adds +1 .6V to VDDIO_BANK13 || -|-|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -|-|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -|-|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -|-|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -|-|12 ||PMOD_A0 LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -
|-
|2 1, 3, 5, 7, 9, 11 ||PMOD_A4 DGND|| - || -
|-
|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V ==SoM's signals mapping=====Bora Lite===As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''. {| class="wikitable"|+! colspan="2" |SoM's signal! colspan="6" |Routing options at carrier board level|-! rowspan="2" |Bank! rowspan="2" |Name! colspan="3" |Option #1(default)! colspan="3" |Option #2|-!Name!Pin!Note!Name!Pin!Note|-| rowspan="54" |34| rowspan="2" |IO_0_34| rowspan="2" |'''IO_0_VRN_34'''|J31.2|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27D.H2|FMC conn.|-| rowspan="2" |IO_25_34| rowspan="2" |'''IO_25_VRP_35'''|J31.4|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27B.D1|FMC conn.|-|IO_L10N_T1_34|IO_L10N_T1_34|J27D.H26|FMC conn.||||-|IO_L10P_T1_34|IO_L10P_T1_34|J27D.H25|FMC conn.||||-|IO_L11N_T1_SRCC_34|IO_L11N_T1_SRCC_34|J27D.G3|FMC conn.||||-|IO_L11P_T1_SRCC_34|IO_L11P_T1_SRCC_34|J27D.G2|FMC conn.||||-|IO_L12N_T1_MRCC_34|IO_L12N_T1_MRCC_34|J27D.H5|FMC conn.||||-|IO_L12P_T1_MRCC_34|IO_L12P_T1_MRCC_34|J27D.H4|FMC conn.||||-|IO_L13N_T2_MRCC_34|'''IO_L13N_T1_MRCC_34'''|J27D.G7|FMC conn.||||-|IO_L13P_T2_MRCC_34|'''IO_L13P_T1_MRCC_34'''|J27D.G6|FMC conn.||||-|IO_L14N_T2_SRCC_34|IO_L14N_T2_SRCC_34|J27B.D9|FMC conn.||||-|IO_L14P_T2_SRCC_34|IO_L14P_T2_SRCC_34|J27B.D8|FMC conn.||||-|IO_L15N_T2_DQS_34|IO_L15N_T2_DQS_34|J27B.D21|FMC conn.||||-|IO_L15P_T2_DQS_34|IO_L15P_T2_DQS_34|J27B.D20|FMC conn.||||-|IO_L16N_T2_34|IO_L16N_T2_34|J27B.C23|FMC conn.||||-|IO_L16P_T2_34|IO_L16P_T2_34|J27B.C22|FMC conn.||||-|IO_L17N_T2_34|IO_L17N_T2_34|J27D.G22|FMC conn.||||-|IO_L17P_T2_34|IO_L17P_T2_34|J27D.G21|FMC conn.||||-|IO_L18N_T2_34|IO_L18N_T2_34|J27D.H20|FMC conn.||||-|IO_L18P_T2_34|IO_L18P_T2_34|J27D.H19|FMC conn.||||-| rowspan="2" |IO_L19N_T3_VREF_34| rowspan="2" |IO_L19N_T3_VREF_34|J27D.G19|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP21|TP SMD|-|IO_L19P_T3_34|n/a|n/a|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L1N_T0_34|IO_L1N_T0_34|J27B.C19|FMC conn.||||-|IO_L1P_T0_34|IO_L1P_T0_34|J27B.C18|FMC conn.||||-|IO_L20N_T3_34|IO_L20N_T3_34|J27B.D18|FMC conn.||||-|IO_L20P_T3_34|IO_L20P_T3_34|J27B.D17|FMC conn.||||-|IO_L21N_T3_DQS_34|IO_L21N_T3_DQS_34|J27D.H17|FMC conn.||||-|IO_L21P_T3_DQS_34|IO_L21P_T3_DQS_34|J27D.H16|FMC conn.||||-|IO_L22N_T3_34|IO_L22N_T3_34|J27D.G16|FMC conn.||||-|IO_L22P_T3_34|IO_L22P_T3_34|J27D.G15|FMC conn.||||-|IO_L23N_T3_34|IO_L23N_T3_34|J27B.C11|FMC conn.||||-|IO_L23P_T3_34|IO_L23P_T3_34|J27B.C10|FMC conn.||||-|IO_L24N_T3_34|IO_L24N_T3_34|J27D.H23|FMC conn.||||-|IO_L24P_T3_34|IO_L24P_T3_34|J27D.H22|FMC conn.||||-|IO_L2N_T0_34|IO_L2N_T0_34|J27B.C15|FMC conn.||||-|IO_L2P_T0_34|IO_L2P_T0_34|J27B.C14|FMC conn.||||-|IO_L3N_T0_DQS_34|IO_L3N_T0_DQS_34|J27D.G13|FMC conn.||||-|IO_L3P_T0_DQS_PUDC_B_34(10K pull-up on SoM)|IO_L3P_T0_DQS_PUDC_B_34|J27D.G12|FMC conn.||||-|IO_L4N_T0_34|IO_L4N_T0_34|J27D.G10|FMC conn.||||-|IO_L4P_T0_34|IO_L4P_T0_34|J27D.G9|FMC conn.||||-|IO_L5N_T0_34|IO_L5N_T0_34|J27D.H11|FMC conn.||||-|IO_L5P_T0_34|IO_L5P_T0_34|J27D.H10|FMC conn.||||-| rowspan="2" |IO_L6N_T0_VREF_34| rowspan="2" |IO_L6N_T0_VREF_34|J27B.D15|FMC conn.||||-|TP22|TP SMD||||-|IO_L6P_T0_34|n/a|n/a|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L7N_T1_34|IO_L7N_T1_34|J27D.H8|FMC conn.||||-|IO_L7P_T1_34|IO_L7P_T1_34|J27D.H7|FMC conn.||||-|IO_L8N_T1_34|IO_L8N_T1_34|J27D.H14|FMC conn.||||-|IO_L8P_T1_34|IO_L8P_T1_34|J27D.H13|FMC conn.||||-|IO_L9N_T1_DQS_34|IO_L9N_T1_DQS_34|J27B.D12|FMC conn.||||-|IO_L9P_T1_DQS_34|IO_L9P_T1_DQS_34|J27B.D11|FMC conn.||||-|||||||||-| rowspan="54" |35| rowspan="2" |IO_0_35| rowspan="2" |'''IO_0_VRN_35'''|J27C.F1|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.1|Header|-| rowspan="2" |IO_25_35| rowspan="2" |'''IO_25_VRP_35'''|J27E.K13|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.3 |Header|-|IO_L10N_T1_AD11N_35|IO_L10N_T1_AD11N_35|J27D.G34|FMC conn.|FPGA_BANK35_AD11N|JP32.3|Header|-|IO_L10P_T1_AD11P_35|IO_L10P_T1_AD11P_35|J27D.G33|FMC conn.|FPGA_BANK35_AD11P|JP32.1|Header|-|IO_L11N_T1_SRCC_35|IO_L11N_T1_SRCC_35|J27E.J3|FMC conn.||||-|IO_L11P_T1_SRCC_35|IO_L11P_T1_SRCC_35|J27E.J2|FMC conn.||||-|IO_L12N_T1_MRCC_35|IO_L12N_T1_MRCC_35|J27E.K5|FMC conn.||||-|IO_L12P_T1_MRCC_35|IO_L12P_T1_MRCC_35|J27E.K4|FMC conn.||||-|IO_L13N_T2_MRCC_35|IO_L13N_T2_MRCC_35|J27C.F5|FMC conn.||||-|IO_L13P_T2_MRCC_35|IO_L13P_T2_MRCC_35|J27C.F4|FMC conn.||||-|IO_L14N_T2_AD4N_SRCC_35|IO_L14N_T2_AD4N_SRCC_35|J27C.E3|FMC conn.|FPGA_BANK35_AD4N|JP30.16|Header|-|IO_L14P_T2_AD4P_SRCC_35|IO_L14P_T2_AD4P_SRCC_35|J27C.E2|FMC conn.|FPGA_BANK35_AD4P|JP30.14|Header|-|IO_L15N_T2_DQS_AD12N_35|IO_L15N_T2_DQS_AD12N_35|J27D.H38|FMC conn.|FPGA_BANK35_AD12N|JP32.8|Header|-|IO_L15P_T2_DQS_AD12P_35|IO_L15P_T2_DQS_AD12P_35|J27D.H37|FMC conn.|FPGA_BANK35_AD12P|JP32.6|Header|-|IO_L16N_T2_35|IO_L16N_T2_35|J27D.G37|FMC conn.||||-|IO_L16P_T2_35|IO_L16P_T2_35|J27D.G36|FMC conn.||||-|IO_L17N_T2_AD5N_35|IO_L17N_T2_AD5N_35|J27E.K8|FMC conn.|FPGA_BANK35_AD5N|JP31.1|Header|-|IO_L17P_T2_AD5P_35|IO_L17P_T2_AD5P_35|J27E.K7|FMC conn.|FPGA_BANK35_AD5P|JP30.15|Header|-|IO_L18N_T2_AD13N_35|IO_L18N_T2_AD13N_35|J27E.J7|FMC conn.|FPGA_BANK35_AD13N|JP32.9|Header|-|IO_L18P_T2_AD13P_35|IO_L18P_T2_AD13P_35|J27E.J6|FMC conn.|FPGA_BANK35_AD13P|JP32.7|Header|-| rowspan="2" |IO_L19N_T3_VREF_35|rowspan="2" |PMOD_A1 IO_L19N_T3_VREF_35|J27C.F8| FMC conn.|rowspan="2" || rowspan="2" || rowspan="2" || -|TP24|TP SMD|-|IO_L19P_T3_35|IO_L19P_T3_35|J27C.F7|FMC conn.||||-|IO_L1N_T0_AD0N_35|IO_L1N_T0_AD0N_35|J27D.G25|FMC conn.|FPGA_BANK35_AD0P|JP30.4 |Header|-|IO_L1P_T0_AD0P_35|IO_L1P_T0_AD0P_35|J27D.G24|FMC conn.|FPGA_BANK35_AD0N|JP30.2|Header|-|IO_L20N_T3_AD6N_35|IO_L20N_T3_AD6N_35|J27C.E7|FMC conn.|FPGA_BANK35_AD6N|JP31.6|Header|-|IO_L20P_T3_AD6P_35|IO_L20P_T3_AD6P_35|J27C.E6|FMC conn.|FPGA_BANK35_AD6P|JP31.4|Header|-|IO_L21N_T3_DQS_AD14N_35|IO_L21N_T3_DQS_AD14N_35|J27E.K11|FMC conn.|FPGA_BANK35_AD14N|JP32.14|Header|-|IO_L21P_T3_DQS_AD14P_35|IO_L21P_T3_DQS_AD14P_35|J27E.K10|FMC conn.|FPGA_BANK35_AD14P|JP32.12|Header|-|IO_L22N_T3_AD7N_35|IO_L22N_T3_AD7N_35|J27E.J10|FMC conn.|PMOD_A5 FPGA_BANK35_AD7N|JP31.7| Header|-|IO_L22P_T3_AD7P_35|IO_L22P_T3_AD7P_35|J27E.J9|FMC conn.|FPGA_BANK35_AD7P|JP31.5|Header| -|IO_L23N_T3_35|IO_L23N_T3_35|J27C.F11|FMC conn.||||-|IO_L23P_T3_35|IO_L23P_T3_35|J27C.F10|FMC conn.||||-|IO_L24N_T3_AD15N_35|IO_L24N_T3_AD15N_35|J27C.E10|FMC conn.|FPGA_BANK35_AD15N|JP32.15|Header|-|IO_L24P_T3_AD15P_35|IO_L24P_T3_AD15P_35|J27C.E9|FMC conn.|FPGA_BANK35_AD15P|JP32.13|Header|-|IO_L2N_T0_AD8N_35|IO_L2N_T0_AD8N_35|J27B.D24|FMC conn.|FPGA_BANK35_AD8N|JP31.12|Header|-|IO_L2P_T0_AD8P_35|IO_L2P_T0_AD8P_35|J27B.D23|FMC conn.|FPGA_BANK35_AD8P|JP31.10|Header|-|IO_L3N_T0_DQS_AD1N_35|IO_L3N_T0_DQS_AD1N_35|J27D.H29|FMC conn.|FPGA_BANK35_AD1N|JP30.5 |Header|-|IO_L3P_T0_DQS_AD1P_35|IO_L3P_T0_DQS_AD1P_35|J27D.H28|FMC conn.|FPGA_BANK35_AD1P|JP30.3|Header|-|IO_L4N_T0_35|IO_L4N_T0_35|J27D.G28|FMC conn.||||-|IO_L4P_T0_35|IO_L4P_T0_35|J27D.G27|FMC conn.||||-|IO_L5N_T0_AD9N_35|IO_L5N_T0_AD9N_35|J27B.D27|FMC conn.|FPGA_BANK35_AD9N|JP31.13|Header|-|IO_L5P_T0_AD9P_35|IO_L5P_T0_AD9P_35|J27B.D26|FMC conn.|FPGA_BANK35_AD9P|JP31.11|Header|-| rowspan="2" |IO_L6N_T0_VREF_35| rowspan="2" |IO_L6N_T0_VREF_35|J27B.C27|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP23|TP SMD|-|IO_L6P_T0_35|IO_L6P_T0_35|J27B.C26|FMC conn.||||-|IO_L7N_T1_AD2N_35|IO_L7N_T1_AD2N_35|J27D.H32|FMC conn.|FPGA_BANK35_AD2N|JP30.10|Header|-|IO_L7P_T1_AD2P_35|IO_L7P_T1_AD2P_35|J27D.H31|FMC conn.|FPGA_BANK35_AD2P|JP30.8|Header|-|IO_L8N_T1_AD10N_35|IO_L8N_T1_AD10N_35|J27D.G31|FMC conn.|FPGA_BANK35_AD10N|JP32.2|Header|-|IO_L8P_T1_AD10P_35|IO_L8P_T1_AD10P_35|J27D.G30|FMC conn.|FPGA_BANK35_AD10P|JP31.16|Header|-|IO_L9N_T1_DQS_AD3N_35|IO_L9N_T1_DQS_AD3N_35|J27D.H35|FMC conn.|FPGA_BANK35_AD3N|JP30.11|Header|-|IO_L9P_T1_DQS_AD3P_35|IO_L9P_T1_DQS_AD3P_35|J27D.H34|FMC conn.|FPGA_BANK35_AD3P|JP30.9|Header|-|||||||||-| rowspan="26" |13'''(not available on Zynq 7007S and 7010)'''|IO_L11P_T1_SRCC_13|'''IO_L23P_T3_13'''|JP17.3|PMOD [A]||||-|IO_L11N_T1_SRCC_13|'''IO_L23N_T3_13'''|JP17.4|PMOD [A]||||-|IO_L12P_T1_MRCC_13|'''IO_L9P_T1_DQS_13'''|JP17.2|PMOD [A]|IO_L9P_T1_DQS_13|J30.1|ONE PIECE|-|IO_L12N_T1_MRCC_13|'''IO_L9N_T1_DQS_13'''|JP17.1|PMOD [A]|IO_L9N_T1_DQS_13|J30.3|ONE PIECE|-|IO_L13P_T2_MRCC_13|'''IO_L7P_T1_13'''|JP17.7|PMOD [A]|IO_L7P_T1_13|J30.24|ONE PIECE|-|IO_L13N_T2_MRCC_13|'''IO_L7N_T1_13'''|JP17.8|PMOD [A]|IO_L7N_T1_13|J30.26|ONE PIECE|-|PMOD_A2 IO_L14P_T2_SRCC_13|'''IO_L15P_T2_DQS_13'''| n/a|ETH1_RXCK|IO_L15P_T2_DQS_13|J30.25|ONE PIECE| -|IO_L14N_T2_SRCC_13|'''IO_L15N_T2_DQS_13'''|n/a|ETH1_RXCTL|IO_L15N_T2_DQS_13|J30.27|ONE PIECE|-|IO_L15P_T2_DQS_13|'''IO_L5P_T0_13'''|JP17.6 |PMOD [A]|IO_L5P_T0_13|J30.20|ONE PIECE|-|IO_L15N_T2_DQS_13|'''IO_L5N_T0_13'''|JP17.5|PMOD [A]|IO_L5N_T0_13|J30.18|ONE PIECE|-|IO_L16N_T2_13|IO_L16N_T2_13|n/a|ETH1_TXCTL|IO_L16N_T2_13|J30.31|ONE PIECE|-|IO_L16P_T2_13|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE|-|IO_L17N_T2_13|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE|-|IO_L17P_T2_13|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE|-|IO_L18N_T2_13|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE|-|IO_L18P_T2_13|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE|-|IO_L19N_T3_VREF_13|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE|-|IO_L19P_T3_13|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|PMOD_A6 J30.41|ONE PIECE| -|IO_L20N_T3_13|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE| -|IO_L20P_T3_13|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE|-|IO_L21N_T3_DQS_13|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE|-|IO_L21P_T3_DQS_13|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE|-|IO_L22N_T3_13|IO_L22N_T3_13|||IO_L22N_T3_13|J30.55|ONE PIECE|-|IO_L22P_T3_13|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE|-| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |IO_L6N_T0_VREF_13|JP23.3|PMOD [B]| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |J30.30| rowspan="2" |ONE PIECE|-|n/a|USB1_OC|} ==== BoraXEVB unavailable signals ====Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector. {| class="wikitable"|+BoraXEVB's signal that are not available when mated with Bora Lite SoM!Bank!Carrier's signal
|-
|7 13||PMOD_A3 || || -IO_25_13
|-
|8 13||PMOD_A7 || || -IO_L1P_T0_13
|-
|9, 10 13||DGND ||Ground || -IO_L1N_T0_13
|-
|11, 12 13||3.3V || || -IO_L2P_T0_13
|-
|}13 ==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" IO_L2N_T0_13
|-
|-
|1 13||PMOD_B0 || - || -IO_L3N_T0_DQS_13
|-
|2 13||PMOD_B4 || - || -IO_L4P_T0_13
|-
|3 13||PMOD_B1 || - || -IO_L4N_T0_13
|-
|4 500||PMOD_B5 || - || -NAND_CS0/SPI0_CS1
|-
|5 500||PMOD_B2 || - || -NAND_IO3
|-
|6 500||PMOD_B6 || - || -NAND_IO4
|-
|7 500||PMOD_B3 || - || -NAND_IO5
|-
|8 500||PMOD_B7 || - || -NAND_IO6
|-
|9, 10 500||DGND ||Ground || -NAND_IO7
|-
|11, 12 500||3.3V || - || -NAND_RD_B/VCFG1
|-
|500
|NAND_CLE/VCFG0
|}
==Schematics==
* ORCAD: http[[mirror:bora/hw/BoraXEVB/wwwBORAXEVB-1.dave6.eu/system/files/area1-BELK-riservata/boraxevbdsn.zip|BORAXEVB-1.06.31-BELK-dsn.zip]]* PDF : http[[mirror:bora/hw/wwwBoraXEVB/S-EVBBX0000C0R-1.dave6.eu/system/files/area-riservata/1_color.pdf|BoraXEVB-S-EVBBX0000C0R-1.26.01.pdf]]
==BOM==
* BoraXEVB: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB_S.EVBBX0000C0R.dave1.eu/system/files/area-riservata/boraxevb-BOM_S6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.26.0.CSV_CSV.zip]]
==Layout==
* http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-CS143714_assem_view.davepdf|boraxevb-CS143714_assem_view.eupdf]]==PCB design (Mentor PADS)==* [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb-CS143714_assembly_viewCS143714.zip|CS143714.pdfzip]]
==Mechanical==
* DXF: http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-2D-CS143714.davedxf.eu/system/files/areazip|boraxevb-2D-riservata/boraxevb_2D_CS143714CS143714.dxf.zip]]* IDF (3D): http[[mirror:bora/hw/BoraXEVB/wwwboraxevb-3D-CS143714.davezip|boraxevb-3D-CS143714.euzip]]* STEP (3D): [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb_3D_CS143714boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
