a000298_approval, dave_user
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| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in not supported on actual BSP version
=== WatchDog Settings - S1, S2 and S3 ===
|-
|12 ||LCD_LVDS_D2+ || - || -
|-
|14 ||LCD_LVDS_CLK- || - || -
|-
|15 ||LCD_LVDS_CLK+ || - || -
The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zip|link]] a spreadsheet providing the same information is available for download.
For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|this section]].
==== HPC Row A ====
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
Even if PL's banks are independent, default configuration of BoraXEVB is such that
*bank 34 and bank 35 have the same supply voltage
*this voltage is selected via JP28.
This configuration is in accordance with default routing of signals used for FMC connector.
====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====
{|class="wikitable" style="text-align: center;"
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
====Detailed jumpers Advanced information about voltage selection connectors========= BANK13 Bank 13 VDDIO selector - selection connector (JP25 ) =====
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
The DEFAULT default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
===== BANK35 Bank 35 VDDIO selector - selection connector (JP27 ) =====
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
Please note that:* By by default VDDIO_BANK35 is supplied by VADJ Regulator.
===== Bank 34 and VADJ VDDIO selector - selection connector (JP28 ) =====
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 9-10 -> supply VADJ with 1.2V
The DEFAULT default configuration is:
# Jumper on 5-6 -> supply VADJ with 1.8V
==Schematics==
* ORCAD: http[[mirror:bora/hw/BoraXEVB/wwwBORAXEVB-1.dave6.eu/system/files/area1-BELK-riservata/boraxevbdsn.zip|BORAXEVB-1.06.31-BELK-dsn.zip]]* PDF : http[[mirror:bora/hw/wwwBoraXEVB/S-EVBBX0000C0R-1.dave6.eu/system/files/area-riservata/1_color.pdf|BoraXEVB-S-EVBBX0000C0R-1.26.01.pdf]]
==BOM==
* BoraXEVB: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB_S.EVBBX0000C0R.dave1.eu/system/files/area-riservata/boraxevb-BOM_S6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.26.0.CSV_CSV.zip]]
==Layout==
* http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-CS143714_assem_view.davepdf|boraxevb-CS143714_assem_view.eupdf]]==PCB design (Mentor PADS)==* [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb-CS143714_assembly_viewCS143714.zip|CS143714.pdfzip]]
==Mechanical==
* DXF: http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-2D-CS143714.davedxf.eu/system/files/areazip|boraxevb-2D-riservata/boraxevb_2D_CS143714CS143714.dxf.zip]]* IDF (3D): http[[mirror:bora/hw/BoraXEVB/wwwboraxevb-3D-CS143714.davezip|boraxevb-3D-CS143714.euzip]]* STEP (3D): [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb_3D_CS143714boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
