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BoraXEVB

12,442 bytes added, 13:15, 14 June 2019
→‎Schematics
[[File:BoraXEVB-01.png|500px|frameless|border]]
==PL's I/O voltage selections==
{|class="wikitable" style="text-alignBlock Diagram== The following picture shows BORA Xpress EVB block diagram: center;"! rowspan="2" style="text[[File:Boraxevb-align: block_diagram.png|thumb|center; font-weight: bold;" | Zynq p/n600px|BoraXEVB simplified block diagram]]! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" styleConfigurable routing options="text-align: center; font-weight: bold;" | Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Bank FPGA banks #12, #34 and #35supports different routing options as shown in the following picture. |-| style="text-align: center; fontFor a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector -weight: bold;" J27| Type [1this section]].| style="text-align[[File: center; fontBoraxevb-weight: bold;" | I/O voltage setting| style="textFPGA-align: center; fontsignals-weight: bold;" routing.png| Type [1]thumb| style="text-align: center; font-weight: bold;" | I/O voltage setting600px| style="text-align: center; font-weight: bold;" | Type [1Configurable routing options diagram]]| style== Features =="text-align: center; font-weight: bold;" | I * 10/100/O voltage setting1000 Ethernet #0 (PS)|-* 10/100/1000 Ethernet #1 (Routed through EMIO)| style="text-align: center;" | 7015* 1x USB 2.0 OTG (MicroAB connector)* 1x Serial port (CLG485 packageRS232 DB9)| style="text-align: center;" | HR* 1x MicroSD* 1x FPGA Mezzanine Card (1FMC) Connector* XADC** Some signals of Bank 35 can be configured as XADC signals.For this reason they can be routed alternatively to 2 .54mm- 3pitch connectors, instead of FMC connector.3V)| style="text* State-of-the-alignart programmable MEMS clock generator (Silicon Labs Si504): center;" this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA* JTAG port* Socket for [[Wireless_Module_(DWM) | User definedDWM Wireless Module]]* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash| style="text* 2.54mm-pitch pin-align: center;" | HRstrip connectors for Bora Xpress PS and PL configurable peripherals (1MIO and EMIO interfaces, GPIOs, custom IPs, .2 - 3.3V)* Jumpers for voltage selection of the PL banks* +12V power connector == Known limitations == Board version CS040713A has the following limitations: {| styleclass="text-align: center;wikitable" | User defined-!Issue!Description| style="text-align: center;" | HRLCD_BKLT_PWM I/O voltage(1| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V.So in this case LCD_BKLT_PWM is an LVCMOS 2 - .5V signal. It is recommended to place a voltage level translator to 3.3V)if the signal voltages are not compatible with the LCD diplay backlight input.| style="text-align: center;" | FMC connector| For the [[Product_serial_number| User definedserial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
|-
| style="text-align: center;" | 7030
(SBG485 package)
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
==Block DiagramConnectors pinout ==
=== J1,J2 and J3 ===The following picture shows pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress EVB block diagram: module]].
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing optionsPower supply - JP2 ===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.
For a detailed description of FMC Power is provided through the JP2 connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
== Features == * 10/100/1000 Ethernet #0 (PS)* 10/100/1000 Ethernet #1 (Routed through EMIO)* 1x USB 2.0 OTG (MicroAB JP2 connector)* 1x Serial port (RS232 DB9)* 1x MicroSD* 1x FPGA Mezzanine Card (FMC) Connector* XADC** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to is a standard 2.54mm-pitch connectors, instead of FMC connector.* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his1mm/her own peripherals and IPs on FPGA* JTAG port* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash* 25.54mm-pitch 5mm DC power jack with positive center pin-strip connectors for Bora Xpress PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)* Jumpers for voltage selection of the PL banks* +12V power connector == Known limitations == Board version CS040713A has the following limitations:
{| class="wikitable"
|-
!Issue!Description|-| LCD_BKLT_PWM I/O voltage| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.|-| FMC connector| For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.|-|} == Connectors pinout == === J1,J2 and J3 ===The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress module]]. === Power supply - JP2 === Power is provided through the JP2 connector. JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin {| class="wikitable" |-!Pin#
!Pin name
!Function
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
 
<b>(*)</b> Boot mode from NAND in not supported on actual BSP version
=== WatchDog Settings - S1, S2 and S3 ===
|-
|}
=== JTAG ===
JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. === BANK13 VDDIO selector = JTAG XILINX - JP25 J13 ====JP25 J13 is a 1214-pin 6x2x2.54 7x2x2 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGND|| - || -|-|2 || LDO_B13_1V63.3V|| adds +1.6V to VDDIO_BANK13 - || -
|-
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-
!Pin#
!Pin name
!Notes
|-
|2 1 || LDO_B35_1V63.3V|| adds +1.6V to VDDIO_BANK35 - || -
|-
|4 2 || LDO_B35_800mV3.3V|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 3, 11, 17, 19 || LDO_B35_400mVN.C.|| adds +400mV to VDDIO_BANK35 - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_200mVDGND|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 5 || LDO_B35_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK35 - || -
|-
|12 7 || LDO_B35_50mVJTAG_TMS|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 || DGNDJTAG_TCK|| - || -
|-
|13 || JTAG_TDO|| - || -|-|15 || JTAG_TRSTn|| - || -|-|}
The jumper configurations are:# No jumpers installed === UART1 -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator === VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 3|UART_EXT_TX| VADJ_FB (51K1)Transmit line|| selects 1.8V VADJ || -Connected to protection diode array
|-
|8 5|DGND| VADJ_FB (68K)Ground|| selects 1.5V VADJ || -
|-
|10 7, 8|| VADJ_FB (100K)|| selects 1N.C.2V VADJ || -|-N.C.|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -Connected to protection diode array
|-
|}
The jumper configurations are:# Jumper on 1=== USB OTG -2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2VJ19 ===
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
=== JTAG ===
 
JTAG port is available as two different mechanical connectors:
* 2.00mm-pitch 7x2 header (Xilinx standard)
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
 
==== JTAG XILINX - J13 ====
 
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDUSB_OTG_VBUS || - || -
|-
|2 || 3.3VUSBM1 || - || -
|-
|4 3 || JTAG_TMSUSBP1 || - || -
|-
|6 4 || JTAG_TCKOTG_ID || - || -
|-
|8 5 || JTAG_TDOUSB_OTG_DGND || - || -
|-
|10 6, 7, 8, 9 || JTAG_TDI|| - || -|-|12 || N.C.|| - || -|-|14 || JTAG_TRSTnUSB_OTG_SHIELD || - || -
|-
|}
==== JTAG ARM MicroSD - J18 =J21 ===J18 J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a 20bidirectional 1.8V/3.3V voltage-pin 10x2x2level translator mounted on the BORA Xpress EVB.54 pitch vertical headerLevel shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1 || 3.3VPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|3, 11, 17, 19 || N.C.PS_SD0_CMD||| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND3.3V||| - || -
|-
|5 || JTAG_TDIPS_SD0_CLK||| - || -
|-
|7 6, 9, 10, 11, 12 || JTAG_TMSDGND||| - || -
|-
|9 7 || JTAG_TCKPS_SD0_DAT0||| - || -
|-
|13 8 || JTAG_TDOPS_SD0_DAT1||| - || -
|-
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
{| class="wikitable"
!Notes
|-
|1, 62 ||5V || - || -|-|3, 4||3.3V || - || -|-|5, 6, <br> 9, 10,<br>19 ||DGND || - || -|N.C.-|N.C.7 ||DWM_SD_CMD || - ||-
|-
|28 |UART_EXT_RX|Receive lineDWM_SD_CLK |Connected to protection diode array| - || -
|-
|311 |UART_EXT_TX|Transmit lineDWM_SD_DAT0 |Connected to protection diode array| - || -
|-
|512, 14,<br>16, 18,<br>20, 22 |DGND|GroundN.C. || - || -
|-
|7, 813 |N.C.|N.C.DWM_SD_DAT1 |Connected to protection diode array| - || -
|-
|}15 ||DWM_SD_DAT2 || - || -|-|17 ||DWM_SD_DAT3 || - || -|-|21 ||DWM_UART_RX || - || -|-|23 ||DWM_UART_CTS || - || -|-|24 ||DWM_BT_F5 || - || -|-|25 ||DWM_UART_TX || - || -|-|26 ||DWM_BT_F2 || - || -|-|27 ||DWM_UART_RTS || - || -|-|28 ||DWM_WIFI_IRQ || - || -|-|29 ||DWM_BT_EN || - || -|-|30 ||DWM_WIFI_EN || - || -=== USB OTG |- J19 ===|}
J19 === CAN - J24 ===J24 is a standard USB MICRO AB connector10-pin 5x2x2. It is 54mm pitch vertical header directly connected to the BORA Xpress USB SoM's transceiver for the CAN interface. This 2.0 OTG peripheral5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 , 6,<br>7, 8,<br>9, 10 ||USB_OTG_VBUS N.C. || - || -
|-
|2 , 5 ||USBM1 CAN_SHIELD || - || -
|-
|3 ||USBP1 CAN_L || - || -
|-
|4 ||OTG_ID || - || -|-|5 ||USB_OTG_DGND || - || -|-|6, 7, 8, 9 ||USB_OTG_SHIELD CAN_H || - || -
|-
|}
=== MicroSD Touch screen - J21 J25=== J21 J25 is a microSD memory card ZIF 4-pin 1.0mm pitch connector. It is connected that connects the touchscreen drive lines to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted touch screen controller on the BORA BoORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 ||PS_SD0_DAT2|TSC_YP || - || -
|-
|2 ||PS_SD0_DAT3|TSC_XP || - || -
|-
|3 ||PS_SD0_CMD|TSC_YM || - || -
|-
|4 ||3.3V|TSC_XM || - || -
|-
|5 ||PS_SD0_CLK||| } === LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux- drivers/platforms/zynq. The following table reports the pinout of the connector: {|| -class="wikitable"
|-
|6, 9, 10, 11, 12 ||DGND||| - || -|-|7 ||PS_SD0_DAT0||| - || -|-|8 ||PS_SD0_DAT1||| - || -|-|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -|-|} === DWM (DAVE Wifi/BT module) socket - J23 ===J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin#
!Pin name
!Function
!Notes
|-
|1, 2 ||5V 3.3V_LCD || - || -
|-
|3, 4 , 7, 10,<br>13, 16, 19 ||3.3V DGND || - Ground || -
|-
|5, 6,<br> 9, 10,<br>19 ||DGND LCD_LVDS_D0- || - || -
|-
|7 6 ||DWM_SD_CMD LCD_LVDS_D0+ || - || -
|-
|8 ||DWM_SD_CLK LCD_LVDS_D1- || - || -
|-
|11 9 ||DWM_SD_DAT0 LCD_LVDS_D1+ || - || -
|-
|12, 14,<br>16, 18,<br>20, 22 11 ||N.C. LCD_LVDS_D2- || - || -
|-
|13 12 ||DWM_SD_DAT1 LCD_LVDS_D2+ || - || -
|-
|15 14 ||DWM_SD_DAT2 LCD_LVDS_CLK- || - || -
|-
|17 15 ||DWM_SD_DAT3 LCD_LVDS_CLK+ || - || -
|-
|21 17 ||DWM_UART_RX LCD_P17 || - || -
|-
|23 18 ||DWM_UART_CTS LCD_P18 || - || -
|-
|24 20 ||DWM_BT_F5 LCD_P20 || - || -
|-
|25 21,22 ||DWM_UART_TX DGND || - Ground || -|-|26 ||DWM_BT_F2 || - || -|-|27 ||DWM_UART_RTS || - || -|-|28 ||DWM_WIFI_IRQ || - || -|-|29 ||DWM_BT_EN || - || -|-|30 ||DWM_WIFI_EN || - || -Shield
|-
|}
=== CAN FPGA Mezzanine Card (FMC) Connector - J24 J27 ===J24 J27 is a 10400 pins ANSI/VITA 57.1-pin 5x2x2.54mm pitch vertical header directly connected 2008 FPGA Mezzanine Card Connector that allows to connect to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10standard I/DB9 flat cablesO mezzanine cards. The following table reports the pinout of the connector:
{| class="wikitable" Please note that BoraXpress EVB FMC Connector is:|-* fully compliant to FMC LPC!Pin# * partially compliant to FMC HPC because HPC side is not fully populated.!Pin name!Function!Notes|-|1, 6,<br>7, 8,<br>9, 10 ||NThe following tables detail how BORA Xpress signals have been routed to FMC connector.C. || At this [[:File:BoraXEVB- || FMC-routing.zip|-|2, 5 ||CAN_SHIELD || - || -link]] a spreadsheet providing the same information is available for download.|-|3 ||CAN_L || For more information about I/O voltage of single- ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|| -|-|4 ||CAN_H || - || -|-|}this section]].
=== Touch screen - J25= HPC Row A ====J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 A1||TSC_YP DGND|| - GND|| -
|-
|2 A2||TSC_XP MGTxRXP1|| - DP1_M2C_P|| -
|-
|3 A3||TSC_YM MGTxRXN1|| - DP1_M2C_N|| -
|-
|4 A4||TSC_XM DGND|| - GND|| -
|-
|} === LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector: {A5||DGND||GND|| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A6||MGTxRXP2||DP2_M2C_P||
|-
|1, 2 A7||3.3V_LCD MGTxRXN2|| - DP2_M2C_N|| -
|-
|3, 4, 7, 10,<br>13, 16, 19 A8||DGND || Ground GND|| -
|-
|5 A9||LCD_LVDS_D0- DGND|| - GND|| -
|-
|6 A10||LCD_LVDS_D0+ MGTxRXP3|| - DP3_M2C_P|| -
|-
|8 A11||LCD_LVDS_D1- MGTxRXN3|| - DP3_M2C_N|| -
|-
|9 A12||LCD_LVDS_D1+ DGND|| - GND|| -
|-
|11 A13||LCD_LVDS_D2- DGND|| - GND|| -
|-
|12 A14||LCD_LVDS_D2+ <span style="color:#ff0000">not connected</span>|| - DP4_M2C_P|| -
|-
|15 A15||LCD_LVDS_CLK+ <span style="color:#ff0000">not connected</span>|| - DP4_M2C_N|| -
|-
|17 A16||LCD_P17 DGND|| - GND|| -
|-
|18 A17||LCD_P18 DGND|| - GND|| -
|-
|20 A18||LCD_P20 <span style="color:#ff0000">not connected</span>|| - DP5_M2C_P|| -
|-
|21,22 A19||DGND <span style="color:#ff0000">not connected</span>|| Ground DP5_M2C_N|| Shield
|-
|} === FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipA20||DGND||GND|link]] a spreadsheet providing the same information is available for download. ==== HPC Row A ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A21||DGND||GND||
|-
| A1A22||DGNDMGTxTXP1||GNDDP1_C2M_P||
|-
| A2A23||MGTxRXP1MGTxTXN1||DP1_M2C_PDP1_C2M_N||
|-
| A3A24||MGTxRXN1DGND||DP1_M2C_NGND||
|-
| A4A25||DGND||GND||
|-
| A5A26||DGNDMGTxTXP2||GNDDP2_C2M_P||
|-
| A6A27||MGTxRXP2MGTxTXN2||DP2_M2C_PDP2_C2M_N||
|-
| A7A28||MGTxRXN2DGND||DP2_M2C_NGND||
|-
| A8A29||DGND||GND||
|-
| A9A30||DGNDMGTxTXP3||GNDDP3_C2M_P||
|-
| A10A31||MGTxRXP3MGTxTXN3||DP3_M2C_PDP3_C2M_N||
|-
| A11A32||MGTxRXN3DGND||DP3_M2C_NGND||
|-
| A12A33||DGND||GND||
|-
| A13A34||DGND<span style="color:#ff0000">not connected</span>||GNDDP4_C2M_P||
|-
| A14A35||<span style="color:#ff0000">not connected</span>||DP4_M2C_PDP4_C2M_N||
|-
| A15A36||<span style="color:#ff0000">not connected</span>DGND||DP4_M2C_NGND||
|-
| A16A37||DGND||GND||
|-
| A17A38||DGND<span style="color:#ff0000">not connected</span>||GNDDP5_C2M_P||
|-
| A18A39||<span style="color:#ff0000">not connected</span>||DP5_M2C_PDP5_C2M_N||
|-
| A19A40||<span style="color:#ff0000">not connected</span>DGND||GND||DP5_M2C_N|} ==== HPC Row B ==== {|class="wikitable"
|-
| A20||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| A21B1||DGNDRSVD||GNDRES1||
|-
| A22B2||MGTxTXP1DGND||DP1_C2M_PGND||
|-
| A23B3||MGTxTXN1DGND||DP1_C2M_NGND||
|-
| A24B4||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_M2C_P||
|-
| A25B5||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_M2C_N||
|-
| A26B6||MGTxTXP2DGND||DP2_C2M_PGND||
|-
| A27B7||MGTxTXN2DGND||DP2_C2M_NGND||
|-
| A28B8||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_M2C_P||
|-
| A29B9||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_M2C_N||
|-
| A30B10||MGTxTXP3DGND||DP3_C2M_PGND||
|-
| A31B11||MGTxTXN3DGND||DP3_C2M_NGND||
|-
| A32B12||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_M2C_P||
|-
| A33B13||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_M2C_N||
|-
| A34B14||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_PGND||
|-
| A35B15||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_NGND||
|-
| A36B16||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_M2C_P||
|-
| A37B17||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_M2C_N||
|-
| A38B18||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_PGND||
|-
| A39B19||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_NGND||
|-
| A40B20||DGNDMGTREFCLK1P||GNDGBTCLK1_M2C_P|||} ==== HPC Row B ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| B21||MGTREFCLK1N||GBTCLK1_M2C_N||
|-
| B1B22||RSVDDGND||RES1GND||
|-
| B2B23||DGND||GND||
|-
| B3B24||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_C2M_P||
|-
| B4B25||<span style="color:#ff0000">not connected</span>||DP9_M2C_PDP9_C2M_N||
|-
| B5B26||<span style="color:#ff0000">not connected</span>DGND||DP9_M2C_NGND||
|-
| B6B27||DGND||GND||
|-
| B7B28||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_C2M_P||
|-
| B8B29||<span style="color:#ff0000">not connected</span>||DP8_M2C_PDP8_C2M_N||
|-
| B9B30||<span style="color:#ff0000">not connected</span>DGND||DP8_M2C_NGND||
|-
| B10B31||DGND||GND||
|-
| B11B32||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_C2M_P||
|-
| B12B33||<span style="color:#ff0000">not connected</span>||DP7_M2C_PDP7_C2M_N||
|-
| B13B34||<span style="color:#ff0000">not connected</span>DGND||DP7_M2C_NGND||
|-
| B14B35||DGND||GND||
|-
| B15B36||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_C2M_P||
|-
| B16B37||<span style="color:#ff0000">not connected</span>||DP6_M2C_PDP6_C2M_N||
|-
| B17B38||<span style="color:#ff0000">not connected</span>DGND||DP6_M2C_NGND||
|-
| B18B39||DGND||GND||
|-
| B19B40||DGNDRSVD||GNDRES0|||} ==== LPC Row C ==== {| class="wikitable"
|-
| B20||MGTREFCLK1P||GBTCLK1_M2C_P||!Pin# !Pin name!Function!Notes
|-
| B21C1||MGTREFCLK1NDGND||GBTCLK1_M2C_NGND||
|-
| B22C2||DGNDMGTxTXP0||GNDDP0_C2M_P||
|-
| B23C3||DGNDMGTxTXN0||GNDDP0_C2M_N||
|-
| B24C4||<span style="color:#ff0000">not connected</span>DGND||DP9_C2M_PGND||
|-
| B25C5||<span style="color:#ff0000">not connected</span>DGND||DP9_C2M_NGND||
|-
| B26C6||DGNDMGTxRXP0||GNDDP0_M2C_P||
|-
| B27C7||DGNDMGTxRXN0||GNDDP0_M2C_N||
|-
| B28C8||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_PGND||
|-
| B29C9||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_NGND||
|-
| B30C10||DGNDIO_L23P_T3_34||GNDLA06_P||
|-
| B31C11||DGNDIO_L23N_T3_34||GNDLA06_N||
|-
| B32C12||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_PGND||
|-
| B33C13||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_NGND||
|-
| B34C14||DGNDIO_L2P_T0_34||GNDLA10_P||
|-
| B35C15||DGNDIO_L2N_T0_34||GNDLA10_N||
|-
| B36C16||<span style="color:#ff0000">not connected</span>DGND||DP6_C2M_PGND||
|-
| B37C17||<span style="color:#ff0000">not connected</span>DGND||DP6_C2M_NGND||
|-
| B38C18||DGNDIO_L1P_T0_34||GNDLA14_P||
|-
| B39C19||DGNDIO_L1N_T0_34||GNDLA14_N||
|-
| B40C20||RSVDDGND||RES0GND|||} ==== LPC Row C ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| C21||DGND||GND||
|-
| C1C22||DGNDIO_L16P_T2_34||GNDLA18_P_CC||
|-
| C2C23||MGTxTXP0IO_L16N_T2_34||DP0_C2M_PLA18_N_CC||
|-
| C3C24||MGTxTXN0DGND||DP0_C2M_NGND||
|-
| C4C25||DGND||GND||
|-
| C5C26||DGNDIO_L6P_T0_35||GNDLA27_P||
|-
| C6C27||MGTxRXP0IO_L6N_T0_VREF_35||DP0_M2C_PLA27_N||
|-
| C7C28||MGTxRXN0DGND||DP0_M2C_NGND||
|-
| C8C29||DGND||GND||
|-
| C9C30||DGNDI2C0_SCL||GNDSCL||
|-
| C10C31||IO_L23P_T3_34I2C0_SDA||LA06_PSDA||
|-
| C11C32||IO_L23N_T3_34DGND||LA06_NGND||
|-
| C12C33||DGND||GND||
|-
| C13C34||DGNDGA0||GNDGA0||
|-
| C14C35||IO_L2P_T0_34FMC_12P0V||LA10_P12P0V||
|-
| C15C36||IO_L2N_T0_34DGND||LA10_NGND||
|-
| C16C37||DGNDFMC_12P0V||GND12P0V||
|-
| C17C38||DGND||GND||
|-
| C18C39||IO_L1P_T0_34FMC_3P3V||LA14_P3P3V||
|-
| C19C40||IO_L1N_T0_34DGND||LA14_NGND|||} ==== LPC Row D ==== {| class="wikitable"
|-
| C20||DGND||GND||!Pin# |-!Pin name| C21||DGND||GND||!Function!Notes
|-
| C22D1||IO_L16P_T2_34IO_25_VRP_34||LA18_P_CCPG_C2M||
|-
| C23D2||IO_L16N_T2_34DGND||LA18_N_CCGND||
|-
| C24D3||DGND||GND||
|-
| C25D4||DGNDMGTREFCLK0P||GNDGBTCLK0_M2C_P||
|-
| C26D5||IO_L6P_T0_35MGTREFCLK0N||LA27_PGBTCLK0_M2C_N||
|-
| C27D6||IO_L6N_T0_VREF_35DGND||LA27_NGND||
|-
| C28D7||DGND||GND||
|-
| C29D8||DGNDIO_L14P_T2_SRCC_34||GNDLA01_P_CC||
|-
| C30D9||I2C0_SCLIO_L14N_T2_SRCC_34||SCLLA01_N_CC||
|-
| C31D10||I2C0_SDADGND||SDAGND||
|-
| C32D11||DGNDIO_L9P_T1_DQS_34||GNDLA05_P||
|-
| C33D12||DGNDIO_L9N_T1_DQS_34||GNDLA05_N||
|-
| C34D13||GA0DGND||GA0GND||
|-
| C35D14||FMC_12P0VIO_L6P_T0_34||12P0VLA09_P||
|-
| C36D15||DGNDIO_L6N_T0_VREF_34||GNDLA09_N||
|-
| C37D16||FMC_12P0VDGND||12P0VGND||
|-
| C38D17||DGNDIO_L20P_T3_34||GNDLA13_P||
|-
| C39D18||FMC_3P3VIO_L20N_T3_34||3P3VLA13_N||
|-
| C40D19||DGND||GND|||} ==== LPC Row D ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| D20||IO_L15P_T2_DQS_34||LA17_P_CC||
|-
| D1D21||IO_25_VRP_34IO_L15N_T2_DQS_34||PG_C2MLA17_N_CC||
|-
| D2D22||DGND||GND||
|-
| D3D23||DGNDIO_L2P_T0_AD8P_35||GNDLA23_P||
|-
| D4D24||MGTREFCLK0PIO_L2N_T0_AD8N_35||GBTCLK0_M2C_PLA23_N||
|-
| D5D25||MGTREFCLK0NDGND||GBTCLK0_M2C_NGND||
|-
| D6D26||DGNDIO_L5P_T0_AD9P_35||GNDLA26_P||
|-
| D7D27||DGNDIO_L5N_T0_AD9N_35||GNDLA26_N||
|-
| D8D28||IO_L14P_T2_SRCC_34DGND||LA01_P_CCGND||
|-
| D9D29||IO_L14N_T2_SRCC_34JTAG_TCK||LA01_N_CCTCK||
|-
| D10D30||DGNDJTAG_TDI||GNDTDI||
|-
| D11D31||IO_L9P_T1_DQS_34FMC_TDO_ZYNQ_TDI||LA05_PTDO||
|-
| D12D32||IO_L9N_T1_DQS_34FMC_3P3VAUX||LA05_N3P3VAUX||
|-
| D13D33||DGNDJTAG_TMS||GNDTMS||
|-
| D14D34||IO_L6P_T0_34JTAG_TRSTn||LA09_PTRST_L||
|-
| D15D35||IO_L6N_T0_VREF_34GA0||LA09_NGA1||
|-
| D16D36||DGNDFMC_3P3V||GND3P3V||
|-
| D17D37||IO_L20P_T3_34DGND||LA13_PGND||
|-
| D18D38||IO_L20N_T3_34FMC_3P3V||LA13_N3P3V||
|-
| D19D39||DGND||GND||
|-
| D20D40||IO_L15P_T2_DQS_34FMC_3P3V||LA17_P_CC3P3V|||} ==== HPC Row E ==== {| class="wikitable"
|-
| D21||IO_L15N_T2_DQS_34||LA17_N_CC||!Pin# !Pin name!Function!Notes
|-
| D22E1||DGND||GND||
|-
| D23E2||IO_L2P_T0_AD8P_35IO_L14P_T2_AD4P_SRCC_35||LA23_PHA01_P_CC||
|-
| D24E3||IO_L2N_T0_AD8N_35IO_L14N_T2_AD4N_SRCC_35||LA23_NHA01_N_CC||
|-
| D25E4||DGND||GND||
|-
| D26E5||IO_L5P_T0_AD9P_35DGND||LA26_PGND||
|-
| D27E6||IO_L5N_T0_AD9N_35IO_L20P_T3_AD6P_35||LA26_NHA05_P||
|-
| D28E7||DGNDIO_L20N_T3_AD6N_35||GNDHA05_N||
|-
| D29E8||JTAG_TCKDGND||TCKGND||
|-
| D30E9||JTAG_TDIIO_L24P_T3_AD15P_35||TDIHA09_P||
|-
| D31E10||FMC_TDO_ZYNQ_TDIIO_L24N_T3_AD15N_35||TDOHA09_N||
|-
| D32E11||FMC_3P3VAUXDGND||3P3VAUXGND||
|-
| D33E12||JTAG_TMS<span style="color:#ff0000">not connected</span>||TMSHA13_P||
|-
| D34E13||JTAG_TRSTn<span style="color:#ff0000">not connected</span>||TRST_LHA13_N||
|-
| D35E14||GA0DGND||GA1GND||
|-
| D36E15||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHA16_P||
|-
| D37E16||DGND<span style="color:#ff0000">not connected</span>||GNDHA16_N||
|-
| D38E17||FMC_3P3VDGND||3P3VGND||
|-
| D39E18||DGND<span style="color:#ff0000">not connected</span>||GNDHA20_P||
|-
| D40E19||FMC_3P3V||3P3V<span style="color:#ff0000">not connected</span>||HA20_N|} ==== HPC Row E ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| E20||DGND||GND||
|-
| E1E21||DGND<span style="color:#ff0000">not connected</span>||GNDHB03_P||
|-
| E2E22||IO_L14P_T2_AD4P_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_P_CCHB03_N||
|-
| E3E23||IO_L14N_T2_AD4N_SRCC_35DGND||HA01_N_CCGND||
|-
| E4E24||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_P||
|-
| E5E25||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_N||
|-
| E6E26||IO_L20P_T3_AD6P_35DGND||HA05_PGND||
|-
| E7E27||IO_L20N_T3_AD6N_35<span style="color:#ff0000">not connected</span>||HA05_NHB09_P||
|-
| E8E28||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_N||
|-
| E9E29||IO_L24P_T3_AD15P_35DGND||HA09_PGND||
|-
| E10E30||IO_L24N_T3_AD15N_35<span style="color:#ff0000">not connected</span>||HA09_NHB13_P||
|-
| E11E31||DGND<span style="color:#ff0000">not connected</span>||GNDHB13_N||
|-
| E12E32||<span style="color:#ff0000">not connected</span>DGND||HA13_PGND||
|-
| E13E33||<span style="color:#ff0000">not connected</span>||HA13_NHB19_P||
|-
| E14E34||DGND<span style="color:#ff0000">not connected</span>||GNDHB19_N||
|-
| E15E35||<span style="color:#ff0000">not connected</span>DGND||HA16_PGND||
|-
| E16E36||<span style="color:#ff0000">not connected</span>||HA16_NHB21_P||
|-
| E17E37||DGND<span style="color:#ff0000">not connected</span>||GNDHB21_N||
|-
| E18E38||<span style="color:#ff0000">not connected</span>DGND||HA20_PGND||
|-
| E19E39||<span style="color:#ff0000">not connected</span>FMC_VADJ||HA20_NVADJ||
|-
| E20E40||DGND||GND|||} ==== HPC Row F ==== {| class="wikitable"
|-
| E21||<span style="color:!Pin#ff0000">not connected</span>||HB03_P||!Pin name!Function!Notes
|-
| E22F1||<span style="color:#ff0000">not connected</span>IO_0_VRN_35||HB03_NPG_M2C||
|-
| E23F2||DGND||GND||
|-
| E24F3||<span style="color:#ff0000">not connected</span>DGND||HB05_PGND||
|-
| E25F4||<span style="color:#ff0000">not connected</span>IO_L13P_T2_MRCC_35||HB05_NHA00_P_CC||
|-
| E26F5||DGNDIO_L13N_T2_MRCC_35||GNDHA00_N_CC||
|-
| E27F6||<span style="color:#ff0000">not connected</span>DGND||HB09_PGND|||-| F7||IO_L19P_T3_35||HA04_P||
|-
| E28F8||<span style="color:#ff0000">not connected</span>IO_L19N_T3_VREF_35||HB09_NHA04_N||
|-
| E29F9||DGND||GND||
|-
| E30F10||<span style="color:#ff0000">not connected</span>IO_L23P_T3_35||HB13_PHA08_P||
|-
| E31F11||<span style="color:#ff0000">not connected</span>IO_L23N_T3_35||HB13_NHA08_N||
|-
| E32F12||DGND||GND||
|-
| E33F13||<span style="color:#ff0000">not connected</span>||HB19_PHA12_P||
|-
| E34F14||<span style="color:#ff0000">not connected</span>||HB19_NHA12_N||
|-
| E35F15||DGND||GND||
|-
| E36F16||<span style="color:#ff0000">not connected</span>||HB21_PHA15_P||
|-
| E37F17||<span style="color:#ff0000">not connected</span>||HB21_NHA15_N||
|-
| E38F18||DGND||GND||
|-
| E39F19||FMC_VADJ<span style="color:#ff0000">not connected</span>||VADJHA19_P||
|-
| E40F20||DGND||GND<span style="color:#ff0000">not connected</span>||HA19_N|} ==== HPC Row F ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| F21||DGND||GND||
|-
| F1F22||IO_0_VRN_35<span style="color:#ff0000">not connected</span>||PG_M2CHB02_P||
|-
| F2F23||DGND<span style="color:#ff0000">not connected</span>||GNDHB02_N||
|-
| F3F24||DGND||GND||
|-
| F4F25||IO_L13P_T2_MRCC_35<span style="color:#ff0000">not connected</span>||HA00_P_CCHB04_P||
|-
| F5F26||IO_L13N_T2_MRCC_35<span style="color:#ff0000">not connected</span>||HA00_N_CCHB04_N||
|-
| F6F27||DGND||GND||
|-
| F7F28||IO_L19P_T3_35<span style="color:#ff0000">not connected</span>||HA04_PHB08_P||
|-
| F8F29||IO_L19N_T3_VREF_35<span style="color:#ff0000">not connected</span>||HA04_NHB08_N||
|-
| F9F30||DGND||GND||
|-
| F10F31||IO_L23P_T3_35<span style="color:#ff0000">not connected</span>||HA08_PHB12_P||
|-
| F11F32||IO_L23N_T3_35<span style="color:#ff0000">not connected</span>||HA08_NHB12_N||
|-
| F12F33||DGND||GND||
|-
| F13F34||<span style="color:#ff0000">not connected</span>||HA12_PHB16_P||
|-
| F14F35||<span style="color:#ff0000">not connected</span>||HA12_NHB16_N||
|-
| F15F36||DGND||GND||
|-
| F16F37||<span style="color:#ff0000">not connected</span>||HA15_PHB20_P||
|-
| F17F38||<span style="color:#ff0000">not connected</span>||HA15_NHB20_N||
|-
| F18F39||DGND||GND||
|-
| F19F40||<span style="color:#ff0000">not connected</span>FMC_VADJ||VADJ||HA19_P|} ==== LPC Row G ==== {|class="wikitable"
|-
| F20||<span style="color:!Pin#ff0000">not connected</span>||HA19_N||!Pin name!Function!Notes
|-
| F21G1||DGND||GND||
|-
| F22G2||<span style="color:#ff0000">not connected</span>IO_L11P_T1_SRCC_34||HB02_PCLK0_C2M_P||
|-
| F23G3||<span style="color:#ff0000">not connected</span>IO_L11N_T1_SRCC_34||HB02_NCLK0_C2M_N||
|-
| F24G4||DGND||GND||
|-
| F25G5||<span style="color:#ff0000">not connected</span>DGND||HB04_PGND||
|-
| F26G6||<span style="color:#ff0000">not connected</span>IO_L13P_T1_MRCC_34||HB04_NLA00_P_CC||
|-
| F27G7||DGNDIO_L13N_T1_MRCC_34||GNDLA00_N_CC||
|-
| F28G8||<span style="color:#ff0000">not connected</span>DGND||HB08_PGND||
|-
| F29G9||<span style="color:#ff0000">not connected</span>IO_L4P_T0_34||HB08_NLA03_P||
|-
| F30G10||DGNDIO_L4N_T0_34||GNDLA03_N||
|-
| F31G11||<span style="color:#ff0000">not connected</span>DGND||HB12_PGND||
|-
| F32G12||<span style="color:#ff0000">not connected</span>IO_L3P_T0_DQS_PUDC_B_34||HB12_NLA08_P||
|-
| F33G13||DGNDIO_L3N_T0_DQS_34||GNDLA08_N||
|-
| F34G14||<span style="color:#ff0000">not connected</span>DGND||HB16_PGND||
|-
| F35G15||<span style="color:#ff0000">not connected</span>IO_L22P_T3_34||HB16_NLA12_P||
|-
| F36G16||DGNDIO_L22N_T3_34||GNDLA12_N||
|-
| F37G17||<span style="color:#ff0000">not connected</span>DGND||HB20_PGND||
|-
| F38G18||<span style="color:#ff0000">not connected</span>IO_L19P_T3_34||HB20_NLA16_P||
|-
| F39G19||DGNDIO_L19N_T3_VREF_34||GNDLA16_N||
|-
| F40G20||FMC_VADJDGND||VADJGND|||} ==== LPC Row G ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| G21||IO_L17P_T2_34||LA20_P||
|-
| G1G22||DGNDIO_L17N_T2_34||GNDLA20_N||
|-
| G2G23||IO_L11P_T1_SRCC_34DGND||CLK0_C2M_PGND||
|-
| G3G24||IO_L11N_T1_SRCC_34IO_L1P_T0_AD0P_35||CLK0_C2M_NLA22_P||
|-
| G4G25||DGNDIO_L1N_T0_AD0N_35||GNDLA22_N||
|-
| G5G26||DGND||GND||
|-
| G6G27||IO_L13P_T1_MRCC_34IO_L4P_T0_35||LA00_P_CCLA25_P||
|-
| G7G28||IO_L13N_T1_MRCC_34IO_L4N_T0_35||LA00_N_CCLA25_N||
|-
| G8G29||DGND||GND||
|-
| G9G30||IO_L4P_T0_34IO_L8P_T1_AD10P_35||LA03_PLA29_P||
|-
| G10G31||IO_L4N_T0_34IO_L8N_T1_AD10N_35||LA03_NLA29_N||
|-
| G11G32||DGND||GND||
|-
| G12G33||IO_L3P_T0_DQS_PUDC_B_34IO_L10P_T1_AD11P_35||LA08_PLA31_P||
|-
| G13G34||IO_L3N_T0_DQS_34IO_L10N_T1_AD11N_35||LA08_NLA31_N||
|-
| G14G35||DGND||GND||
|-
| G15G36||IO_L22P_T3_34IO_L16P_T2_35||LA12_PLA33_P||
|-
| G16G37||IO_L22N_T3_34IO_L16N_T2_35||LA12_NLA33_N||
|-
| G17G38||DGND||GND||
|-
| G18G39||IO_L19P_T3_34FMC_VADJ||LA16_PVADJ||
|-
| G19G40||IO_L19N_T3_VREF_34DGND||LA16_NGND|||} ==== LPC Row H ==== {| class="wikitable"
|-
| G20||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| G21H1||IO_L17P_T2_34FMC_VREF_A_M2C||LA20_PVREF_A_M2C||
|-
| G22H2||IO_L17N_T2_34FMC_PRSNT_M2C_L||LA20_NPRSNT_M2C_L||
|-
| G23H3||DGND||GND||
|-
| G24H4||IO_L1P_T0_AD0P_35IO_L12P_T1_MRCC_34||LA22_PCLK0_M2C_P||
|-
| G25H5||IO_L1N_T0_AD0N_35IO_L12N_T1_MRCC_34||LA22_NCLK0_M2C_N||
|-
| G26H6||DGND||GND||
|-
| G27H7||IO_L4P_T0_35IO_L7P_T1_34||LA25_PLA02_P||
|-
| G28H8||IO_L4N_T0_35IO_L7N_T1_34||LA25_NLA02_N||
|-
| G29H9||DGND||GND||
|-
| G30H10||IO_L8P_T1_AD10P_35IO_L5P_T0_34||LA29_PLA04_P||
|-
| G31H11||IO_L8N_T1_AD10N_35IO_L5N_T0_34||LA29_NLA04_N||
|-
| G32H12||DGND||GND||
|-
| G33H13||IO_L10P_T1_AD11P_35IO_L8P_T1_34||LA31_PLA07_P||
|-
| G34H14||IO_L10N_T1_AD11N_35IO_L8N_T1_34||LA31_NLA07_N||
|-
| G35H15||DGND||GND||
|-
| G36H16||IO_L16P_T2_35IO_L21P_T3_DQS_34||LA33_PLA11_P||
|-
| G37H17||IO_L16N_T2_35IO_L21N_T3_DQS_34||LA33_NLA11_N||
|-
| G38H18||DGND||GND||
|-
| G39H19||FMC_VADJIO_L18P_T2_34||VADJLA15_P||
|-
| G40H20||DGNDIO_L18N_T2_34||GNDLA15_N|||} ==== LPC Row H ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| H21||DGND||GND||
|-
| H1H22||FMC_VREF_A_M2CIO_L24P_T3_34||VREF_A_M2CLA19_P||
|-
| H2H23||FMC_PRSNT_M2C_LIO_L24N_T3_34||PRSNT_M2C_LLA19_N||
|-
| H3H24||DGND||GND||
|-
| H4H25||IO_L12P_T1_MRCC_34IO_L10P_T1_34||CLK0_M2C_PLA21_P||
|-
| H5H26||IO_L12N_T1_MRCC_34IO_L10N_T1_34||CLK0_M2C_NLA21_N||
|-
| H6H27||DGND||GND||
|-
| H7H28||IO_L7P_T1_34IO_L3P_T0_DQS_AD1P_35||LA02_PLA24_P||
|-
| H8H29||IO_L7N_T1_34IO_L3N_T0_DQS_AD1N_35||LA02_NLA24_N||
|-
| H9H30||DGND||GND||
|-
| H10H31||IO_L5P_T0_34IO_L7P_T1_AD2P_35||LA04_PLA28_P||
|-
| H11H32||IO_L5N_T0_34IO_L7N_T1_AD2N_35||LA04_NLA28_N||
|-
| H12H33||DGND||GND||
|-
| H13H34||IO_L8P_T1_34IO_L9P_T1_DQS_AD3P_35||LA07_PLA30_P||
|-
| H14H35||IO_L8N_T1_34IO_L9N_T1_DQS_AD3N_35||LA07_NLA30_N||
|-
| H15H36||DGND||GND||
|-
| H16H37||IO_L21P_T3_DQS_34IO_L15P_T2_DQS_AD12P_35||LA11_PLA32_P||
|-
| H17H38||IO_L21N_T3_DQS_34IO_L15N_T2_DQS_AD12N_35||LA11_NLA32_N||
|-
| H18H39||DGND||GND||
|-
| H19H40||IO_L18P_T2_34FMC_VADJ||LA15_PVADJ|||} ==== HPC Row J ==== {| class="wikitable"
|-
| H20||IO_L18N_T2_34||LA15_N||!Pin# !Pin name!Function!Notes
|-
| H21J1||DGND||GND||
|-
| H22J2||IO_L24P_T3_34IO_L11P_T1_SRCC_35||LA19_PCLK1_C2M_P||
|-
| H23J3||IO_L24N_T3_34IO_L11N_T1_SRCC_35||LA19_NCLK1_C2M_N||
|-
| H24J4||DGND||GND||
|-
| H25J5||IO_L10P_T1_34DGND||LA21_PGND||
|-
| H26J6||IO_L10N_T1_34IO_L18P_T2_AD13P_35||LA21_NHA03_P||
|-
| H27J7||DGNDIO_L18N_T2_AD13N_35||GNDHA03_N||
|-
| H28J8||IO_L3P_T0_DQS_AD1P_35DGND||LA24_PGND||
|-
| H29J9||IO_L3N_T0_DQS_AD1N_35IO_L22P_T3_AD7P_35||LA24_NHA07_P||
|-
| H30J10||DGNDIO_L22N_T3_AD7N_35||GNDHA07_N||
|-
| H31J11||IO_L7P_T1_AD2P_35DGND||LA28_PGND||
|-
| H32J12||IO_L7N_T1_AD2N_35<span style="color:#ff0000">not connected</span>||LA28_NHA11_P||
|-
| H33J13||DGND<span style="color:#ff0000">not connected</span>||GNDHA11_N||
|-
| H34J14||IO_L9P_T1_DQS_AD3P_35DGND||LA30_PGND||
|-
| H35J15||IO_L9N_T1_DQS_AD3N_35<span style="color:#ff0000">not connected</span>||LA30_NHA14_P||
|-
| H36J16||DGND<span style="color:#ff0000">not connected</span>||GNDHA14_N||
|-
| H37J17||IO_L15P_T2_DQS_AD12P_35DGND||LA32_PGND||
|-
| H38J18||IO_L15N_T2_DQS_AD12N_35<span style="color:#ff0000">not connected</span>||LA32_NHA18_P||
|-
| H39J19||DGND<span style="color:#ff0000">not connected</span>||GNDHA18_N||
|-
| H40J20||FMC_VADJDGND||VADJGND|||} ==== HPC Row J ==== {| class="wikitable"
|-
!Pin| J21||<span style="color:# !Pin name!Function!Notesff0000">not connected</span>||HA22_P||
|-
| J1J22||DGND<span style="color:#ff0000">not connected</span>||GNDHA22_N||
|-
| J2J23||IO_L11P_T1_SRCC_35DGND||CLK1_C2M_PGND||
|-
| J3J24||IO_L11N_T1_SRCC_35<span style="color:#ff0000">not connected</span>||CLK1_C2M_NHB01_P||
|-
| J4J25||DGND<span style="color:#ff0000">not connected</span>||GNDHB01_N||
|-
| J5J26||DGND||GND||
|-
| J6J27||IO_L18P_T2_AD13P_35<span style="color:#ff0000">not connected</span>||HA03_PHB07_P||
|-
| J7J28||IO_L18N_T2_AD13N_35<span style="color:#ff0000">not connected</span>||HA03_NHB07_N||
|-
| J8J29||DGND||GND||
|-
| J9J30||IO_L22P_T3_AD7P_35<span style="color:#ff0000">not connected</span>||HA07_PHB11_P||
|-
| J10J31||IO_L22N_T3_AD7N_35<span style="color:#ff0000">not connected</span>||HA07_NHB11_N||
|-
| J11J32||DGND||GND||
|-
| J12J33||<span style="color:#ff0000">not connected</span>||HA11_PHB15_P||
|-
| J13J34||<span style="color:#ff0000">not connected</span>||HA11_NHB15_N||
|-
| J14J35||DGND||GND||
|-
| J15J36||<span style="color:#ff0000">not connected</span>||HA14_PHB18_P||
|-
| J16J37||<span style="color:#ff0000">not connected</span>||HA14_NHB18_N||
|-
| J17J38||DGND||GND||
|-
| J18J39||<span style="color:#ff0000">not connected</span>||HA18_PVIO_B_M2C||
|-
| J19J40||<span style="color:#ff0000">not connected</span>DGND||GND||HA18_N|} ==== HPC Row K ==== {|class="wikitable"
|-
| J20||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| J21K1||<span style="color:#ff0000">not connected</span>||HA22_PVREF_B_M2C||
|-
| J22K2||<span style="color:#ff0000">not connected</span>DGND||HA22_NGND||
|-
| J23K3||DGND||GND||
|-
| J24K4||<span style="color:#ff0000">not connected</span>IO_L12P_T1_MRCC_35||HB01_PCLK1_M2C_P||
|-
| J25K5||<span style="color:#ff0000">not connected</span>IO_L12N_T1_MRCC_35||HB01_NCLK1_M2C_N||
|-
| J26K6||DGND||GND||
|-
| J27K7||<span style="color:#ff0000">not connected</span>IO_L17P_T2_AD5P_35||HB07_PHA02_P||
|-
| J28K8||<span style="color:#ff0000">not connected</span>IO_L17N_T2_AD5N_35||HB07_NHA02_N||
|-
| J29K9||DGND||GND||
|-
| J30K10||<span style="color:#ff0000">not connected</span>IO_L21P_T3_DQS_AD14P_35||HB11_PHA06_P||
|-
| J31K11||<span style="color:#ff0000">not connected</span>IO_L21N_T3_DQS_AD14N_35||HB11_NHA06_N||
|-
| J32K12||DGND||GND||
|-
| J33K13||<span style="color:#ff0000">not connected</span>IO_25_VRP_35||HB15_PHA10_P||
|-
| J34K14||<span style="color:#ff0000">not connected</span>||HB15_NHA10_N||
|-
| J35K15||DGND||GND||
|-
| J36K16||<span style="color:#ff0000">not connected</span>||HB18_PHA17_P_CC||
|-
| J37K17||<span style="color:#ff0000">not connected</span>||HB18_NHA17_N_CC||
|-
| J38K18||DGND||GND||
|-
| J39K19||<span style="color:#ff0000">not connected</span>||VIO_B_M2CHA21_P||
|-
| J40K20||DGND||GND<span style="color:#ff0000">not connected</span>||HA21_N|} ==== HPC Row K ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| K21||DGND||GND||
|-
| K1K22||<span style="color:#ff0000">not connected</span>||VREF_B_M2CHA23_P||
|-
| K2K23||DGND<span style="color:#ff0000">not connected</span>||GNDHA23_N||
|-
| K3K24||DGND||GND||
|-
| K4K25||IO_L12P_T1_MRCC_35<span style="color:#ff0000">not connected</span>||CLK1_M2C_PHB00_P_CC||
|-
| K5K26||IO_L12N_T1_MRCC_35<span style="color:#ff0000">not connected</span>||CLK1_M2C_NHB00_N_CC||
|-
| K6K27||DGND||GND||
|-
| K7K28||IO_L17P_T2_AD5P_35<span style="color:#ff0000">not connected</span>||HA02_PHB06_P_CC||
|-
| K8K29||IO_L17N_T2_AD5N_35<span style="color:#ff0000">not connected</span>||HA02_NHB06_N_CC||
|-
| K9K30||DGND||GND||
|-
| K10K31||IO_L21P_T3_DQS_AD14P_35<span style="color:#ff0000">not connected</span>||HA06_PHB10_P||
|-
| K11K32||IO_L21N_T3_DQS_AD14N_35<span style="color:#ff0000">not connected</span>||HA06_NHB10_N||
|-
| K12K33||DGND||GND||
|-
| K13K34||IO_25_VRP_35<span style="color:#ff0000">not connected</span>||HA10_PHB14_P||
|-
| K14K35||<span style="color:#ff0000">not connected</span>||HA10_NHB14_N||
|-
| K15K36||DGND||GND||
|-
| K16K37||<span style="color:#ff0000">not connected</span>||HA17_P_CCHB17_P_CC||
|-
| K17K38||<span style="color:#ff0000">not connected</span>||HA17_N_CCHB17_N_CC||
|-
| K18K39||DGND||GND||
|-
| K19K40||<span style="color:#ff0000">not connected</span>||HA21_PVIO_B_M2C|||} === Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
| K20||<span style="color:!Pin#ff0000">not connected</span>||HA21_N||!Pin name!Function!Notes
|-
| K211, 4, 9, 12 ||DGND||GNDGround ||-
|-
| K222 ||<span style="color:#ff0000">not connected</span>SPI0_CS0n ||HA23_P- ||-
|-
| K233 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_SCLK/span>NAND_IO1 ||HA23_N- ||-
|-
| K245 ||DGNDZYNQ_SPI0_DQ0/NAND_ALE ||GND- ||-
|-
| K256 ||<span style="color:#ff0000">not connected<NAND_CS0/span>SPI0_CS1 ||HB00_P_CC- ||-
|-
| K267 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ2/span>NAND_IO2 ||HB00_N_CC- ||-
|-
| K278 ||DGNDZYNQ_SPI0_DQ1/NAND_WE ||GND- ||-
|-
| K2810 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ3/span>NAND_IO0 ||HB06_P_CC- ||-
|-
| K2911 ||<span style="color:#ff0000">not connected</span>ZYNQ_NAND_RD_B ||HB06_N_CC- ||-
|-
| K30||DGND||GND|} ==== Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
|-
!Pin# !Pin name!Function!Notes|-|1 || K31MON_VCCPLL ||<span style="color:#ff0000">not connected</span>- || -|-|2 || MON_3.3V ||HB10_P- ||-
|-
| K323 ||<span style="color:#ff0000">not connected</span>MON_XADC_VCC ||HB10_N- ||-
|-
| K334 ||DGNDMON_1V2_ETH ||GND- ||-
|-
| K345 ||<span style="color:#ff0000">not connected</span>MON_FPGA_VDDIO_BANK35 ||HB14_P- ||-
|-
| K356 ||<span style="color:#ff0000">not connected</span>MON_VDDQ_1V5 ||HB14_N- ||-
|-
| K367 ||DGNDMON_FPGA_VDDIO_BANK34 ||GND- ||-
|-
| K378 ||<span style="color:#ff0000">not connected</span>MON_1.8V ||HB17_P_CC- ||-
|-
| K389 ||<span style="color:#ff0000">not connected</span>MON_FPGA_VDDIO_BANK13 ||HB17_N_CC- ||-
|-
| K3910 ||DGNDMON_1.0V ||GND- ||-
|-
| K4011 ||<span style="color:#ff0000">not connected</span>MON_1.8V_IO ||VIO_B_M2C- ||-|}-|12 || MON_MGTAVCC || - || -|-|13 || MON_MGTAVTT || - || -|-=== Pin strip connectors ===|14 || MON_MGTAVCCAUX || - || -|-==== SPI|15,NAND 16 || DGND || Ground || - JP13 ====|-|} 
JP13 ==== Ethernet GPIO - JP18 ====JP18 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 42, 95, 12 <br>6, 16|| DGND || Ground || -
|-
|2 3 || SPI0_CS0n CLK125_NDO|| - || -
|-
|3 4 || ZYNQ_SPI0_SCLK/NAND_IO1 ETH1_CLK125_NDO || - || -
|-
|5 7 || ZYNQ_SPI0_DQ0/NAND_ALE ETH_MDC || - || -
|-
|6 8 || NAND_CS0/SPI0_CS1 ETH1_MDC || - || -
|-
|7 9 || ZYNQ_SPI0_DQ2/NAND_IO2 ETH_MDIO || - || -
|-
|8 10 || ZYNQ_SPI0_DQ1/NAND_WE ETH1_MDIO || - || -
|-
|10 11 || ZYNQ_SPI0_DQ3/NAND_IO0 ETH_INTn || - || -|-|12 || ETH1_INTn || - || -|-|13 || PS_MIO51_501 || - || -|-|14 || ETH1_RESETn || - || -
|-
|11 15 || ZYNQ_NAND_RD_B PS_MIO50_501 || - || -
|-
|}
==== Voltage Monitor - JP15 ====
JP15 ==== SPI,NAND - JP19 ====JP19 is a 1612-pin 8x2x26x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 , 11, 12|| MON_VCCPLL DGND || - Ground || -
|-
|2 || MON_3.3V NAND_BUSY|| - || -
|-
|3 || MON_XADC_VCC ZYNQ_NAND_CLE || - || -
|-
|4 || MON_1V2_ETH NAND_IO3 || - || -
|-
|5 || MON_FPGA_VDDIO_BANK35 NAND_IO4 || - || -
|-
|6 || MON_VDDQ_1V5 NAND_IO5 || - || -
|-
|7 || MON_FPGA_VDDIO_BANK34 NAND_IO6 || - || -
|-
|8 || MON_1.8V NAND_IO7 || - || -
|-
|9 || MON_FPGA_VDDIO_BANK13 CONN_SPI_RSTn || - || -
|-
|10 || MON_1.0V MEM_WPn || - || -|-|11 || MON_1.8V_IO || - || -|-|12 || MON_MGTAVCC || - || -|-|13 || MON_MGTAVTT || - || -|-|14 || MON_MGTAVCCAUX || - || -|-|15, 16 || DGND || Ground || -
|-
|}
 ==== Ethernet GPIO FPGA, WatchDog, RTC, RST - JP18 JP22 ====JP18 JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2, 5,<br>6, 16|| DGND FPGA_INIT_B|| Ground - || -
|-
|3 2 || CLK125_NDORTC_32KHZ || - || -
|-
|4 3 || ETH1_CLK125_NDO FPGA_PROGRAM_B|| - || -
|-
|7 4 || ETH_MDC RTC_RST || - || -
|-
|8 5 || ETH1_MDC FPGA_DONE || - || -
|-
|9 6 || ETH_MDIO RTC_INT/SQW || - || -
|-
|7, 8 || DGND || Ground || -|-|9 || WD_SET0 || - || -|-|10 || ETH1_MDIO SYS_RSTn || - || -|-|11 || WD_SET1 || - || -
|-
|11 12 ||ETH_INTn PORSTn || - || -
|-
|12 13 || ETH1_INTn WD_SET2 || - || -
|-
|13 14 || PS_MIO51_501 MRSTn || - || -
|-
|14 15 || ETH1_RESETn PS_MIO15_500 || - || -
|-
|15 16 || PS_MIO50_501 CB_PWR_GOOD || - || -
|-
|}
 ==== SPI,NAND AUX PINs - JP19 JP29 ====JP19 JP29 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 11, 12|| DGND EVB_1.8V || Ground - || -
|-
|2 || NAND_BUSY3.3V || - || -
|-
|3 || ZYNQ_NAND_CLE PS_I2C0_DAT|| - || -
|-
|4 || NAND_IO3 I2C0_SDA || - || -|-|5 || PS_I2C0_CK || - || -|-|6 || I2C0_SCL || - || -|-|7, 8,<br>13 || DGND || Ground || -
|-
|5 9 || NAND_IO4 EXT_VMON2_V1 || - || -Mount option
|-
|6 10, 16 || NAND_IO5 XADC_AGND || - Analog Ground || -
|-
|7 11 || NAND_IO6 EXT_VMON2_V2 || - || -Mount option
|-
|8 12 || NAND_IO7 XADC_VN_R || - || -
|-
|9 14 || CONN_SPI_RSTn XADC_VP_R || - || -
|-
|10 15 || MEM_WPn INA_ALERT || - || -
|-
|}
==== FPGA, WatchDog, RTC, RST - JP22 ====JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorPlease note that:
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption ==== ADC - JP30, JP31, JP32 ==== JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors: JP30:{| class="wikitable" |-!Pin# !Pin name!Function!Notes
|-
|1 || FPGA_INIT_B|| - || -!Pin# !Pin name!Function!Notes
|-
|2 || RTC_32KHZ FPGA_BANK35_AD0N || - AD0_N || -Mount option
|-
|3 || FPGA_PROGRAM_BFPGA_BANK35_AD1P || - AD1_P || -Mount option
|-
|4 || RTC_RST FPGA_BANK35_AD0P || - AD0_P || -Mount option
|-
|5 || FPGA_DONE FPGA_BANK35_AD1N || - AD1_N || -Mount option
|-
|6 8 || RTC_INT/SQW FPGA_BANK35_AD2P || - AD2_P || -Mount option
|-
|7, 8 9 || DGND FPGA_BANK35_AD3P || Ground AD3_P || -Mount option
|-
|9 10 || WD_SET0 FPGA_BANK35_AD2N || - AD2_N || -Mount option
|-
|10 11 || SYS_RSTn FPGA_BANK35_AD3N || - AD3_N || -Mount option
|-
|11 14 || WD_SET1 FPGA_BANK35_AD4P || - AD4_P || -Mount option
|-
|12 15 || PORSTn FPGA_BANK35_AD5P || - AD5_P || -Mount option
|-
|13 16 || WD_SET2 FPGA_BANK35_AD4N || - AD4_N || -Mount option
|-
|14 1, 6, 7,<br>12, 13 || MRSTn || - || -|-|15 || PS_MIO15_500 || - || -|-|16 || CB_PWR_GOOD DGND || - || -
|-
|}
==== AUX PINs - JP29 ====JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorJP31: 
{| class="wikitable"
|-
!Notes
|-
|1 || EVB_1.8V FPGA_BANK35_AD5N || - AD5_N || -Mount option
|-
|2 4 || 3.3V FPGA_BANK35_AD6P || - AD6_P || -Mount option
|-
|3 5 || PS_I2C0_DATFPGA_BANK35_AD7P || - AD7_P || -Mount option
|-
|4 6 || I2C0_SDA FPGA_BANK35_AD6N || - AD6_N || -Mount option
|-
|5 7 || PS_I2C0_CK FPGA_BANK35_AD7N || - AD7_N || -Mount option
|-
|6 10 || I2C0_SCL FPGA_BANK35_AD8P || - AD8_P || -Mount option
|-
|7, 8,<br>13 11 || DGND FPGA_BANK35_AD9P || Ground AD9_P || -Mount option
|-
|9 12 || EXT_VMON2_V1 FPGA_BANK35_AD8N || - AD8_N || Mount option
|-
|10, 16 13 || XADC_AGND FPGA_BANK35_AD9N || Analog Ground AD9_N || -Mount option
|-
|11 16 || EXT_VMON2_V2 FPGA_BANK35_AD10P || - AD10_P || Mount option
|-
|12 || XADC_VN_R || - || -|-|2, 3, 8,<br>9, 14 || XADC_VP_R || - || -|-|, 15 || INA_ALERT DGND || - || -
|-
|}
Please note that: * Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption ==== ADC - JP30, JP31, JP32 ==== JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors: JP30:
{| class="wikitable"
|-
!Notes
|-
|2 1 || FPGA_BANK35_AD0N FPGA_BANK35_AD11P || AD0_N AD11_P || Mount option
|-
|3 2 || FPGA_BANK35_AD1P FPGA_BANK35_AD10N || AD1_P AD10_N || Mount option
|-
|4 3 || FPGA_BANK35_AD0P FPGA_BANK35_AD11N || AD0_P AD11_N || Mount option
|-
|5 6 || FPGA_BANK35_AD1N FPGA_BANK35_AD12P || AD1_N AD12_P || Mount option
|-
|8 7 || FPGA_BANK35_AD2P FPGA_BANK35_AD13P || AD2_P AD13_P || Mount option
|-
|9 8 || FPGA_BANK35_AD3P FPGA_BANK35_AD12N || AD3_P AD12_N || Mount option
|-
|10 9 || FPGA_BANK35_AD2N FPGA_BANK35_AD13N || AD2_N AD13_N || Mount option
|-
|11 12 || FPGA_BANK35_AD3N FPGA_BANK35_AD14P || AD3_N AD14_P || Mount option
|-
|14 13 || FPGA_BANK35_AD4P FPGA_BANK35_AD15P || AD4_P AD15_P || Mount option
|-
|15 14 || FPGA_BANK35_AD5P FPGA_BANK35_AD14N || AD5_P AD14_N || Mount option
|-
|16 15 || FPGA_BANK35_AD4N FPGA_BANK35_AD15N || AD4_N AD15_N || Mount option
|-
|14, 65, 710,<br>1211, 13 16 || DGND || - || -
|-
|}
JP31=== Digilent Pmod™ Compatible headers === Please note that:* Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector  ==== Digilent Pmod™ Compatible - JP17 ==== JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name
!Function
!Notes
|-
|1 || FPGA_BANK35_AD5N PMOD_A0 || AD5_N || Mount option-
|-
|4 2 || FPGA_BANK35_AD6P PMOD_A4 || AD6_P || Mount option-
|-
|5 3 || FPGA_BANK35_AD7P PMOD_A1 || AD7_P || Mount option-
|-
|6 4 || FPGA_BANK35_AD6N PMOD_A5 || AD6_N || Mount option-
|-
|7 5 || FPGA_BANK35_AD7N PMOD_A2 || AD7_N || Mount option-
|-
|10 6 || FPGA_BANK35_AD8P PMOD_A6 || AD8_P || Mount option-
|-
|11 7 || FPGA_BANK35_AD9P PMOD_A3 || AD9_P || Mount option-
|-
|12 8 || FPGA_BANK35_AD8N PMOD_A7 || AD8_N || Mount option-
|-
|13 9, 10 || FPGA_BANK35_AD9N DGND || AD9_N Ground || Mount option-
|-
|16 || FPGA_BANK35_AD10P || AD10_P || Mount option11, 12 |-|2, 3, 8,<br>9, 14, 15 || DGND .3V || - || -
|-
|}
JP32==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD11P PMOD_B0 || AD11_P - || Mount option-
|-
|2 || FPGA_BANK35_AD10N PMOD_B4 || AD10_N - || Mount option-
|-
|3 || FPGA_BANK35_AD11N PMOD_B1 || AD11_N - || Mount option-
|-
|6 4 || FPGA_BANK35_AD12P PMOD_B5 || AD12_P - || Mount option-
|-
|7 5 || FPGA_BANK35_AD13P PMOD_B2 || AD13_P - || Mount option-
|-
|8 6 || FPGA_BANK35_AD12N PMOD_B6 || AD12_N - || Mount option-
|-
|9 7 || FPGA_BANK35_AD13N PMOD_B3 || AD13_N - || Mount option-
|-
|12 8 || FPGA_BANK35_AD14P PMOD_B7 || AD14_P - || Mount option-
|-
|13 9, 10 || FPGA_BANK35_AD15P DGND || AD15_P Ground || Mount option-
|-
|14 || FPGA_BANK35_AD14N || AD14_N || Mount option|-|15 || FPGA_BANK35_AD15N || AD15_N || Mount option|-|4, 5, 10,<br>11, 16 12 || DGND 3.3V || - || -
|-
|}
===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
=== Digilent Pmod™ Compatible headers =PL's I/O voltage selections==PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:*'''each bank must be powered even if none of its I/Os is used'''*'''voltage selection must be done before powering up the board'''.
Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built The following table recaps the characteristics of the PL's I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2banks,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegratedin terms of allowable power supplies.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector
{|class="wikitable" style="text-align: center;"! rowspan="2" style= Digilent Pmod™ Compatible "text-align: center; font- JP17 weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" style= JP17 is a 12"text-align: center; font-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connectorweight:bold;" | Bank #13 {| class! colspan="2" style="wikitabletext-align: center; font-weight: bold;" | Bank #35
|-
!Pin# | style="text-align: center; font-weight: bold;" | Type [1]!Pin name| style="text-align: center; font-weight: bold;" | I/O voltage setting!Function| style="text-align: center; font-weight: bold;" | Type [1]!Notes| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
|style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1 .2 - 3.3V)| style="text-align: center;" | User defined|style="text-align: center;" |PMOD_A0 HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined
|-
|style="text-align: center;" | 7030(SBG485 package)| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" |User defined|PMOD_A4 style="text-align: center;" |HR(1.2 - 3.3V)| style="text-align: center;" |User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance ===BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''. Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details. Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)===={|class="wikitable" style="text-align: center;"|+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" |3 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP25.1-2! style="text-align: center; font-weight: bold;" |PMOD_A1 JP25.3-4! style="text-align: center; font-weight: bold;" |JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" |JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12
|-
|style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #35 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4 ! style="text-align: center; font-weight: bold;" |JP27.5-6! style="text-align: center; font-weight: bold;" |PMOD_A5 JP27.7-8! style="text-align: center; font-weight: bold;" |JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|5 style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" |'''closed'''|PMOD_A2 style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | open|} ====Examples of valid combinations for Zynq 7015-based SOMs===={|class="wikitable" style="text-align: center;"|+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" |6 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP25.1-2! style="text-align: center; font-weight: bold;" |PMOD_A6 JP25.3-4! style="text-align: center; font-weight: bold;" |JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" |JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12
|-
|7 style="text-align: center;" |1.2|PMOD_A3 style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|8 style="text-align: center;" |1.5|PMOD_A7 style="text-align: center;" |open| style="text-align: center;" |'''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|9, 10 style="text-align: center;" |1.8|DGND style="text-align: center;" |open|Ground style="text-align: center;" |'''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|11, 12 style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" |open|3.3V style="text-align: center;" | '''closed'''| style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
{|class="wikitable" style="text-align: center;"|+Bank #35 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style="text-align: center; font-weight: bold;" | JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open |}  {|class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style= Digilent Pmod™ Compatible "text- JP23 align: center;" | open|} ====Advanced information about voltage selection connectors====JP23 ===== Bank 13 VDDIO selection connector (JP25) =====JP25 is a 12-pin 6x2x2.54 pitch vertical headerused for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B13_1V6|| adds +1 .6V to VDDIO_BANK13 || -|-|4 || LDO_B13_800mV||PMOD_B0 adds +800mV to VDDIO_BANK13 || - |-|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -|-|2 8 || LDO_B13_200mV||adds +200mV to VDDIO_BANK13 |PMOD_B4 |-| - |10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -|-|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -|-|1, 3 , 5, 7, 9, 11 ||PMOD_B1 DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {|class="wikitable" |PMOD_B5 -!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || - |-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|5 6 || LDO_B35_400mV||adds +400mV to VDDIO_BANK35 |PMOD_B2 |-| - |8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|6 10 || LDO_B35_100mV||adds +100mV to VDDIO_BANK35 |PMOD_B6 |-| - |12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7 , 9, 11 ||PMOD_B3 DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)||selects 3.3V VADJ |PMOD_B7 |-| - |4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|9, 10 ||DGND VADJ_FB (100K)||Ground selects 1.2V VADJ || -|-|11, 12 ||RFU|| Reserved || -|-|1, 3.3V , 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V
==Schematics==
 * ORCAD: http[[mirror:bora/hw/BoraXEVB/wwwBORAXEVB-1.dave6.eu/system/files/area1-BELK-riservata/boraxevbdsn.zip|BORAXEVB-1.06.31-BELK-dsn.zip]]* PDF : http[[mirror:bora/hw/wwwBoraXEVB/S-EVBBX0000C0R-1.dave6.eu/system/files/area-riservata/1_color.pdf|BoraXEVB-S-EVBBX0000C0R-1.26.01.pdf]]
==BOM==
* BoraXEVB: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB_S.EVBBX0000C0R.dave1.eu/system/files/area-riservata/boraxevb-BOM_S6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.26.0.CSV_CSV.zip]]
==Layout==
* http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-CS143714_assem_view.davepdf|boraxevb-CS143714_assem_view.eupdf]]==PCB design (Mentor PADS)==* [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb-CS143714_assembly_viewCS143714.zip|CS143714.pdfzip]]
==Mechanical==
* DXF: http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-2D-CS143714.davedxf.eu/system/files/areazip|boraxevb-2D-riservata/boraxevb_2D_CS143714CS143714.dxf.zip]]* IDF (3D): http[[mirror:bora/hw/BoraXEVB/wwwboraxevb-3D-CS143714.davezip|boraxevb-3D-CS143714.euzip]]* STEP (3D): [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb_3D_CS143714boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
U0005
a000298_approval, dave_user
299
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