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BoraXEVB

14,446 bytes added, 13:15, 14 June 2019
→‎Schematics
{{Applies To BoraX}}
{{InfoBoxBottom}}
 
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOM. However, it can host different models of BoraX SOM. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
==Introduction==
Bora Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|Bora Xpress system-on-module]].
==Block Diagram==
The following picture shows Bora BORA Xpress EVB block diagram:
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]
|-
| FMC connector
| The FMC For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
|-
|}
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
 
<b>(*)</b> Boot mode from NAND in not supported on actual BSP version
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora BORA Xpress module watchdog.
For more details please refer to [[Watchdog (BORAXpress)|this page]].
| WD_SET2 = '0' || OFF || ON
|}
 
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
=== JTAG ===
=== BANK13 VDDIO selector JTAG port is available as two different mechanical connectors:* 2.00mm- JP25 ===pitch 7x2 header (Xilinx standard)JP25 is a 12* 2.54mm-pin 6x2x2.54 pitch vertical 10x2 header used for the selection - through jumpers - of the bank supply voltages(ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. The following table reports the pinout of * JTAG on BORA Xpress EVB is also connected to the FMC connector:. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ====
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGND|| - || -|-|2 || LDO_B13_1V63.3V|| adds +1.6V to VDDIO_BANK13 - || -
|-
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|2 1 || LDO_B35_1V63.3V|| adds +1.6V to VDDIO_BANK35 - || -
|-
|4 2 || LDO_B35_800mV3.3V|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 3, 11, 17, 19 || LDO_B35_400mVN.C.|| adds +400mV to VDDIO_BANK35 - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_200mVDGND|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 5 || LDO_B35_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK35 - || -
|-
|12 7 || LDO_B35_50mVJTAG_TMS|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 || DGNDJTAG_TCK|| - || -|-|13 || JTAG_TDO|| - || -|-|15 || JTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed === UART1 -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator === VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 3|UART_EXT_TX| VADJ_FB (51K1)Transmit line|| selects 1.8V VADJ || -Connected to protection diode array
|-
|8 5|DGND| VADJ_FB (68K)Ground|| selects 1.5V VADJ || -
|-
|10 7, 8|| VADJ_FB (100K)|| selects 1N.C.2V VADJ || -|-N.C.|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -Connected to protection diode array
|-
|}
The jumper configurations are:# Jumper on 1=== USB OTG -2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2VJ19 ===
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
=== JTAG ===
 
JTAG port is available as two different mechanical connectors:
* 2.00mm-pitch 7x2 header (Xilinx standard)
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
 
==== JTAG XILINX - J13 ====
 
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDUSB_OTG_VBUS || - || -
|-
|2 || 3.3VUSBM1 || - || -
|-
|4 3 || JTAG_TMSUSBP1 || - || -
|-
|6 4 || JTAG_TCKOTG_ID || - || -
|-
|8 5 || JTAG_TDOUSB_OTG_DGND || - || -
|-
|10 6, 7, 8, 9 || JTAG_TDI|| - || -|-|12 || N.C.|| - || -|-|14 || JTAG_TRSTnUSB_OTG_SHIELD || - || -
|-
|}
==== JTAG ARM MicroSD - J18 =J21 ===J18 J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a 20bidirectional 1.8V/3.3V voltage-pin 10x2x2level translator mounted on the BORA Xpress EVB.54 pitch vertical headerLevel shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1 || 3.3VPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|3, 11, 17, 19 || N.C.PS_SD0_CMD||| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND3.3V||| - || -
|-
|5 || JTAG_TDIPS_SD0_CLK||| - || -
|-
|7 6, 9, 10, 11, 12 || JTAG_TMSDGND||| - || -
|-
|9 7 || JTAG_TCKPS_SD0_DAT0||| - || -
|-
|13 8 || JTAG_TDOPS_SD0_DAT1||| - || -
|-
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
{| class="wikitable"
!Notes
|-
|1, 6, 4, 92 |N.C.|N.C.5V || - || -
|-
|23, 4 |UART_EXT_RX|Receive line3.3V |Connected to protection diode array| - || -
|-
|35, 6,<br> 9, 10,<br>19 |UART_EXT_TX|Transmit lineDGND |Connected to protection diode array| - || -
|-
|57 |DGND|GroundDWM_SD_CMD || - || -
|-
|7, 8|N.C.|N.C.DWM_SD_CLK |Connected to protection diode array| - || -
|-
|} === USB OTG 11 ||DWM_SD_DAT0 || - J19 === J19 is a standard USB MICRO AB connector. It is connected to the Bora Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector: {| class="wikitable" | -
|-
!Pin# !Pin name!Function!Notes|12, 14,<br>16, 18,<br>20, 22 ||N.C. || - || -
|-
|1 13 ||USB_OTG_VBUS DWM_SD_DAT1 || - || -|-|15 ||DWM_SD_DAT2 || - || -|-|17 ||DWM_SD_DAT3 || - || -|-|21 ||DWM_UART_RX || - || -|-|23 ||DWM_UART_CTS || - || -|-|24 ||DWM_BT_F5 || - || -|-|25 ||DWM_UART_TX || - || -
|-
|2 26 ||USBM1 DWM_BT_F2 || - || -
|-
|3 27 ||USBP1 DWM_UART_RTS || - || -
|-
|4 28 ||OTG_ID DWM_WIFI_IRQ || - || -
|-
|5 29 ||USB_OTG_DGND DWM_BT_EN || - || -
|-
|6, 7, 8, 9 30 ||USB_OTG_SHIELD DWM_WIFI_EN || - || -
|-
|}
=== MicroSD CAN - J21 J24 === J21 J24 is a microSD memory card connector10-pin 5x2x2. It is 54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the Bora Xpress SOM through a bidirectional 1CAN interface.8V/3This 2.3V voltage5mm-level translator mounted on the Bora Xpress EVB. Level shifter pitch header is required because MIO signals are 1.8Vcompatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 , 6,<br>7, 8,<br>9, 10 ||PS_SD0_DAT2|N.C. || - || -
|-
|2 , 5 ||PS_SD0_DAT3CAN_SHIELD || - || -|-|3 ||CAN_L || - || -
|-
|3 4 ||PS_SD0_CMD|CAN_H || - || -
|-
|} === Touch screen - J25===J25 is a ZIF 4 ||3-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB.3VThe following table reports the pinout of the connector: {||| - || -class="wikitable"
|-
|5 ||PS_SD0_CLK||| - || -!Pin# !Pin name!Function!Notes
|-
|6, 9, 10, 11, 12 1 ||DGND|TSC_YP || - || -
|-
|7 2 ||PS_SD0_DAT0|TSC_XP || - || -
|-
|8 3 ||PS_SD0_DAT1|TSC_YM || - || -
|-
|13 4 |3.3V|TSC_XM || - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== DWM (DAVE Wifi/BT module) socket LVDS - J23 J26 ===J23 J26 is a 52991vertical double row straight 20-0308 connector type (30 pinspin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, verticalZynq does not implement an LCD controller, 0however this can be integrated in FPGA fabric as shown by this example: https://wiki.50mm picth)analog. This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVBcom/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2 ||5V 3.3V_LCD || - || -
|-
|3, 4 , 7, 10,<br>13, 16, 19 ||3.3V DGND || - Ground || -
|-
|5, 6,<br> 9, 10,<br>19 ||DGND LCD_LVDS_D0- || - || -
|-
|7 6 ||DWM_SD_CMD LCD_LVDS_D0+ || - || -
|-
|8 ||DWM_SD_CLK LCD_LVDS_D1- || - || -
|-
|11 9 ||DWM_SD_DAT0 LCD_LVDS_D1+ || - || -
|-
|12, 14,<br>16, 18,<br>20, 22 11 ||N.C. LCD_LVDS_D2- || - || -
|-
|13 12 ||DWM_SD_DAT1 LCD_LVDS_D2+ || - || -
|-
|15 14 ||DWM_SD_DAT2 LCD_LVDS_CLK- || - || -
|-
|17 15 ||DWM_SD_DAT3 LCD_LVDS_CLK+ || - || -
|-
|21 17 ||DWM_UART_RX LCD_P17 || - || -
|-
|23 18 ||DWM_UART_CTS LCD_P18 || - || -
|-
|24 20 ||DWM_BT_F5 LCD_P20 || - || -
|-
|25 21,22 ||DWM_UART_TX DGND || - Ground || -Shield
|-
|26 ||DWM_BT_F2 || } === FPGA Mezzanine Card (FMC) Connector - || J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.|-|27 ||DWM_UART_RTS || - || -Please note that BoraXpress EVB FMC Connector is:|-* fully compliant to FMC LPC|28 ||DWM_WIFI_IRQ || - || -* partially compliant to FMC HPC because HPC side is not fully populated.|-|29 ||DWM_BT_EN || The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB- || FMC-routing.zip|-link]] a spreadsheet providing the same information is available for download.|30 ||DWM_WIFI_EN || - || -|For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|}this section]].
=== CAN - J24 = HPC Row A ====J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 6,<br>7, 8,<br>9, 10 A1||N.C. DGND||GND||| - | A2||MGTxRXP1||DP1_M2C_P|| -
|-
|2, 5 A3||CAN_SHIELD MGTxRXN1|| - DP1_M2C_N|| -
|-
|3 A4||CAN_L DGND|| - GND|| -
|-
|4 A5||CAN_H DGND|| - GND|| -
|-
|} === Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector: {A6||MGTxRXP2||DP2_M2C_P|| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A7||MGTxRXN2||DP2_M2C_N||
|-
|1 A8||TSC_YP DGND|| - GND|| -
|-
|2 A9||TSC_XP DGND|| - GND|| -
|-
|3 A10||TSC_YM MGTxRXP3|| - DP3_M2C_P|| -
|-
|4 A11||TSC_XM MGTxRXN3|| - DP3_M2C_N|| -
|-
|} === LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector: {A12||DGND||GND|| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A13||DGND||GND||
|-
|1, 2 A14||3.3V_LCD <span style="color:#ff0000">not connected</span>|| - DP4_M2C_P|| -
|-
|3, 4, 7, 10,A15||<span style="color:#ff0000">not connected<br/span>13, 16, 19 ||DP4_M2C_N|||-| A16||DGND || Ground GND|| -
|-
|5 A17||LCD_LVDS_D0- DGND|| - GND|| -
|-
|6 A18||LCD_LVDS_D0+ <span style="color:#ff0000">not connected</span>|| - DP5_M2C_P|| -
|-
|8 A19||LCD_LVDS_D1- <span style="color:#ff0000">not connected</span>|| - DP5_M2C_N|| -
|-
|9 A20||LCD_LVDS_D1+ DGND|| - GND|| -
|-
|11 A21||LCD_LVDS_D2- DGND|| - GND|| -
|-
|12 A22||LCD_LVDS_D2+ MGTxTXP1|| - DP1_C2M_P|| -
|-
|15 A23||LCD_LVDS_CLK+ MGTxTXN1|| - DP1_C2M_N|| -
|-
|17 A24||LCD_P17 DGND|| - GND|| -
|-
|18 A25||LCD_P18 DGND|| - GND|| -
|-
|20 A26||LCD_P20 MGTxTXP2|| - DP2_C2M_P|| -
|-
|21,22 A27||DGND MGTxTXN2|| Ground DP2_C2M_N|| Shield
|-
|} === FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BoraX signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipA28||DGND||GND|link]] a spreadsheet providing the same information is available for download. ==== HPC Row A ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A29||DGND||GND||
|-
| A1A30||DGNDMGTxTXP3||GNDDP3_C2M_P||
|-
| A2A31||MGTxRXP1MGTxTXN3||DP1_M2C_PDP3_C2M_N||
|-
| A3A32||MGTxRXN1DGND||DP1_M2C_NGND||
|-
| A4A33||DGND||GND||
|-
| A5A34||DGND<span style="color:#ff0000">not connected</span>||GNDDP4_C2M_P||
|-
| A6A35||MGTxRXP2<span style="color:#ff0000">not connected</span>||DP2_M2C_PDP4_C2M_N||
|-
| A7A36||MGTxRXN2DGND||DP2_M2C_NGND||
|-
| A8A37||DGND||GND||
|-
| A9A38||DGND<span style="color:#ff0000">not connected</span>||GNDDP5_C2M_P||
|-
| A10A39||MGTxRXP3<span style="color:#ff0000">not connected</span>||DP3_M2C_PDP5_C2M_N||
|-
| A11A40||MGTxRXN3DGND||DP3_M2C_NGND|||} ==== HPC Row B ==== {| class="wikitable"
|-
| A12||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| A13B1||DGNDRSVD||GNDRES1||
|-
| A14B2||<span style="color:#ff0000">not connected</span>DGND||DP4_M2C_PGND||
|-
| A15B3||<span style="color:#ff0000">not connected</span>DGND||DP4_M2C_NGND||
|-
| A16B4||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_M2C_P||
|-
| A17B5||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_M2C_N||
|-
| A18B6||<span style="color:#ff0000">not connected</span>DGND||DP5_M2C_PGND||
|-
| A19B7||<span style="color:#ff0000">not connected</span>DGND||DP5_M2C_NGND||
|-
| A20B8||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_M2C_P||
|-
| A21B9||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_M2C_N||
|-
| A22B10||MGTxTXP1DGND||DP1_C2M_PGND||
|-
| A23B11||MGTxTXN1DGND||DP1_C2M_NGND||
|-
| A24B12||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_M2C_P||
|-
| A25B13||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_M2C_N||
|-
| A26B14||MGTxTXP2DGND||DP2_C2M_PGND||
|-
| A27B15||MGTxTXN2DGND||DP2_C2M_NGND||
|-
| A28B16||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_M2C_P||
|-
| A29B17||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_M2C_N||
|-
| A30B18||MGTxTXP3DGND||DP3_C2M_PGND||
|-
| A31B19||MGTxTXN3DGND||DP3_C2M_NGND||
|-
| A32B20||DGNDMGTREFCLK1P||GNDGBTCLK1_M2C_P||
|-
| A33B21||DGNDMGTREFCLK1N||GNDGBTCLK1_M2C_N||
|-
| A34B22||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_PGND||
|-
| A35B23||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_NGND||
|-
| A36B24||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_C2M_P||
|-
| A37B25||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_C2M_N||
|-
| A38B26||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_PGND||
|-
| A39B27||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_NGND||
|-
| A40B28||DGND||GND<span style="color:#ff0000">not connected</span>||DP8_C2M_P|} ==== HPC Row B ==== {| class="wikitable"
|-
!Pin| B29||<span style="color:# !Pin name!Function!Notesff0000">not connected</span>||DP8_C2M_N||
|-
| B1B30||RSVDDGND||RES1GND||
|-
| B2B31||DGND||GND||
|-
| B3B32||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_C2M_P||
|-
| B4B33||<span style="color:#ff0000">not connected</span>||DP9_M2C_PDP7_C2M_N||
|-
| B5B34||<span style="color:#ff0000">not connected</span>DGND||DP9_M2C_NGND||
|-
| B6B35||DGND||GND||
|-
| B7B36||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_C2M_P||
|-
| B8B37||<span style="color:#ff0000">not connected</span>||DP8_M2C_PDP6_C2M_N||
|-
| B9B38||<span style="color:#ff0000">not connected</span>DGND||DP8_M2C_NGND||
|-
| B10B39||DGND||GND||
|-
| B11B40||DGNDRSVD||GNDRES0|||} ==== LPC Row C ==== {| class="wikitable"
|-
| B12||<span style="color:!Pin#ff0000">not connected</span>||DP7_M2C_P||!Pin name!Function!Notes
|-
| B13C1||<span style="color:#ff0000">not connected</span>DGND||DP7_M2C_NGND||
|-
| B14C2||DGNDMGTxTXP0||GNDDP0_C2M_P||
|-
| B15C3||DGNDMGTxTXN0||GNDDP0_C2M_N||
|-
| B16C4||<span style="color:#ff0000">not connected</span>DGND||DP6_M2C_PGND||
|-
| B17C5||<span style="color:#ff0000">not connected</span>DGND||DP6_M2C_NGND||
|-
| B18C6||DGNDMGTxRXP0||GNDDP0_M2C_P||
|-
| B19C7||DGNDMGTxRXN0||GNDDP0_M2C_N||
|-
| B20C8||MGTREFCLK1PDGND||GBTCLK1_M2C_PGND||
|-
| B21C9||MGTREFCLK1NDGND||GBTCLK1_M2C_NGND||
|-
| B22C10||DGNDIO_L23P_T3_34||GNDLA06_P||
|-
| B23C11||DGNDIO_L23N_T3_34||GNDLA06_N||
|-
| B24C12||<span style="color:#ff0000">not connected</span>DGND||DP9_C2M_PGND||
|-
| B25C13||<span style="color:#ff0000">not connected</span>DGND||DP9_C2M_NGND||
|-
| B26C14||DGNDIO_L2P_T0_34||GNDLA10_P||
|-
| B27C15||DGNDIO_L2N_T0_34||GNDLA10_N||
|-
| B28C16||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_PGND||
|-
| B29C17||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_NGND||
|-
| B30C18||DGNDIO_L1P_T0_34||GNDLA14_P|||-| C19||IO_L1N_T0_34||LA14_N||
|-
| B31C20||DGND||GND||
|-
| B32C21||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_PGND||
|-
| B33C22||<span style="color:#ff0000">not connected</span>IO_L16P_T2_34||DP7_C2M_NLA18_P_CC||
|-
| B34C23||DGNDIO_L16N_T2_34||GNDLA18_N_CC||
|-
| B35C24||DGND||GND||
|-
| B36C25||<span style="color:#ff0000">not connected</span>DGND||DP6_C2M_PGND||
|-
| B37C26||<span style="color:#ff0000">not connected</span>IO_L6P_T0_35||DP6_C2M_NLA27_P||
|-
| B38C27||DGNDIO_L6N_T0_VREF_35||GNDLA27_N||
|-
| B39C28||DGND||GND||
|-
| B40C29||RSVDDGND||RES0GND|||} ==== LPC Row C ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| C30||I2C0_SCL||SCL||
|-
| C1C31||DGNDI2C0_SDA||GNDSDA||
|-
| C2C32||MGTxTXP0DGND||DP0_C2M_PGND||
|-
| C3C33||MGTxTXN0DGND||DP0_C2M_NGND||
|-
| C4C34||DGNDGA0||GNDGA0||
|-
| C5C35||DGNDFMC_12P0V||GND12P0V||
|-
| C6C36||MGTxRXP0DGND||DP0_M2C_PGND||
|-
| C7C37||MGTxRXN0FMC_12P0V||DP0_M2C_N12P0V||
|-
| C8C38||DGND||GND||
|-
| C9C39||DGNDFMC_3P3V||GND3P3V||
|-
| C10C40||IO_L23P_T3_34DGND||LA06_PGND|||} ==== LPC Row D ==== {| class="wikitable"
|-
| C11||IO_L23N_T3_34||LA06_N||!Pin# !Pin name!Function!Notes
|-
| C12D1||DGNDIO_25_VRP_34||GNDPG_C2M||
|-
| C13D2||DGND||GND||
|-
| C14D3||IO_L2P_T0_34DGND||LA10_PGND||
|-
| C15D4||IO_L2N_T0_34MGTREFCLK0P||LA10_NGBTCLK0_M2C_P||
|-
| C16D5||DGNDMGTREFCLK0N||GNDGBTCLK0_M2C_N||
|-
| C17D6||DGND||GND||
|-
| C18D7||IO_L1P_T0_34DGND||LA14_PGND||
|-
| C19D8||IO_L1N_T0_34IO_L14P_T2_SRCC_34||LA14_NLA01_P_CC||
|-
| C20D9||DGNDIO_L14N_T2_SRCC_34||GNDLA01_N_CC||
|-
| C21D10||DGND||GND||
|-
| C22D11||IO_L16P_T2_34IO_L9P_T1_DQS_34||LA18_P_CCLA05_P||
|-
| C23D12||IO_L16N_T2_34IO_L9N_T1_DQS_34||LA18_N_CCLA05_N||
|-
| C24D13||DGND||GND||
|-
| C25D14||DGNDIO_L6P_T0_34||GNDLA09_P||
|-
| C26D15||IO_L6P_T0_35IO_L6N_T0_VREF_34||LA27_PLA09_N||
|-
| C27D16||IO_L6N_T0_VREF_35DGND||LA27_NGND||
|-
| C28D17||DGNDIO_L20P_T3_34||GNDLA13_P||
|-
| C29D18||DGNDIO_L20N_T3_34||GNDLA13_N||
|-
| C30D19||I2C0_SCLDGND||SCLGND||
|-
| C31D20||I2C0_SDAIO_L15P_T2_DQS_34||SDALA17_P_CC||
|-
| C32D21||DGNDIO_L15N_T2_DQS_34||GNDLA17_N_CC||
|-
| C33D22||DGND||GND||
|-
| C34D23||GA0IO_L2P_T0_AD8P_35||GA0LA23_P||
|-
| C35D24||FMC_12P0VIO_L2N_T0_AD8N_35||12P0VLA23_N||
|-
| C36D25||DGND||GND||
|-
| C37D26||FMC_12P0VIO_L5P_T0_AD9P_35||12P0VLA26_P||
|-
| C38D27||DGNDIO_L5N_T0_AD9N_35||GNDLA26_N||
|-
| C39D28||FMC_3P3VDGND||3P3VGND||
|-
| C40D29||JTAG_TCK||TCK|||-| D30||JTAG_TDI||TDI|||-| D31||FMC_TDO_ZYNQ_TDI||TDO|||-| D32||FMC_3P3VAUX||3P3VAUX|||-| D33||JTAG_TMS||TMS|||-| D34||JTAG_TRSTn||TRST_L|||-| D35||GA0||GA1|||-| D36||FMC_3P3V||3P3V|||-| D37||DGND||GND|||-| D38||FMC_3P3V||3P3V|||-| D39||DGND||GND|||-| D40||FMC_3P3V||3P3V||
|}
==== LPC HPC Row D E ====
{| class="wikitable"
!Notes
|-
| D1E1||IO_25_VRP_34DGND||PG_C2MGND||
|-
| D2E2||DGNDIO_L14P_T2_AD4P_SRCC_35||GNDHA01_P_CC||
|-
| D3E3||DGNDIO_L14N_T2_AD4N_SRCC_35||GNDHA01_N_CC||
|-
| D4E4||MGTREFCLK0PDGND||GBTCLK0_M2C_PGND||
|-
| D5E5||MGTREFCLK0NDGND||GBTCLK0_M2C_NGND||
|-
| D6E6||DGNDIO_L20P_T3_AD6P_35||GNDHA05_P||
|-
| D7E7||DGNDIO_L20N_T3_AD6N_35||GNDHA05_N||
|-
| D8E8||IO_L14P_T2_SRCC_34DGND||LA01_P_CCGND||
|-
| D9E9||IO_L14N_T2_SRCC_34IO_L24P_T3_AD15P_35||LA01_N_CCHA09_P||
|-
| D10E10||DGNDIO_L24N_T3_AD15N_35||GNDHA09_N||
|-
| D11E11||IO_L9P_T1_DQS_34DGND||LA05_PGND||
|-
| D12E12||IO_L9N_T1_DQS_34<span style="color:#ff0000">not connected</span>||LA05_NHA13_P||
|-
| D13E13||DGND<span style="color:#ff0000">not connected</span>||GNDHA13_N||
|-
| D14E14||IO_L6P_T0_34DGND||LA09_PGND||
|-
| D15E15||IO_L6N_T0_VREF_34<span style="color:#ff0000">not connected</span>||LA09_NHA16_P||
|-
| D16E16||DGND<span style="color:#ff0000">not connected</span>||GNDHA16_N||
|-
| D17E17||IO_L20P_T3_34DGND||LA13_PGND||
|-
| D18E18||IO_L20N_T3_34<span style="color:#ff0000">not connected</span>||LA13_NHA20_P||
|-
| D19E19||DGND<span style="color:#ff0000">not connected</span>||GNDHA20_N||
|-
| D20E20||IO_L15P_T2_DQS_34DGND||LA17_P_CCGND||
|-
| D21E21||IO_L15N_T2_DQS_34<span style="color:#ff0000">not connected</span>||LA17_N_CCHB03_P||
|-
| D22E22||DGND<span style="color:#ff0000">not connected</span>||GNDHB03_N||
|-
| D23E23||IO_L2P_T0_AD8P_35DGND||LA23_PGND||
|-
| D24E24||IO_L2N_T0_AD8N_35<span style="color:#ff0000">not connected</span>||LA23_NHB05_P||
|-
| D25E25||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_N||
|-
| D26E26||IO_L5P_T0_AD9P_35DGND||LA26_PGND||
|-
| D27E27||IO_L5N_T0_AD9N_35<span style="color:#ff0000">not connected</span>||LA26_NHB09_P||
|-
| D28E28||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_N||
|-
| D29E29||JTAG_TCKDGND||TCKGND||
|-
| D30E30||JTAG_TDI<span style="color:#ff0000">not connected</span>||TDIHB13_P||
|-
| D31E31||FMC_TDO_ZYNQ_TDI<span style="color:#ff0000">not connected</span>||TDOHB13_N||
|-
| D32E32||FMC_3P3VAUXDGND||3P3VAUXGND||
|-
| D33E33||JTAG_TMS<span style="color:#ff0000">not connected</span>||TMSHB19_P||
|-
| D34E34||JTAG_TRSTn<span style="color:#ff0000">not connected</span>||TRST_LHB19_N||
|-
| D35E35||GA0DGND||GA1GND||
|-
| D36E36||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHB21_P||
|-
| D37E37||DGND<span style="color:#ff0000">not connected</span>||GNDHB21_N||
|-
| D38E38||FMC_3P3VDGND||3P3VGND||
|-
| D39E39||DGNDFMC_VADJ||GNDVADJ||
|-
| D40E40||FMC_3P3VDGND||3P3VGND||
|}
==== HPC Row E F ====
{| class="wikitable"
!Notes
|-
| E1F1||DGNDIO_0_VRN_35||GNDPG_M2C||
|-
| E2F2||IO_L14P_T2_AD4P_SRCC_35DGND||HA01_P_CCGND||
|-
| E3F3||IO_L14N_T2_AD4N_SRCC_35DGND||HA01_N_CCGND||
|-
| E4F4||DGNDIO_L13P_T2_MRCC_35||GNDHA00_P_CC||
|-
| E5F5||DGNDIO_L13N_T2_MRCC_35||GNDHA00_N_CC||
|-
| E6F6||IO_L20P_T3_AD6P_35DGND||HA05_PGND||
|-
| E7F7||IO_L20N_T3_AD6N_35IO_L19P_T3_35||HA05_NHA04_P||
|-
| E8F8||DGNDIO_L19N_T3_VREF_35||GNDHA04_N||
|-
| E9F9||IO_L24P_T3_AD15P_35DGND||HA09_PGND||
|-
| E10F10||IO_L24N_T3_AD15N_35IO_L23P_T3_35||HA09_NHA08_P||
|-
| E11F11||DGNDIO_L23N_T3_35||GNDHA08_N||
|-
| E12F12||<span style="color:#ff0000">not connected</span>DGND||HA13_PGND||
|-
| E13F13||<span style="color:#ff0000">not connected</span>||HA13_NHA12_P||
|-
| E14F14||DGND<span style="color:#ff0000">not connected</span>||GNDHA12_N||
|-
| E15F15||<span style="color:#ff0000">not connected</span>DGND||HA16_PGND||
|-
| E16F16||<span style="color:#ff0000">not connected</span>||HA16_NHA15_P||
|-
| E17F17||DGND<span style="color:#ff0000">not connected</span>||GNDHA15_N||
|-
| E18F18||<span style="color:#ff0000">not connected</span>DGND||HA20_PGND||
|-
| E19F19||<span style="color:#ff0000">not connected</span>||HA20_NHA19_P||
|-
| E20F20||DGND<span style="color:#ff0000">not connected</span>||GNDHA19_N||
|-
| E21F21||<span style="color:#ff0000">not connected</span>DGND||HB03_PGND||
|-
| E22F22||<span style="color:#ff0000">not connected</span>||HB03_NHB02_P||
|-
| E23F23||DGND<span style="color:#ff0000">not connected</span>||GNDHB02_N||
|-
| E24F24||<span style="color:#ff0000">not connected</span>DGND||HB05_PGND||
|-
| E25F25||<span style="color:#ff0000">not connected</span>||HB05_NHB04_P||
|-
| E26F26||DGND<span style="color:#ff0000">not connected</span>||GNDHB04_N||
|-
| E27F27||<span style="color:#ff0000">not connected</span>DGND||HB09_PGND||
|-
| E28F28||<span style="color:#ff0000">not connected</span>||HB09_NHB08_P||
|-
| E29F29||DGND<span style="color:#ff0000">not connected</span>||GNDHB08_N||
|-
| E30F30||<span style="color:#ff0000">not connected</span>DGND||HB13_PGND||
|-
| E31F31||<span style="color:#ff0000">not connected</span>||HB13_NHB12_P||
|-
| E32F32||DGND<span style="color:#ff0000">not connected</span>||GNDHB12_N||
|-
| E33F33||<span style="color:#ff0000">not connected</span>DGND||HB19_PGND||
|-
| E34F34||<span style="color:#ff0000">not connected</span>||HB19_NHB16_P||
|-
| E35F35||DGND<span style="color:#ff0000">not connected</span>||GNDHB16_N||
|-
| E36F36||<span style="color:#ff0000">not connected</span>DGND||HB21_PGND||
|-
| E37F37||<span style="color:#ff0000">not connected</span>||HB21_NHB20_P||
|-
| E38F38||DGND<span style="color:#ff0000">not connected</span>||GNDHB20_N||
|-
| E39F39||FMC_VADJDGND||VADJGND||
|-
| E40F40||DGNDFMC_VADJ||GNDVADJ||
|}
==== HPC LPC Row F G ====
{| class="wikitable"
!Notes
|-
| F1G1||IO_0_VRN_35DGND||PG_M2CGND||
|-
| F2G2||DGNDIO_L11P_T1_SRCC_34||GNDCLK0_C2M_P||
|-
| F3G3||DGNDIO_L11N_T1_SRCC_34||GNDCLK0_C2M_N||
|-
| F4G4||IO_L13P_T2_MRCC_35DGND||HA00_P_CCGND||
|-
| F5G5||IO_L13N_T2_MRCC_35DGND||HA00_N_CCGND||
|-
| F6G6||DGNDIO_L13P_T1_MRCC_34||GNDLA00_P_CC||
|-
| F7G7||IO_L19P_T3_35IO_L13N_T1_MRCC_34||HA04_PLA00_N_CC||
|-
| F8G8||IO_L19N_T3_VREF_35DGND||HA04_NGND||
|-
| F9G9||DGNDIO_L4P_T0_34||GNDLA03_P||
|-
| F10G10||IO_L23P_T3_35IO_L4N_T0_34||HA08_PLA03_N||
|-
| F11G11||IO_L23N_T3_35DGND||HA08_NGND||
|-
| F12G12||DGNDIO_L3P_T0_DQS_PUDC_B_34||GNDLA08_P||
|-
| F13G13||<span style="color:#ff0000">not connected</span>IO_L3N_T0_DQS_34||HA12_PLA08_N||
|-
| F14G14||<span style="color:#ff0000">not connected</span>DGND||HA12_NGND||
|-
| F15G15||DGNDIO_L22P_T3_34||GNDLA12_P||
|-
| F16G16||<span style="color:#ff0000">not connected</span>IO_L22N_T3_34||HA15_PLA12_N||
|-
| F17G17||<span style="color:#ff0000">not connected</span>DGND||HA15_NGND||
|-
| F18G18||DGNDIO_L19P_T3_34||GNDLA16_P||
|-
| F19G19||<span style="color:#ff0000">not connected</span>IO_L19N_T3_VREF_34||HA19_PLA16_N||
|-
| F20G20||<span style="color:#ff0000">not connected</span>DGND||HA19_NGND||
|-
| F21G21||DGNDIO_L17P_T2_34||GNDLA20_P||
|-
| F22G22||<span style="color:#ff0000">not connected</span>IO_L17N_T2_34||HB02_PLA20_N||
|-
| F23G23||<span style="color:#ff0000">not connected</span>DGND||HB02_NGND||
|-
| F24G24||DGNDIO_L1P_T0_AD0P_35||GNDLA22_P||
|-
| F25G25||<span style="color:#ff0000">not connected</span>IO_L1N_T0_AD0N_35||HB04_PLA22_N||
|-
| F26G26||<span style="color:#ff0000">not connected</span>DGND||HB04_NGND||
|-
| F27G27||DGNDIO_L4P_T0_35||GNDLA25_P||
|-
| F28G28||<span style="color:#ff0000">not connected</span>IO_L4N_T0_35||HB08_PLA25_N||
|-
| F29G29||<span style="color:#ff0000">not connected</span>DGND||HB08_NGND||
|-
| F30G30||DGNDIO_L8P_T1_AD10P_35||GNDLA29_P||
|-
| F31G31||<span style="color:#ff0000">not connected</span>IO_L8N_T1_AD10N_35||HB12_PLA29_N||
|-
| F32G32||<span style="color:#ff0000">not connected</span>DGND||HB12_NGND||
|-
| F33G33||DGNDIO_L10P_T1_AD11P_35||GNDLA31_P||
|-
| F34G34||<span style="color:#ff0000">not connected</span>IO_L10N_T1_AD11N_35||HB16_PLA31_N||
|-
| F35G35||<span style="color:#ff0000">not connected</span>DGND||HB16_NGND||
|-
| F36G36||DGNDIO_L16P_T2_35||GNDLA33_P||
|-
| F37G37||<span style="color:#ff0000">not connected</span>IO_L16N_T2_35||HB20_PLA33_N||
|-
| F38G38||<span style="color:#ff0000">not connected</span>DGND||HB20_NGND||
|-
| F39G39||DGNDFMC_VADJ||GNDVADJ||
|-
| F40G40||FMC_VADJDGND||VADJGND||
|}
==== LPC Row G H ====
{| class="wikitable"
!Notes
|-
| G1H1||DGNDFMC_VREF_A_M2C||GNDVREF_A_M2C||
|-
| G2H2||IO_L11P_T1_SRCC_34FMC_PRSNT_M2C_L||CLK0_C2M_PPRSNT_M2C_L||
|-
| G3H3||IO_L11N_T1_SRCC_34DGND||CLK0_C2M_NGND||
|-
| G4H4||DGNDIO_L12P_T1_MRCC_34||GNDCLK0_M2C_P||
|-
| G5H5||DGNDIO_L12N_T1_MRCC_34||GNDCLK0_M2C_N||
|-
| G6H6||IO_L13P_T1_MRCC_34DGND||LA00_P_CCGND||
|-
| G7H7||IO_L13N_T1_MRCC_34IO_L7P_T1_34||LA00_N_CCLA02_P||
|-
| G8H8||DGNDIO_L7N_T1_34||GNDLA02_N||
|-
| G9H9||IO_L4P_T0_34DGND||LA03_PGND||
|-
| G10H10||IO_L4N_T0_34IO_L5P_T0_34||LA03_NLA04_P||
|-
| G11H11||DGNDIO_L5N_T0_34||GNDLA04_N||
|-
| G12H12||IO_L3P_T0_DQS_PUDC_B_34DGND||LA08_PGND||
|-
| G13H13||IO_L3N_T0_DQS_34IO_L8P_T1_34||LA08_NLA07_P||
|-
| G14H14||DGNDIO_L8N_T1_34||GNDLA07_N||
|-
| G15H15||IO_L22P_T3_34DGND||LA12_PGND||
|-
| G16H16||IO_L22N_T3_34IO_L21P_T3_DQS_34||LA12_NLA11_P||
|-
| G17H17||DGNDIO_L21N_T3_DQS_34||GNDLA11_N||
|-
| G18H18||IO_L19P_T3_34DGND||LA16_PGND||
|-
| G19H19||IO_L19N_T3_VREF_34IO_L18P_T2_34||LA16_NLA15_P||
|-
| G20H20||DGNDIO_L18N_T2_34||GNDLA15_N||
|-
| G21H21||IO_L17P_T2_34DGND||LA20_PGND||
|-
| G22H22||IO_L17N_T2_34IO_L24P_T3_34||LA20_NLA19_P||
|-
| G23H23||DGNDIO_L24N_T3_34||GNDLA19_N||
|-
| G24H24||IO_L1P_T0_AD0P_35DGND||LA22_PGND||
|-
| G25H25||IO_L1N_T0_AD0N_35IO_L10P_T1_34||LA22_NLA21_P||
|-
| G26H26||DGNDIO_L10N_T1_34||GNDLA21_N||
|-
| G27H27||IO_L4P_T0_35DGND||LA25_PGND||
|-
| G28H28||IO_L4N_T0_35IO_L3P_T0_DQS_AD1P_35||LA25_NLA24_P||
|-
| G29H29||DGNDIO_L3N_T0_DQS_AD1N_35||GNDLA24_N||
|-
| G30H30||IO_L8P_T1_AD10P_35DGND||LA29_PGND||
|-
| G31H31||IO_L8N_T1_AD10N_35IO_L7P_T1_AD2P_35||LA29_NLA28_P||
|-
| G32H32||DGNDIO_L7N_T1_AD2N_35||GNDLA28_N||
|-
| G33H33||IO_L10P_T1_AD11P_35DGND||LA31_PGND||
|-
| G34H34||IO_L10N_T1_AD11N_35IO_L9P_T1_DQS_AD3P_35||LA31_NLA30_P||
|-
| G35H35||DGNDIO_L9N_T1_DQS_AD3N_35||GNDLA30_N||
|-
| G36H36||IO_L16P_T2_35DGND||LA33_PGND||
|-
| G37H37||IO_L16N_T2_35IO_L15P_T2_DQS_AD12P_35||LA33_NLA32_P||
|-
| G38H38||DGNDIO_L15N_T2_DQS_AD12N_35||GNDLA32_N||
|-
| G39H39||FMC_VADJDGND||VADJGND||
|-
| G40H40||DGNDFMC_VADJ||GNDVADJ||
|}
==== LPC HPC Row H J ====
{| class="wikitable"
!Notes
|-
| H1J1||FMC_VREF_A_M2CDGND||VREF_A_M2CGND||
|-
| H2J2||FMC_PRSNT_M2C_LIO_L11P_T1_SRCC_35||PRSNT_M2C_LCLK1_C2M_P||
|-
| H3J3||DGNDIO_L11N_T1_SRCC_35||GNDCLK1_C2M_N||
|-
| H4J4||IO_L12P_T1_MRCC_34DGND||CLK0_M2C_PGND||
|-
| H5J5||IO_L12N_T1_MRCC_34DGND||CLK0_M2C_NGND||
|-
| H6J6||DGNDIO_L18P_T2_AD13P_35||GNDHA03_P||
|-
| H7J7||IO_L7P_T1_34IO_L18N_T2_AD13N_35||LA02_PHA03_N||
|-
| H8J8||IO_L7N_T1_34DGND||LA02_NGND||
|-
| H9J9||DGNDIO_L22P_T3_AD7P_35||GNDHA07_P||
|-
| H10J10||IO_L5P_T0_34IO_L22N_T3_AD7N_35||LA04_PHA07_N||
|-
| H11J11||IO_L5N_T0_34DGND||LA04_NGND||
|-
| H12J12||DGND<span style="color:#ff0000">not connected</span>||GNDHA11_P||
|-
| H13J13||IO_L8P_T1_34<span style="color:#ff0000">not connected</span>||LA07_PHA11_N||
|-
| H14J14||IO_L8N_T1_34DGND||LA07_NGND||
|-
| H15J15||DGND<span style="color:#ff0000">not connected</span>||GNDHA14_P||
|-
| H16J16||IO_L21P_T3_DQS_34<span style="color:#ff0000">not connected</span>||LA11_PHA14_N||
|-
| H17J17||IO_L21N_T3_DQS_34DGND||LA11_NGND||
|-
| H18J18||DGND<span style="color:#ff0000">not connected</span>||GNDHA18_P||
|-
| H19J19||IO_L18P_T2_34<span style="color:#ff0000">not connected</span>||LA15_PHA18_N||
|-
| H20J20||IO_L18N_T2_34DGND||LA15_NGND||
|-
| H21J21||DGND<span style="color:#ff0000">not connected</span>||GNDHA22_P||
|-
| H22J22||IO_L24P_T3_34<span style="color:#ff0000">not connected</span>||LA19_PHA22_N||
|-
| H23J23||IO_L24N_T3_34DGND||LA19_NGND||
|-
| H24J24||DGND<span style="color:#ff0000">not connected</span>||GNDHB01_P||
|-
| H25J25||IO_L10P_T1_34<span style="color:#ff0000">not connected</span>||LA21_PHB01_N||
|-
| H26J26||IO_L10N_T1_34DGND||LA21_NGND||
|-
| H27J27||DGND<span style="color:#ff0000">not connected</span>||GNDHB07_P||
|-
| H28J28||IO_L3P_T0_DQS_AD1P_35<span style="color:#ff0000">not connected</span>||LA24_PHB07_N||
|-
| H29J29||IO_L3N_T0_DQS_AD1N_35DGND||LA24_NGND||
|-
| H30J30||DGND<span style="color:#ff0000">not connected</span>||GNDHB11_P||
|-
| H31J31||IO_L7P_T1_AD2P_35<span style="color:#ff0000">not connected</span>||LA28_PHB11_N||
|-
| H32J32||IO_L7N_T1_AD2N_35DGND||LA28_NGND||
|-
| H33J33||DGND<span style="color:#ff0000">not connected</span>||GNDHB15_P||
|-
| H34J34||IO_L9P_T1_DQS_AD3P_35<span style="color:#ff0000">not connected</span>||LA30_PHB15_N||
|-
| H35J35||IO_L9N_T1_DQS_AD3N_35DGND||LA30_NGND||
|-
| H36J36||DGND<span style="color:#ff0000">not connected</span>||GNDHB18_P||
|-
| H37J37||IO_L15P_T2_DQS_AD12P_35<span style="color:#ff0000">not connected</span>||LA32_PHB18_N||
|-
| H38J38||IO_L15N_T2_DQS_AD12N_35DGND||LA32_NGND||
|-
| H39J39||DGND<span style="color:#ff0000">not connected</span>||GNDVIO_B_M2C||
|-
| H40J40||FMC_VADJDGND||VADJGND||
|}
==== HPC Row J K ====
{| class="wikitable"
!Notes
|-
| J1K1||DGND<span style="color:#ff0000">not connected</span>||GNDVREF_B_M2C||
|-
| J2K2||IO_L11P_T1_SRCC_35DGND||CLK1_C2M_PGND||
|-
| J3K3||IO_L11N_T1_SRCC_35DGND||CLK1_C2M_NGND||
|-
| J4K4||DGNDIO_L12P_T1_MRCC_35||GNDCLK1_M2C_P||
|-
| J5K5||DGNDIO_L12N_T1_MRCC_35||GNDCLK1_M2C_N||
|-
| J6K6||IO_L18P_T2_AD13P_35DGND||HA03_PGND||
|-
| J7K7||IO_L18N_T2_AD13N_35IO_L17P_T2_AD5P_35||HA03_NHA02_P||
|-
| J8K8||DGNDIO_L17N_T2_AD5N_35||GNDHA02_N||
|-
| J9K9||IO_L22P_T3_AD7P_35DGND||HA07_PGND||
|-
| J10K10||IO_L22N_T3_AD7N_35IO_L21P_T3_DQS_AD14P_35||HA07_NHA06_P||
|-
| J11K11||DGNDIO_L21N_T3_DQS_AD14N_35||GNDHA06_N||
|-
| J12K12||<span style="color:#ff0000">not connected</span>DGND||HA11_PGND||
|-
| J13K13||<span style="color:#ff0000">not connected</span>IO_25_VRP_35||HA11_NHA10_P||
|-
| J14K14||DGND<span style="color:#ff0000">not connected</span>||GNDHA10_N||
|-
| J15K15||<span style="color:#ff0000">not connected</span>DGND||HA14_PGND||
|-
| J16K16||<span style="color:#ff0000">not connected</span>||HA14_NHA17_P_CC||
|-
| J17K17||DGND<span style="color:#ff0000">not connected</span>||GNDHA17_N_CC||
|-
| J18K18||<span style="color:#ff0000">not connected</span>DGND||HA18_PGND||
|-
| J19K19||<span style="color:#ff0000">not connected</span>||HA18_NHA21_P||
|-
| J20K20||DGND<span style="color:#ff0000">not connected</span>||GNDHA21_N||
|-
| J21K21||<span style="color:#ff0000">not connected</span>DGND||HA22_PGND||
|-
| J22K22||<span style="color:#ff0000">not connected</span>||HA22_NHA23_P||
|-
| J23K23||DGND<span style="color:#ff0000">not connected</span>||GNDHA23_N||
|-
| J24K24||<span style="color:#ff0000">not connected</span>DGND||HB01_PGND||
|-
| J25K25||<span style="color:#ff0000">not connected</span>||HB01_NHB00_P_CC||
|-
| J26K26||DGND<span style="color:#ff0000">not connected</span>||GNDHB00_N_CC||
|-
| J27K27||<span style="color:#ff0000">not connected</span>DGND||HB07_PGND||
|-
| J28K28||<span style="color:#ff0000">not connected</span>||HB07_NHB06_P_CC||
|-
| J29K29||DGND<span style="color:#ff0000">not connected</span>||GNDHB06_N_CC||
|-
| J30K30||<span style="color:#ff0000">not connected</span>DGND||HB11_PGND||
|-
| J31K31||<span style="color:#ff0000">not connected</span>||HB11_NHB10_P||
|-
| J32K32||DGND<span style="color:#ff0000">not connected</span>||GNDHB10_N||
|-
| J33K33||<span style="color:#ff0000">not connected</span>DGND||HB15_PGND||
|-
| J34K34||<span style="color:#ff0000">not connected</span>||HB15_NHB14_P||
|-
| J35K35||DGND<span style="color:#ff0000">not connected</span>||GNDHB14_N||
|-
| J36K36||<span style="color:#ff0000">not connected</span>DGND||HB18_PGND||
|-
| J37K37||<span style="color:#ff0000">not connected</span>||HB18_NHB17_P_CC||
|-
| J38K38||DGND<span style="color:#ff0000">not connected</span>||GNDHB17_N_CC||
|-
| J39K39||<span style="color:#ff0000">not connected</span>DGND||VIO_B_M2CGND||
|-
| J40K40||DGND<span style="color:#ff0000">not connected</span>||GNDVIO_B_M2C||
|}
===Pin strip connectors = HPC Row K == ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
| K11, 4, 9, 12 ||<span style="color:#ff0000">not connected</span>DGND ||VREF_B_M2CGround ||-
|-
| K22 ||DGNDSPI0_CS0n ||GND- ||-
|-
| K33 ||DGNDZYNQ_SPI0_SCLK/NAND_IO1 ||GND- ||-
|-
| K45 ||IO_L12P_T1_MRCC_35ZYNQ_SPI0_DQ0/NAND_ALE ||CLK1_M2C_P- ||-
|-
| K56 ||IO_L12N_T1_MRCC_35NAND_CS0/SPI0_CS1 ||CLK1_M2C_N- ||-
|-
| K67 ||DGNDZYNQ_SPI0_DQ2/NAND_IO2 ||GND- ||-
|-
| K78 ||IO_L17P_T2_AD5P_35ZYNQ_SPI0_DQ1/NAND_WE ||HA02_P- ||-
|-
| K810 ||IO_L17N_T2_AD5N_35ZYNQ_SPI0_DQ3/NAND_IO0 ||HA02_N- ||-
|-
| K911 ||DGNDZYNQ_NAND_RD_B ||GND- ||-
|-
| K10||IO_L21P_T3_DQS_AD14P_35||HA06_P|} ==== Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
|-
| K11||IO_L21N_T3_DQS_AD14N_35||HA06_N||!Pin# !Pin name!Function!Notes
|-
| K121 ||DGNDMON_VCCPLL ||GND- ||-
|-
| K132 ||IO_25_VRP_35MON_3.3V ||HA10_P- ||-
|-
| K143 ||<span style="color:#ff0000">not connected</span>MON_XADC_VCC ||HA10_N- ||-
|-
| K154 ||DGNDMON_1V2_ETH ||GND- ||-
|-
| K165 ||<span style="color:#ff0000">not connected</span>MON_FPGA_VDDIO_BANK35 ||HA17_P_CC- ||-
|-
| K176 ||<span style="color:#ff0000">not connected</span>MON_VDDQ_1V5 ||HA17_N_CC- ||-
|-
| K187 ||DGNDMON_FPGA_VDDIO_BANK34 ||GND- ||-
|-
| K198 ||<span style="color:#ff0000">not connected</span>MON_1.8V ||HA21_P- ||-
|-
| K209 ||<span style="color:#ff0000">not connected</span>MON_FPGA_VDDIO_BANK13 ||HA21_N- ||-
|-
| K2110 ||DGNDMON_1.0V ||GND- ||-
|-
| K2211 ||<span style="color:#ff0000">not connected</span>MON_1.8V_IO ||HA23_P- ||-
|-
| K2312 ||<span style="color:#ff0000">not connected</span>MON_MGTAVCC ||HA23_N- ||-
|-
| K2413 ||DGNDMON_MGTAVTT ||GND- ||-
|-
| K2514 ||<span style="color:#ff0000">not connected</span>MON_MGTAVCCAUX ||HB00_P_CC- ||-
|-
| K2615, 16 ||<span style="color:#ff0000">not connected</span>DGND ||HB00_N_CCGround ||-
|-
| K27||DGND||GND|}  ==== Ethernet GPIO - JP18 ====JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
|-
| K28||<span style="color:!Pin#ff0000">not connected</span>||HB06_P_CC||!Pin name!Function!Notes
|-
| K291, 2, 5,<br>6, 16||<span style="color:#ff0000">not connected</span>DGND ||HB06_N_CCGround ||-
|-
| K303 ||DGNDCLK125_NDO||GND- ||-
|-
| K314 ||<span style="color:#ff0000">not connected</span>ETH1_CLK125_NDO ||HB10_P- ||-|-|7 || ETH_MDC || - || -
|-
| K328 ||<span style="color:#ff0000">not connected</span>ETH1_MDC ||HB10_N- ||-
|-
| K339 ||DGNDETH_MDIO ||GND- ||-
|-
| K3410 ||<span style="color:#ff0000">not connected</span>ETH1_MDIO ||HB14_P- ||-
|-
| K3511 ||<span style="color:#ff0000">not connected</span>ETH_INTn ||HB14_N- ||-
|-
| K3612 ||DGNDETH1_INTn ||GND- ||-
|-
| K3713 ||<span style="color:#ff0000">not connected</span>PS_MIO51_501 ||HB17_P_CC- ||-
|-
| K3814 ||<span style="color:#ff0000">not connected</span>ETH1_RESETn ||HB17_N_CC- ||-
|-
| K3915 ||DGNDPS_MIO50_501 ||GND- ||-
|-
| K40||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
=== Pin strip connectors ===
==== SPI,NAND - JP13 JP19 ==== JP13 JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 4, 911, 12 || DGND || Ground || -
|-
|2 || SPI0_CS0n NAND_BUSY|| - || -
|-
|3 || ZYNQ_SPI0_SCLK/NAND_IO1 ZYNQ_NAND_CLE || - || -|-|4 || NAND_IO3 || - || -
|-
|5 || ZYNQ_SPI0_DQ0/NAND_ALE NAND_IO4 || - || -
|-
|6 || NAND_CS0/SPI0_CS1 NAND_IO5 || - || -
|-
|7 || ZYNQ_SPI0_DQ2/NAND_IO2 NAND_IO6 || - || -
|-
|8 || ZYNQ_SPI0_DQ1/NAND_WE NAND_IO7 || - || -
|-
|10 9 || ZYNQ_SPI0_DQ3/NAND_IO0 CONN_SPI_RSTn || - || -
|-
|11 10 || ZYNQ_NAND_RD_B MEM_WPn || - || -
|-
|}
==== Voltage Monitor FPGA, WatchDog, RTC, RST - JP15 JP22 ==== JP15 JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 || MON_VCCPLL FPGA_INIT_B|| - || -
|-
|2 || MON_3.3V RTC_32KHZ || - || -
|-
|3 || MON_XADC_VCC FPGA_PROGRAM_B|| - || -
|-
|4 || MON_1V2_ETH RTC_RST || - || -
|-
|5 || MON_FPGA_VDDIO_BANK35 FPGA_DONE || - || -
|-
|6 || MON_VDDQ_1V5 RTC_INT/SQW || - || -
|-
|7 , 8 || MON_FPGA_VDDIO_BANK34 DGND || - Ground || -
|-
|8 9 || MON_1.8V WD_SET0 || - || -
|-
|9 10 || MON_FPGA_VDDIO_BANK13 SYS_RSTn || - || -
|-
|10 11 || MON_1.0V WD_SET1 || - || -
|-
|11 12 || MON_1.8V_IO PORSTn || - || -
|-
|12 13 || MON_MGTAVCC WD_SET2 || - || -
|-
|13 14 || MON_MGTAVTT MRSTn || - || -
|-
|14 15 || MON_MGTAVCCAUX PS_MIO15_500 || - || -
|-
|15, 16 || DGND CB_PWR_GOOD || Ground - || -
|-
|}
 ==== Ethernet GPIO AUX PINs - JP18 JP29 ====JP18 JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2, 5,<br>6, 16|| DGND EVB_1.8V || Ground - || -
|-
|3 2 || CLK125_NDO3.3V || - || -
|-
|3 || PS_I2C0_DAT|| - || -|-|4 || ETH1_CLK125_NDO I2C0_SDA || - || -
|-
|7 5 || ETH_MDC PS_I2C0_CK || - || -
|-
|8 6 || ETH1_MDC I2C0_SCL || - || -
|-
|9 7, 8,<br>13 || ETH_MDIO DGND || - Ground || -
|-
|10 9 || ETH1_MDIO EXT_VMON2_V1 || - || -Mount option
|-
|11 10, 16 ||ETH_INTn XADC_AGND || - Analog Ground || -
|-
|12 11 || ETH1_INTn EXT_VMON2_V2 || - || -Mount option
|-
|13 12 || PS_MIO51_501 XADC_VN_R || - || -
|-
|14 || ETH1_RESETn XADC_VP_R || - || -
|-
|15 || PS_MIO50_501 INA_ALERT || - || -
|-
|}
Please note that:
==== SPI,NAND - JP19 ====JP19 * Three devices are connected to I2C0 bus (this is a 12-pin 6x2x2level shifted from 1.54 pitch vertical header8V to 3. The following table reports 3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the pinout of the connectoruser to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor:this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ==== JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors: JP30:{| class="wikitable"
|-
!Pin#
!Notes
|-
|1, 11, 122 || DGND FPGA_BANK35_AD0N || Ground AD0_N || Mount option| -|3 || FPGA_BANK35_AD1P || AD1_P || Mount option|-|4 || FPGA_BANK35_AD0P || AD0_P || Mount option
|-
|2 5 || NAND_BUSYFPGA_BANK35_AD1N || - AD1_N || -Mount option
|-
|3 8 || ZYNQ_NAND_CLE FPGA_BANK35_AD2P || - AD2_P || -Mount option
|-
|4 9 || NAND_IO3 FPGA_BANK35_AD3P || - AD3_P || -Mount option
|-
|5 10 || NAND_IO4 FPGA_BANK35_AD2N || - AD2_N || -Mount option
|-
|6 11 || NAND_IO5 FPGA_BANK35_AD3N || - AD3_N || -Mount option
|-
|7 14 || NAND_IO6 FPGA_BANK35_AD4P || - AD4_P || -Mount option
|-
|8 15 || NAND_IO7 FPGA_BANK35_AD5P || - AD5_P || -Mount option
|-
|9 16 || CONN_SPI_RSTn FPGA_BANK35_AD4N || - AD4_N || -Mount option
|-
|10 1, 6, 7,<br>12, 13 || MEM_WPn DGND || - || -
|-
|}
==== FPGA, WatchDog, RTC, RST - JP22 ====JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorJP31: 
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_INIT_BFPGA_BANK35_AD5N || - AD5_N || -Mount option
|-
|2 4 || RTC_32KHZ FPGA_BANK35_AD6P || - AD6_P || -Mount option
|-
|3 5 || FPGA_PROGRAM_BFPGA_BANK35_AD7P || - AD7_P || -Mount option
|-
|4 6 || RTC_RST FPGA_BANK35_AD6N || - AD6_N || -Mount option
|-
|5 7 || FPGA_DONE FPGA_BANK35_AD7N || - AD7_N || -Mount option
|-
|6 10 || RTC_INT/SQW FPGA_BANK35_AD8P || - AD8_P || -Mount option
|-
|7, 8 11 || DGND FPGA_BANK35_AD9P || Ground AD9_P || -Mount option
|-
|9 12 || WD_SET0 FPGA_BANK35_AD8N || - AD8_N || -Mount option
|-
|10 13 || SYS_RSTn FPGA_BANK35_AD9N || - AD9_N || -Mount option
|-
|11 16 || WD_SET1 FPGA_BANK35_AD10P || - AD10_P || -Mount option
|-
|12 2, 3, 8,<br>9, 14, 15 || PORSTn DGND || - || -
|-
|13 || WD_SET2 || - || -|-|14 || MRSTn || - || -|-|15 || PS_MIO15_500 || - || -|-|16 || CB_PWR_GOOD || - || -|-|} ==== AUX PINs - JP29 ====JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorJP32: {| class="wikitable"
|-
!Pin#
!Notes
|-
|1 || EVB_1.8V FPGA_BANK35_AD11P || - AD11_P || -Mount option
|-
|2 || 3.3V FPGA_BANK35_AD10N || - AD10_N || -Mount option
|-
|3 || PS_I2C0_DATFPGA_BANK35_AD11N || - AD11_N || -Mount option
|-
|4 6 || I2C0_SDA FPGA_BANK35_AD12P || - AD12_P || -Mount option
|-
|5 7 || PS_I2C0_CK FPGA_BANK35_AD13P || - AD13_P || -Mount option
|-
|6 8 || I2C0_SCL FPGA_BANK35_AD12N || - AD12_N || -Mount option
|-
|7, 8,<br>13 9 || DGND FPGA_BANK35_AD13N || Ground AD13_N || -Mount option
|-
|9 12 || EXT_VMON2_V1 FPGA_BANK35_AD14P || - AD14_P || Mount option
|-
|10, 16 13 || XADC_AGND FPGA_BANK35_AD15P || Analog Ground AD15_P || -Mount option
|-
|11 14 || EXT_VMON2_V2 FPGA_BANK35_AD14N || - AD14_N || Mount option
|-
|12 15 || XADC_VN_R FPGA_BANK35_AD15N || - AD15_N || -Mount option
|-
|14 4, 5, 10,<br>11, 16 || XADC_VP_R || - || -|-|15 || INA_ALERT DGND || - || -
|-
|}
Please note that:=== Digilent Pmod™ Compatible headers ===
Please note that: * Three devices are connected Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to I2C0 bus (this is level shifted from 1.8V quickly connect several pre-built I/O modules to 3.3V)PL:** Silicon Labs Si571 programmable clock generatorhttp: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA/www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** resistive touch screen controller for LCD screenhttp://www.maximintegrated.com/products/evkits/fpga-modules/** consumption monitor: this is connected Signals used to shunt resistor put in series on Bora power rail, allowing implement LVDS LCD interface can alternatively routed to measure SoM consumptionDigilent Pmod™ Compatible compatible connector
==== ADC Digilent Pmod™ Compatible - JP30, JP31, JP32 JP17 ====
JP30, JP31, JP32 are 16JP17 is a 12-pin 8x2x26x2x2.54 pitch vertical header. The following tables table reports the pinout of the connectorsconnector:
JP30:
{| class="wikitable"
|-
!Notes
|-
|2 1 || FPGA_BANK35_AD0N PMOD_A0 || AD0_N || Mount option-
|-
|3 2 || FPGA_BANK35_AD1P PMOD_A4 || AD1_P || Mount option-
|-
|4 3 || FPGA_BANK35_AD0P PMOD_A1 || AD0_P || Mount option-
|-
|5 4 || FPGA_BANK35_AD1N PMOD_A5 || AD1_N || Mount option-
|-
|8 5 || FPGA_BANK35_AD2P PMOD_A2 || AD2_P || Mount option-
|-
|9 6 || FPGA_BANK35_AD3P PMOD_A6 || AD3_P || Mount option-
|-
|10 7 || FPGA_BANK35_AD2N PMOD_A3 || AD2_N || Mount option-
|-
|11 8 || FPGA_BANK35_AD3N PMOD_A7 || AD3_N || Mount option-
|-
|14 9, 10 || FPGA_BANK35_AD4P DGND || AD4_P Ground || Mount option-
|-
|15 || FPGA_BANK35_AD5P || AD5_P || Mount option|-|16 || FPGA_BANK35_AD4N || AD4_N || Mount option|-|1, 6, 711,<br>12, 13 || DGND 3.3V || - || -
|-
|}
JP31==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD5N PMOD_B0 || AD5_N - || Mount option-
|-
|4 2 || FPGA_BANK35_AD6P PMOD_B4 || AD6_P - || Mount option-
|-
|5 3 || FPGA_BANK35_AD7P PMOD_B1 || AD7_P - || Mount option-
|-
|6 4 || FPGA_BANK35_AD6N PMOD_B5 || AD6_N - || Mount option-
|-
|5 ||PMOD_B2 || - || -|-|6 ||PMOD_B6 || - || -|-|7 || FPGA_BANK35_AD7N PMOD_B3 || AD7_N - || Mount option-
|-
|10 8 || FPGA_BANK35_AD8P PMOD_B7 || AD8_P - || Mount option-
|-
|11 9, 10 || FPGA_BANK35_AD9P DGND || AD9_P Ground || Mount option-
|-
|11, 12 || FPGA_BANK35_AD8N 3.3V || AD8_N - || Mount option-
|-
|13 }===JP27, JP27 and JP28===These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]]. ==PL's I/O voltage selections==PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:*'''each bank must be powered even if none of its I/Os is used'''*'''voltage selection must be done before powering up the board'''. The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies. {| FPGA_BANK35_AD9N class="wikitable" style="text-align: center;"! rowspan="2" style="text-align: center; font-weight: bold;" |Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | AD9_N Bank #34! colspan="2" style="text-align: center; font-weight: bold;" |Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Mount optionBank #35
|-
|16 style="text-align: center; font-weight: bold;" |Type [1]| FPGA_BANK35_AD10P style="text-align: center; font-weight: bold;" |I/O voltage setting| AD10_P style="text-align: center; font-weight: bold;" |Type [1]| Mount optionstyle="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
|style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1.2, - 3, 8,<br>9, 14, 15 .3V)|style="text-align: center;" | DGND User defined|style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined
|-
| style="text-align: center;" | 7030
(SBG485 package)
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
 
===BoraXEVB voltage selection jumpers===
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
 
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
JP32:Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)
|-
!Pin# style="text-align: center; font-weight: bold;" | Nominal voltage [V]!Pin namestyle="text-align: center; font-weight: bold;" | JP25.1-2!Functionstyle="text-align: center; font-weight: bold;" | JP25.3-4!Notesstyle="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12
|-
| style="text-align: center;" |1 .2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''|style="text-align: center;" | FPGA_BANK35_AD11P '''closed'''|style="text-align: center;" | AD11_P '''closed'''|style="text-align: center;" | Mount optionopen
|-
|2 style="text-align: center;" |1.5| FPGA_BANK35_AD10N style="text-align: center;" |open| AD10_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|3 style="text-align: center;" |1.8| FPGA_BANK35_AD11N style="text-align: center;" |open| AD11_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|6 style="text-align: center;" |2.5| FPGA_BANK35_AD12P style="text-align: center;" |'''closed'''| AD12_P style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|-
|7 style="text-align: center;" |3.3| FPGA_BANK35_AD13P style="text-align: center;" |'''closed'''| AD13_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #35 (HP)
|-
! style="text-align: center; font-weight: bold;" |8 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP27.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD12N JP27.3-4! style="text-align: center; font-weight: bold;" |JP27.5-6! style="text-align: center; font-weight: bold;" | AD12_N JP27.7-8! style="text-align: center; font-weight: bold;" |JP27.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP27.11-12
|-
|9 style="text-align: center;" |1.2| FPGA_BANK35_AD13N style="text-align: center;" |open| AD13_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|12 style="text-align: center;" |1.5| FPGA_BANK35_AD14P style="text-align: center;" |open| AD14_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|13 style="text-align: center;" |1.8| FPGA_BANK35_AD15P style="text-align: center;" |open| AD15_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #34 (HP)
|-
! style="text-align: center; font-weight: bold;" |14 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP28.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD14N JP28.3-4! style="text-align: center; font-weight: bold;" |JP28.5-6! style="text-align: center; font-weight: bold;" | AD14_N JP28.7-8! style="text-align: center; font-weight: bold;" |JP28.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP28.11-12
|-
|15 style="text-align: center;" |1.2| FPGA_BANK35_AD15N style="text-align: center;" |open| AD15_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|4, style="text-align: center;" | 1.5, 10,<br>11, 16 | style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" |open| DGND style="text-align: center;" |'''closed'''| style="text- align: center;" |open| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
=== Digilent Pmod™ Compatible headers =Examples of valid combinations for Zynq 7015-based SOMs===={|class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}
Please note that:
* Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812
** http://www.maximintegrated.com/products/evkits/fpga-modules/
* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector
{|class="wikitable" style="text-align: center;"|+Bank #35 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style= Digilent Pmod™ Compatible "text-align: center; font- JP17 weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style= JP17 is a 12"text-align: center; font-pin 6x2x2weight: bold;" | JP27.54 pitch vertical header. The following table reports the pinout of the connector:9-10 {| class! style="wikitabletext-align: center; font-weight: bold;" | JP27.11-12
|-
!Pin# | style="text-align: center;" | 1.2!Pin name| style="text-align: center;" | open!Function| style="text-align: center;" | open!Notes| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
| style="text-align: center;" |1 .5|style="text-align: center;" |PMOD_A0 open|style="text-align: center;" | '''closed'''|style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|2 style="text-align: center;" |1.8|PMOD_A4 style="text-align: center;" |open| style="text-align: center;" |'''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|3 style="text-align: center;" |2.5|PMOD_A1 style="text-align: center;" |'''closed'''| style="text-align: center;" |open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|-
|4 style="text-align: center;" |3.3|PMOD_A5 style="text-align: center;" |'''closed'''| style="text-align: center;" |'''closed'''| style="text-align: center;" | '''closed'''|style="text-align: center;" | open|5 style="text-align: center;" |open|PMOD_A2 style="text-align: center;" |open | }  {|class="wikitable" style="text-align: center;"| -+Bank #34 (HP)
|-
! style="text-align: center; font-weight: bold;" |6 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP28.1-2! style="text-align: center; font-weight: bold;" |PMOD_A6 JP28.3-4! style="text-align: center; font-weight: bold;" |JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" |JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12
|-
|7 style="text-align: center;" |1.2|PMOD_A3 style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
|-
|8 style="text-align: center;" |1.5|PMOD_A7 style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
|-
|9, 10 style="text-align: center;" |1.8|DGND style="text-align: center;" |open|Ground style="text-align: center;" |open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|-
|11, 12 style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" |'''closed'''|3.3V style="text-align: center;" | open| style="text-align: center;" |open| style="text-align: center;" |open| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
====Advanced information about voltage selection connectors====
===== Bank 13 VDDIO selection connector (JP25) =====
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
==== Digilent Pmod™ Compatible - JP23 ====
JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 2 ||PMOD_B0 LDO_B13_1V6|| - adds +1.6V to VDDIO_BANK13 || -
|-
|2 4 ||PMOD_B4 LDO_B13_800mV|| - adds +800mV to VDDIO_BANK13 || -
|-
|3 6 ||PMOD_B1 LDO_B13_400mV|| - adds +400mV to VDDIO_BANK13 || -
|-
|4 8 ||PMOD_B5 LDO_B13_200mV|| - adds +200mV to VDDIO_BANK13 || -
|-
|5 10 ||PMOD_B2 LDO_B13_100mV|| - adds +100mV to VDDIO_BANK13 || -
|-
|6 12 ||PMOD_B6 LDO_B13_50mV|| - adds +50mV to VDDIO_BANK13 || -
|-
|1, 3, 5, 7 ||PMOD_B3 || - || -|-|8 ||PMOD_B7 || - || -|-|, 9, 10 11 ||DGND ||Ground || -|-|11, 12 ||3.3V || - || -
|-
|}
==Schematics==The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V ==Schematics==* ORCAD: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB-1.dave6.eu/system/files/area1-BELK-riservata/boraxevbdsn.zip|BORAXEVB-1.06.31-BELK-dsn.zip]]* PDF : http[[mirror:bora/hw/wwwBoraXEVB/S-EVBBX0000C0R-1.dave6.eu/system/files/area-riservata/1_color.pdf|BoraXEVB-S-EVBBX0000C0R-1.26.01.pdf]]
==BOM==
* BoraXEVB: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB_S.EVBBX0000C0R.dave1.eu/system/files/area-riservata/boraxevb-BOM_S6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.26.0.CSV_CSV.zip]]
==Layout==
* http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-CS143714_assem_view.davepdf|boraxevb-CS143714_assem_view.eupdf]]==PCB design (Mentor PADS)==* [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb-CS143714_assembly_viewCS143714.zip|CS143714.pdfzip]]
==Mechanical==
* DXF: http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-2D-CS143714.davedxf.eu/system/files/areazip|boraxevb-2D-riservata/boraxevb_2D_CS143714CS143714.dxf.zip]]* IDF (3D): http[[mirror:bora/hw/BoraXEVB/wwwboraxevb-3D-CS143714.davezip|boraxevb-3D-CS143714.euzip]]* STEP (3D): [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb_3D_CS143714boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
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