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BoraXEVB

19,629 bytes added, 13:15, 14 June 2019
→‎Schematics
{{Applies To BoraX}}
{{InfoBoxBottom}}
 
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOM. However, it can host different models of BoraX SOM. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
==Introduction==
Bora Xpress EVB is a carrier board designed to host [[BoraXpress SOM|Bora Xpress system-on-module]].
==Block Diagram==
The following picture shows Bora BORA Xpress EVB block diagram:
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]
===Configurable routing options===
FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.
 
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].
[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
== Features ==
| LCD_BKLT_PWM I/O voltage
| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.
|-
| FMC connector
| For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
|-
|}
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
 
<b>(*)</b> Boot mode from NAND in not supported on actual BSP version
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora BORA Xpress module watchdog.
For more details please refer to [[Watchdog (BORAXpress)|this page]].
| WD_SET2 = '0' || OFF || ON
|}
 
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
=== JTAG ===
=== BANK13 VDDIO selector JTAG port is available as two different mechanical connectors:* 2.00mm- JP25 ===pitch 7x2 header (Xilinx standard)JP25 is a 12* 2.54mm-pin 6x2x2.54 pitch vertical 10x2 header used for the selection - through jumpers - of the bank supply voltages(ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. The following table reports the pinout of * JTAG on BORA Xpress EVB is also connected to the FMC connector:. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ====
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|2 1, 3, 5, 7, 9, 11, 13 || LDO_B13_1V6DGND|| adds +1.6V to VDDIO_BANK13 - || -
|-
|4 2 || LDO_B13_800mV3.3V|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 4 || LDO_B13_400mVJTAG_TMS|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 6 || LDO_B13_200mVJTAG_TCK|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 8 || LDO_B13_100mVJTAG_TDO|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 10 || LDO_B13_50mVJTAG_TDI|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 12 || DGNDN.C.|| - || -|-|14 || JTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|2 1 || LDO_B35_1V63.3V|| adds +1.6V to VDDIO_BANK35 - || -
|-
|4 2 || LDO_B35_800mV3.3V|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 3, 11, 17, 19 || LDO_B35_400mVN.C.|| adds +400mV to VDDIO_BANK35 - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_200mVDGND|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 5 || LDO_B35_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK35 - || -|-|7 || JTAG_TMS|| - || -|-|9 || JTAG_TCK|| - || -
|-
|12 13 || LDO_B35_50mVJTAG_TDO|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 15 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed === UART1 -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator === VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 3|UART_EXT_TX| VADJ_FB (51K1)Transmit line|| selects 1.8V VADJ || -Connected to protection diode array
|-
|8 5|DGND| VADJ_FB (68K)Ground|| selects 1.5V VADJ || -
|-
|10 7, 8|| VADJ_FB (100K)|| selects 1N.C.2V VADJ || -|-N.C.|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -Connected to protection diode array
|-
|}
The jumper configurations are:# Jumper on 1=== USB OTG -2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The DEFAULT configuration is:# Jumper on 5-6 -> supply VADJ with 1.8VJ19 ===
=== JTAG ===J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
JTAG port is available as two different mechanical connectors:
* 2.00mm-pitch 7x2 header (Xilinx standard)
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
 
==== JTAG XILINX - J13 ====
 
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDUSB_OTG_VBUS || - || -
|-
|2 || 3.3VUSBM1 || - || -
|-
|4 3 || JTAG_TMSUSBP1 || - || -
|-
|6 4 || JTAG_TCKOTG_ID || - || -
|-
|8 5 || JTAG_TDOUSB_OTG_DGND || - || -
|-
|10 6, 7, 8, 9 || JTAG_TDIUSB_OTG_SHIELD || - || -
|-
|12 || N.C.|| - || -} |=== MicroSD -J21 ===|14 || JTAG_TRSTn|| - || -|J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-|}level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
==== JTAG ARM - J18 ====
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || 3.3VPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|3, 11, 17, 19 || N.C.PS_SD0_CMD||| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND3.3V||| - || -
|-
|5 || JTAG_TDIPS_SD0_CLK||| - || -
|-
|7 6, 9, 10, 11, 12 || JTAG_TMSDGND||| - || -
|-
|9 7 || JTAG_TCKPS_SD0_DAT0||| - || -
|-
|13 8 || JTAG_TDOPS_SD0_DAT1||| - || -
|-
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
{| class="wikitable"
!Notes
|-
|1, 6, 4, 92 |N.C.|N.C.5V || - || -
|-
|23, 4 |UART_EXT_RX|Receive line3.3V |Connected to protection diode array| - || -
|-
|35, 6,<br> 9, 10,<br>19 |UART_EXT_TX|Transmit lineDGND |Connected to protection diode array| - || -
|-
|57 |DGND|GroundDWM_SD_CMD || - || -
|-
|7, 8|N.C.|N.C.DWM_SD_CLK |Connected to protection diode array| - || -
|-
|}11 ||DWM_SD_DAT0 || - || - === USB OTG |- J19 === J19 is a standard USB MICRO AB connector|12, 14,<br>16, 18,<br>20, 22 ||N. It is connected to the Bora Xpress USB 2C.0 OTG peripheral. The following table reports the pinout of the connector: {| class="wikitable" | - || -
|-
!Pin# !Pin name!Function!Notes|13 ||DWM_SD_DAT1 || - || -
|-
|1 15 ||USB_OTG_VBUS DWM_SD_DAT2 || - || -
|-
|2 17 ||USBM1 DWM_SD_DAT3 || - || -
|-
|3 21 ||USBP1 DWM_UART_RX || - || -
|-
|4 23 ||OTG_ID DWM_UART_CTS || - || -
|-
|5 24 ||USB_OTG_DGND DWM_BT_F5 || - || -
|-
|6, 7, 8, 9 25 ||USB_OTG_SHIELD DWM_UART_TX || - || -
|-
|} === MicroSD 26 ||DWM_BT_F2 || - J21 === J21 is a microSD memory card connector. It is connected to the Bora Xpress SOM through a bidirectional 1.8V/3.3V voltage|| -level translator mounted on the Bora Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector: {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes|27 ||DWM_UART_RTS || - || -
|-
|1 28 ||PS_SD0_DAT2|DWM_WIFI_IRQ || - || -
|-
|2 29 ||PS_SD0_DAT3|DWM_BT_EN || - || -
|-
|3 30 ||PS_SD0_CMDDWM_WIFI_EN ||| - || -|-|4 ||3.3V||| - || -|-|5 ||PS_SD0_CLK||| - || -|-|6, 9, 10, 11, 12 ||DGND||| - || -|-|7 ||PS_SD0_DAT0||| - || -|-|8 ||PS_SD0_DAT1||| - || -|-|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== DWM (DAVE Wifi/BT module) socket CAN - J23 J24 ===J23 J24 is a 5299110-0308 connector type (30 pins, pin 5x2x2.54mm pitch vertical, 0header directly connected to BORA Xpress SoM's transceiver for the CAN interface.50mm picth)This 2. This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVB5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2 6,<br>7, 8,<br>9, 10 ||5V N.C. || - || -
|-
|32, 4 5 ||3.3V CAN_SHIELD || - || -
|-
|5, 6,<br> 9, 10,<br>19 3 ||DGND CAN_L || - || -
|-
|7 4 ||DWM_SD_CMD CAN_H || - || -
|-
|8 ||DWM_SD_CLK || } === Touch screen - J25===J25 is a ZIF 4- pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector: {|| -class="wikitable"
|-
|11 ||DWM_SD_DAT0 || - || -!Pin# !Pin name!Function!Notes
|-
|12, 14,<br>16, 18,<br>20, 22 1 ||N.C. TSC_YP || - || -
|-
|13 2 ||DWM_SD_DAT1 TSC_XP || - || -
|-
|15 3 ||DWM_SD_DAT2 TSC_YM || - || -
|-
|17 4 ||DWM_SD_DAT3 TSC_XM || - || -
|-
|21 ||DWM_UART_RX || - || -|-|23 ||DWM_UART_CTS || - || -|-|24 ||DWM_BT_F5 || - || -|-|25 ||DWM_UART_TX || - || -|-|26 ||DWM_BT_F2 || - || -|-|27 ||DWM_UART_RTS || - || -|-|28 ||DWM_WIFI_IRQ || - || -|-|29 ||DWM_BT_EN || - || -|-|30 ||DWM_WIFI_EN || - || -|-|} === CAN LVDS - J24 J26 ===J24 J26 is a 10vertical double row straight 20-pin 5x2x21.54mm 25mm pitch vertical header directly connected . This interface shows how to implement a differential connection to Bora Xpress SoM's transceiver for the CAN interfacean LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki. This 2analog.5mmcom/resources/tools-pitch header is compatible with commonly available IDCsoftware/linux-10drivers/platforms/DB9 flat cableszynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 6,<br>7, 8,<br>9, 10 2 ||N.C3. 3V_LCD || - || -
|-
|23, 5 4, 7, 10,<br>13, 16, 19 ||CAN_SHIELD DGND || - Ground || -
|-
|3 5 ||CAN_L LCD_LVDS_D0- || - || -
|-
|4 6 ||CAN_H LCD_LVDS_D0+ || - || -|-|8 ||LCD_LVDS_D1- || - || -|-|9 ||LCD_LVDS_D1+ || - || -|-|11 ||LCD_LVDS_D2- || - || -|-|12 ||LCD_LVDS_D2+ || - || -
|-
|} === Touch screen 14 ||LCD_LVDS_CLK- J25===J25 is a ZIF 4|| -pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector: {| class="wikitable" | -
|-
!Pin# !Pin name!Function!Notes|15 ||LCD_LVDS_CLK+ || - || -
|-
|1 17 ||TSC_YP LCD_P17 || - || -
|-
|2 18 ||TSC_XP LCD_P18 || - || -
|-
|3 20 ||TSC_YM LCD_P20 || - || -
|-
|4 21,22 ||TSC_XM DGND || - Ground || -Shield
|-
|}
=== LVDS FPGA Mezzanine Card (FMC) Connector - J26 J27 ===J26 J27 is a vertical double row straight 20400 pins ANSI/VITA 57.1-pin 12008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.25mm pitch header Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. This interface shows  The following tables detail how BORA Xpress signals have been routed to implement a differential connection to an LCD screenFMC connector. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by At this example[[: httpsFile://wikiBoraXEVB-FMC-routing.analogzip|link]] a spreadsheet providing the same information is available for download.com For more information about I/resources/toolsO voltage of single-softwareended signals available on FMC connector, please refer to [[#PL's I/linux-drivers/platforms/zynqO voltage selections|this section]]. The following table reports the pinout of the connector: ==== HPC Row A ====
{| class="wikitable"
!Notes
|-
|1, 2 A1||3.3V_LCD DGND|| - GND|| -
|-
|3, 4, 7, 10,<br>13, 16, 19 A2||DGND MGTxRXP1|| Ground DP1_M2C_P|| -
|-
|5 A3||LCD_LVDS_D0- MGTxRXN1|| - DP1_M2C_N|| -
|-
|6 A4||LCD_LVDS_D0+ DGND|| - GND|| -
|-
|8 A5||LCD_LVDS_D1- DGND|| - GND|| -
|-
|9 A6||LCD_LVDS_D1+ MGTxRXP2|| - DP2_M2C_P|| -
|-
|11 A7||LCD_LVDS_D2- MGTxRXN2|| - DP2_M2C_N|| -
|-
|12 A8||LCD_LVDS_D2+ DGND|| - GND|| -
|-
|15 A9||LCD_LVDS_CLK+ DGND|| - GND|| -
|-
|17 A10||LCD_P17 MGTxRXP3|| - DP3_M2C_P|| -
|-
|18 A11||LCD_P18 MGTxRXN3|| - DP3_M2C_N|| -
|-
|20 A12||LCD_P20 DGND|| - GND|| -
|-
|21,22 A13||DGND || Ground GND|| Shield
|-
|} A14||<span style=== FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is"color:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is #ff0000">not fully populated. ==== HPC Row A ==== {connected</span>||DP4_M2C_P|| class="wikitable"
|-
!Pin| A15||<span style="color:# !Pin name!Function!Notesff0000">not connected</span>||DP4_M2C_N||
|-
| A1A16||DGND||GND||
|-
| A2A17||MGTxRXP1DGND||DP1_M2C_PGND||
|-
| A3A18||MGTxRXN1<span style="color:#ff0000">not connected</span>||DP1_M2C_NDP5_M2C_P||
|-
| A4||DGND||GND|||-| A5||DGND||GND|||-| A6||MGTxRXP2||DP2_M2C_P|||-| A7||MGTxRXN2||DP2_M2C_N|||-| A8||DGND||GND|||-| A9||DGND||GND|||-| A10||MGTxRXP3||DP3_M2C_P|||-| A11||MGTxRXN3||DP3_M2C_N|||-| A12||DGND||GND|||-| A13||DGND||GND|||-| A14||NC||DP4_M2C_P|||-| A15||NC||DP4_M2C_N|||-| A16||DGND||GND|||-| A17||DGND||GND|||-| A18||NC||DP5_M2C_P|||-| A19||NC<span style="color:#ff0000">not connected</span>||DP5_M2C_N||
|-
| A20||DGND||GND||
| A33||DGND||GND||
|-
| A34||NC<span style="color:#ff0000">not connected</span>||DP4_C2M_P||
|-
| A35||NC<span style="color:#ff0000">not connected</span>||DP4_C2M_N||
|-
| A36||DGND||GND||
| A37||DGND||GND||
|-
| A38||NC<span style="color:#ff0000">not connected</span>||DP5_C2M_P||
|-
| A39||NC<span style="color:#ff0000">not connected</span>||DP5_C2M_N||
|-
| A40||DGND||GND||
| B3||DGND||GND||
|-
| B4||NC<span style="color:#ff0000">not connected</span>||DP9_M2C_P||
|-
| B5||NC<span style="color:#ff0000">not connected</span>||DP9_M2C_N||
|-
| B6||DGND||GND||
| B7||DGND||GND||
|-
| B8||NC<span style="color:#ff0000">not connected</span>||DP8_M2C_P||
|-
| B9||NC<span style="color:#ff0000">not connected</span>||DP8_M2C_N||
|-
| B10||DGND||GND||
| B11||DGND||GND||
|-
| B12||NC<span style="color:#ff0000">not connected</span>||DP7_M2C_P||
|-
| B13||NC<span style="color:#ff0000">not connected</span>||DP7_M2C_N||
|-
| B14||DGND||GND||
| B15||DGND||GND||
|-
| B16||NC<span style="color:#ff0000">not connected</span>||DP6_M2C_P||
|-
| B17||NC<span style="color:#ff0000">not connected</span>||DP6_M2C_N||
|-
| B18||DGND||GND||
| B23||DGND||GND||
|-
| B24||NC<span style="color:#ff0000">not connected</span>||DP9_C2M_P||
|-
| B25||NC<span style="color:#ff0000">not connected</span>||DP9_C2M_N||
|-
| B26||DGND||GND||
| B27||DGND||GND||
|-
| B28||NC<span style="color:#ff0000">not connected</span>||DP8_C2M_P||
|-
| B29||NC<span style="color:#ff0000">not connected</span>||DP8_C2M_N||
|-
| B30||DGND||GND||
| B31||DGND||GND||
|-
| B32||NC<span style="color:#ff0000">not connected</span>||DP7_C2M_P||
|-
| B33||NC<span style="color:#ff0000">not connected</span>||DP7_C2M_N||
|-
| B34||DGND||GND||
| B35||DGND||GND||
|-
| B36||NC<span style="color:#ff0000">not connected</span>||DP6_C2M_P||
|-
| B37||NC<span style="color:#ff0000">not connected</span>||DP6_C2M_N||
|-
| B38||DGND||GND||
| E11||DGND||GND||
|-
| E12||NC<span style="color:#ff0000">not connected</span>||HA13_P||
|-
| E13||NC<span style="color:#ff0000">not connected</span>||HA13_N||
|-
| E14||DGND||GND||
|-
| E15||NC<span style="color:#ff0000">not connected</span>||HA16_P||
|-
| E16||NC<span style="color:#ff0000">not connected</span>||HA16_N||
|-
| E17||DGND||GND||
|-
| E18||NC<span style="color:#ff0000">not connected</span>||HA20_P||
|-
| E19||NC<span style="color:#ff0000">not connected</span>||HA20_N||
|-
| E20||DGND||GND||
|-
| E21||NC<span style="color:#ff0000">not connected</span>||HB03_P||
|-
| E22||NC<span style="color:#ff0000">not connected</span>||HB03_N||
|-
| E23||DGND||GND||
|-
| E24||NC<span style="color:#ff0000">not connected</span>||HB05_P||
|-
| E25||NC<span style="color:#ff0000">not connected</span>||HB05_N||
|-
| E26||DGND||GND||
|-
| E27||NC<span style="color:#ff0000">not connected</span>||HB09_P||
|-
| E28||NC<span style="color:#ff0000">not connected</span>||HB09_N||
|-
| E29||DGND||GND||
|-
| E30||NC<span style="color:#ff0000">not connected</span>||HB13_P||
|-
| E31||NC<span style="color:#ff0000">not connected</span>||HB13_N||
|-
| E32||DGND||GND||
|-
| E33||NC<span style="color:#ff0000">not connected</span>||HB19_P||
|-
| E34||NC<span style="color:#ff0000">not connected</span>||HB19_N||
|-
| E35||DGND||GND||
|-
| E36||NC<span style="color:#ff0000">not connected</span>||HB21_P||
|-
| E37||NC<span style="color:#ff0000">not connected</span>||HB21_N||
|-
| E38||DGND||GND||
| F12||DGND||GND||
|-
| F13||NC<span style="color:#ff0000">not connected</span>||HA12_P||
|-
| F14||NC<span style="color:#ff0000">not connected</span>||HA12_N||
|-
| F15||DGND||GND||
|-
| F16||NC<span style="color:#ff0000">not connected</span>||HA15_P||
|-
| F17||NC<span style="color:#ff0000">not connected</span>||HA15_N||
|-
| F18||DGND||GND||
|-
| F19||NC<span style="color:#ff0000">not connected</span>||HA19_P||
|-
| F20||NC<span style="color:#ff0000">not connected</span>||HA19_N||
|-
| F21||DGND||GND||
|-
| F22||NC<span style="color:#ff0000">not connected</span>||HB02_P||
|-
| F23||NC<span style="color:#ff0000">not connected</span>||HB02_N||
|-
| F24||DGND||GND||
|-
| F25||NC<span style="color:#ff0000">not connected</span>||HB04_P||
|-
| F26||NC<span style="color:#ff0000">not connected</span>||HB04_N||
|-
| F27||DGND||GND||
|-
| F28||NC<span style="color:#ff0000">not connected</span>||HB08_P||
|-
| F29||NC<span style="color:#ff0000">not connected</span>||HB08_N||
|-
| F30||DGND||GND||
|-
| F31||NC<span style="color:#ff0000">not connected</span>||HB12_P||
|-
| F32||NC<span style="color:#ff0000">not connected</span>||HB12_N||
|-
| F33||DGND||GND||
|-
| F34||NC<span style="color:#ff0000">not connected</span>||HB16_P||
|-
| F35||NC<span style="color:#ff0000">not connected</span>||HB16_N||
|-
| F36||DGND||GND||
|-
| F37||NC<span style="color:#ff0000">not connected</span>||HB20_P||
|-
| F38||NC<span style="color:#ff0000">not connected</span>||HB20_N||
|-
| F39||DGND||GND||
| J11||DGND||GND||
|-
| J12||NC<span style="color:#ff0000">not connected</span>||HA11_P||
|-
| J13||NC<span style="color:#ff0000">not connected</span>||HA11_N||
|-
| J14||DGND||GND||
|-
| J15||NC<span style="color:#ff0000">not connected</span>||HA14_P||
|-
| J16||NC<span style="color:#ff0000">not connected</span>||HA14_N||
|-
| J17||DGND||GND||
|-
| J18||NC<span style="color:#ff0000">not connected</span>||HA18_P||
|-
| J19||NC<span style="color:#ff0000">not connected</span>||HA18_N||
|-
| J20||DGND||GND||
|-
| J21||NC<span style="color:#ff0000">not connected</span>||HA22_P||
|-
| J22||NC<span style="color:#ff0000">not connected</span>||HA22_N||
|-
| J23||DGND||GND||
|-
| J24||NC<span style="color:#ff0000">not connected</span>||HB01_P||
|-
| J25||NC<span style="color:#ff0000">not connected</span>||HB01_N||
|-
| J26||DGND||GND||
|-
| J27||NC<span style="color:#ff0000">not connected</span>||HB07_P||
|-
| J28||NC<span style="color:#ff0000">not connected</span>||HB07_N||
|-
| J29||DGND||GND||
|-
| J30||NC<span style="color:#ff0000">not connected</span>||HB11_P||
|-
| J31||NC<span style="color:#ff0000">not connected</span>||HB11_N||
|-
| J32||DGND||GND||
|-
| J33||NC<span style="color:#ff0000">not connected</span>||HB15_P||
|-
| J34||NC<span style="color:#ff0000">not connected</span>||HB15_N||
|-
| J35||DGND||GND||
|-
| J36||NC<span style="color:#ff0000">not connected</span>||HB18_P||
|-
| J37||NC<span style="color:#ff0000">not connected</span>||HB18_N||
|-
| J38||DGND||GND||
|-
| J39||NC<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|-
| J40||DGND||GND||
!Notes
|-
| K1||NC<span style="color:#ff0000">not connected</span>||VREF_B_M2C||
|-
| K2||DGND||GND||
| K13||IO_25_VRP_35||HA10_P||
|-
| K14||NC<span style="color:#ff0000">not connected</span>||HA10_N||
|-
| K15||DGND||GND||
|-
| K16||NC<span style="color:#ff0000">not connected</span>||HA17_P_CC||
|-
| K17||NC<span style="color:#ff0000">not connected</span>||HA17_N_CC||
|-
| K18||DGND||GND||
|-
| K19||NC<span style="color:#ff0000">not connected</span>||HA21_P||
|-
| K20||NC<span style="color:#ff0000">not connected</span>||HA21_N||
|-
| K21||DGND||GND||
|-
| K22||NC<span style="color:#ff0000">not connected</span>||HA23_P||
|-
| K23||NC<span style="color:#ff0000">not connected</span>||HA23_N||
|-
| K24||DGND||GND||
|-
| K25||NC<span style="color:#ff0000">not connected</span>||HB00_P_CC||
|-
| K26||NC<span style="color:#ff0000">not connected</span>||HB00_N_CC||
|-
| K27||DGND||GND||
|-
| K28||NC<span style="color:#ff0000">not connected</span>||HB06_P_CC||
|-
| K29||NC<span style="color:#ff0000">not connected</span>||HB06_N_CC||
|-
| K30||DGND||GND||
|-
| K31||NC<span style="color:#ff0000">not connected</span>||HB10_P||
|-
| K32||NC<span style="color:#ff0000">not connected</span>||HB10_N||
|-
| K33||DGND||GND||
|-
| K34||NC<span style="color:#ff0000">not connected</span>||HB14_P||
|-
| K35||NC<span style="color:#ff0000">not connected</span>||HB14_N||
|-
| K36||DGND||GND||
|-
| K37||NC<span style="color:#ff0000">not connected</span>||HB17_P_CC||
|-
| K38||NC<span style="color:#ff0000">not connected</span>||HB17_N_CC||
|-
| K39||DGND||GND||
|-
| K40||NC<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
|-
|}
===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
==SchematicsPL's I/O voltage selections==PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:*'''each bank must be powered even if none of its I/Os is used'''*'''voltage selection must be done before powering up the board'''. The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
* ORCAD{|class="wikitable" style="text-align: center;"! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35|-| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: httpcenter; font-weight:bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/wwwO voltage setting|-| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|-| style="text-align: center;" | 7030(SBG485 package)| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.dave2 - 1.eu8V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance ===BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/systemO banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''. Since characteristics of PL's I/filesO banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details. Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)===={|class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #35 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style="text-align: center; font-weight: bold;" | JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Examples of valid combinations for Zynq 7015-based SOMs===={|class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|}  {|class="wikitable" style="text-align: center;"|+Bank #35 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style="text-align: center; font-weight: bold;" | JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open |}  {|class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Advanced information about voltage selection connectors========= Bank 13 VDDIO selection connector (JP25) =====JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -|-|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -|-|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -|-|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -|-|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -|-|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V ==Schematics==* ORCAD: [[mirror:bora/hw/BoraXEVB/areaBORAXEVB-1.6.1-riservata/boraxevbBELK-dsn.zip|BORAXEVB-1.06.31-BELK-dsn.zip]]* PDF : http[[mirror:bora/hw/BoraXEVB/wwwS-EVBBX0000C0R-1.6.dave1_color.eu/system/files/area-riservata/pdf|BoraXEVB-S-EVBBX0000C0R-1.26.01.pdf]]
==BOM==
* BoraXEVB: http[[mirror:bora/hw/wwwBoraXEVB/BORAXEVB_S.EVBBX0000C0R.dave1.eu/system/files/area-riservata/boraxevb-BOM_S6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.26.0.CSV_CSV.zip]]
==Layout==
* http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-CS143714_assem_view.davepdf|boraxevb-CS143714_assem_view.eupdf]]==PCB design (Mentor PADS)==* [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb-CS143714_assembly_viewCS143714.zip|CS143714.pdfzip]]
==Mechanical==
* DXF: http[[mirror:bora/hw/wwwBoraXEVB/boraxevb-2D-CS143714.davedxf.eu/system/files/areazip|boraxevb-2D-riservata/boraxevb_2D_CS143714CS143714.dxf.zip]]* IDF (3D): http[[mirror:bora/hw/BoraXEVB/wwwboraxevb-3D-CS143714.davezip|boraxevb-3D-CS143714.euzip]]* STEP (3D): [[mirror:bora/systemhw/filesBoraXEVB/area-riservata/boraxevb_3D_CS143714boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
U0005
a000298_approval, dave_user
299
edits
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