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BoraXEVB

389 bytes removed, 08:21, 5 November 2015
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=== Pin strip connectors ===
==== ADC SPI,NAND - JP30, JP31, JP32 JP13 ====
JP30, JP31, JP32 are 16JP13 is a 12-pin 8x2x26x2x2.54 pitch vertical header. The following tables table reports the pinout of the connectorsconnector:
JP30:
{| class="wikitable"
|-
!Notes
|-
|2 1, 4, 9, 12 || FPGA_BANK35_AD0N DGND || AD0_N Ground || Mount option-
|-
|3 2 || FPGA_BANK35_AD1P SPI0_CS0n || AD1_P - || Mount option-
|-
|4 3 || FPGA_BANK35_AD0P ZYNQ_SPI0_SCLK/NAND_IO1 || AD0_P - || Mount option-
|-
|5 || FPGA_BANK35_AD1N ZYNQ_SPI0_DQ0/NAND_ALE || AD1_N - || Mount option-
|-
|8 6 || FPGA_BANK35_AD2P NAND_CS0/SPI0_CS1 || AD2_P - || Mount option-
|-
|9 7 || FPGA_BANK35_AD3P ZYNQ_SPI0_DQ2/NAND_IO2 || AD3_P - || Mount option-
|-
|10 8 || FPGA_BANK35_AD2N ZYNQ_SPI0_DQ1/NAND_WE || AD2_N - || Mount option-
|-
|11 10 || FPGA_BANK35_AD3N ZYNQ_SPI0_DQ3/NAND_IO0 || AD3_N - || Mount option-
|-
|14 11 || FPGA_BANK35_AD4P || AD4_P || Mount option|-|15 || FPGA_BANK35_AD5P || AD5_P || Mount option|-|16 || FPGA_BANK35_AD4N || AD4_N || Mount option|-|1, 6, 7,<br>12, 13 || DGND ZYNQ_NAND_RD_B || - || -
|-
|}
JP31==== Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD5N MON_VCCPLL || AD5_N - || Mount option-|-|2 || MON_3.3V || - || - |-|3 || MON_XADC_VCC || - || -|-|4 || MON_1V2_ETH || - || -|-|5 || MON_FPGA_VDDIO_BANK35 || - || -
|-
|4 6 || FPGA_BANK35_AD6P MON_VDDQ_1V5 || AD6_P - || Mount option-
|-
|5 7 || FPGA_BANK35_AD7P MON_FPGA_VDDIO_BANK34 || AD7_P - || Mount option-
|-
|6 8 || FPGA_BANK35_AD6N MON_1.8V || AD6_N - || Mount option-
|-
|7 9 || FPGA_BANK35_AD7N MON_FPGA_VDDIO_BANK13 || AD7_N - || Mount option-
|-
|10 || FPGA_BANK35_AD8P MON_1.0V || AD8_P - || Mount option-
|-
|11 || FPGA_BANK35_AD9P MON_1.8V_IO || AD9_P - || Mount option-
|-
|12 || FPGA_BANK35_AD8N MON_MGTAVCC || AD8_N - || Mount option-
|-
|13 || FPGA_BANK35_AD9N MON_MGTAVTT || AD9_N - || Mount option-
|-
|16 14 || FPGA_BANK35_AD10P MON_MGTAVCCAUX || AD10_P - || Mount option-
|-
|2, 3, 8,<br>915, 14, 15 16 || DGND || - Ground || -
|-
|}
JP32==== Ethernet GPIO - JP18 ====JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1 , 2, 5,<br>6, 16|| FPGA_BANK35_AD11P DGND || AD11_P Ground || Mount option-
|-
|2 3 || FPGA_BANK35_AD10N CLK125_NDO|| AD10_N - || Mount option-
|-
|3 4 || FPGA_BANK35_AD11N ETH1_CLK125_NDO || AD11_N - || Mount option-
|-
|6 7 || FPGA_BANK35_AD12P ETH_MDC || AD12_P - || Mount option-
|-
|7 8 || FPGA_BANK35_AD13P ETH1_MDC || AD13_P - || Mount option-
|-
|8 9 || FPGA_BANK35_AD12N ETH_MDIO || AD12_N - || Mount option-
|-
|9 10 || FPGA_BANK35_AD13N ETH1_MDIO || AD13_N - || Mount option-
|-
|12 11 || FPGA_BANK35_AD14P ETH_INTn || AD14_P - || Mount option-
|-
|13 12 || FPGA_BANK35_AD15P ETH1_INTn || AD15_P - || Mount option-
|-
|14 13 || FPGA_BANK35_AD14N PS_MIO51_501 || AD14_N - || Mount option-
|-
|15 14 || FPGA_BANK35_AD15N ETH1_RESETn || AD15_N - || Mount option-
|-
|4, 5, 10,<br>11, 16 15 || DGND PS_MIO50_501 || - || -
|-
|}
==== SPI,NAND - JP13 ====
JP13 ==== SPI,NAND - JP19 ====JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 4, 911, 12 || DGND || Ground || -|-|2 || NAND_BUSY|| - || -
|-
|2 3 || SPI0_CS0n ZYNQ_NAND_CLE || - || -
|-
|3 4 || ZYNQ_SPI0_SCLK/NAND_IO1 NAND_IO3 || - || -
|-
|5 || ZYNQ_SPI0_DQ0/NAND_ALE NAND_IO4 || - || -
|-
|6 || NAND_CS0/SPI0_CS1 NAND_IO5 || - || -
|-
|7 || ZYNQ_SPI0_DQ2/NAND_IO2 NAND_IO6 || - || -
|-
|8 || ZYNQ_SPI0_DQ1/NAND_WE NAND_IO7 || - || -
|-
|10 9 || ZYNQ_SPI0_DQ3/NAND_IO0 CONN_SPI_RSTn || - || -
|-
|11 10 || ZYNQ_NAND_RD_B MEM_WPn || - || -
|-
|}
==== Voltage Monitor FPGA, WatchDog, RTC, RST - JP15 JP22 ==== JP15 JP22 is a 1216-pin 6x2x28x2x2.00 54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 || MON_VCCPLL FPGA_INIT_B|| - || -
|-
|2 || MON_3.3V RTC_32KHZ || - || -
|-
|3 || MON_XADC_VCC FPGA_PROGRAM_B|| - || -
|-
|4 || MON_1V2_ETH RTC_RST || - || -
|-
|5 || MON_FPGA_VDDIO_BANK35 FPGA_DONE || - || -
|-
|6 || MON_VDDQ_1V5 RTC_INT/SQW || - || -
|-
|7 , 8 || MON_FPGA_VDDIO_BANK34 DGND || - Ground || -
|-
|8 9 || MON_1.8V WD_SET0 || - || -
|-
|9 10 || MON_FPGA_VDDIO_BANK13 SYS_RSTn || - || -
|-
|10 11 || MON_1.0V WD_SET1 || - || -
|-
|11 12 || MON_1.8V_IO PORSTn || - || -
|-
|12 13 || DGND WD_SET2 || Ground - || -
|-
|}  ==== Ethernet GPIO 14 || MRSTn || - JP18 ====JP18 is a 12|| -pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes|15 || PS_MIO15_500 || - || -
|-
|1, 11, 1216 || DGND || Ground || -|-|2 || NAND_BUSY|| - || -|-|3 || ZYNQ_NAND_CLE || - || -|-|4 || NAND_IO3 || - || -|-|5 || NAND_IO4 || - || -|-|6 || NAND_IO5 || - || -|-|7 || NAND_IO6 || - || -|-|8 || NAND_IO7 || - || -|-|9 || CONN_SPI_RSTn || - || -|-|10 || MEM_WPn CB_PWR_GOOD || - || -
|-
|}
==== SPI,NAND AUX PINs - JP19 JP29 ====JP19 JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1, || EVB_1.8V || - || -|-|2, 5,<br>6, 16|| DGND 3.3V || Ground - || -
|-
|3 || CLK125_NDOPS_I2C0_DAT|| - || -
|-
|4 || ETH1_CLK125_NDO I2C0_SDA || - || -
|-
|7 5 || ETH_MDC PS_I2C0_CK || - || -
|-
|8 6 || ETH1_MDC I2C0_SCL || - || -
|-
|9 7, 8,<br>13 || ETH_MDIO DGND || - Ground || -
|-
|10 9 || ETH1_MDIO EXT_VMON2_V1 || - || -Mount option
|-
|11 10, 16 ||ETH_INTn XADC_AGND || - Analog Ground || -
|-
|12 11 || ETH1_INTn EXT_VMON2_V2 || - || -Mount option
|-
|13 12 || PS_MIO51_501 XADC_VN_R || - || -
|-
|14 || ETH1_RESETn XADC_VP_R || - || -
|-
|15 || PS_MIO50_501 INA_ALERT || - || -
|-
|}
==== ADC - JP20 ====Please note that:JP20 * Three devices are connected to I2C0 bus (this is a 12-pin 6x2x2level shifted from 1.54 pitch vertical header8V to 3. The following table reports 3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the pinout of the connectoruser to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor:this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
 
JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:
 
JP30:
{| class="wikitable"
|-
!Notes
|-
|1 2 || VDDIO_BANK35FPGA_BANK35_AD0N || AD0_N || Mount option| - |3 || FPGA_BANK35_AD1P || AD1_P || Mount option| -|4 || FPGA_BANK35_AD0P || AD0_P || Mount option|-|5 || FPGA_BANK35_AD1N || AD1_N || Mount option
|-
|2, 6,<br>11, 12 8 || XADC_AGND FPGA_BANK35_AD2P || - AD2_P || -Mount option
|-
|3 9 || ZYNQ_AD0P_35 FPGA_BANK35_AD3P || - AD3_P || -Mount option
|-
|4 10 || MON_XADC_VCC FPGA_BANK35_AD2N || - AD2_N || -Mount option
|-
|5 11 || ZYNQ_AD15P_35 FPGA_BANK35_AD3N || - AD3_N || -Mount option
|-
|7 14 || ZYNQ_AD15N_35 FPGA_BANK35_AD4P || - AD4_P || -Mount option
|-
|8 15 || XADC_VN_R FPGA_BANK35_AD5P || - AD5_P || -Mount option
|-
|9 16 || ZYNQ_AD2P_35 FPGA_BANK35_AD4N || - AD4_N || -Mount option
|-
|10 1, 6, 7,<br>12, 13 || XADC_VP_R DGND || - || -
|-
|}
==== I2C, BANK34 - JP21 ====JP21 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorJP31:
{| class="wikitable"
|-
!Notes
|-
|1 || EVB_1.8V FPGA_BANK35_AD5N || - AD5_N || -Mount option
|-
|2 4 || 3.3V FPGA_BANK35_AD6P || - AD6_P || -Mount option
|-
|3 5 || PS_I2C0_DATFPGA_BANK35_AD7P || - AD7_P || -Mount option
|-
|4 6 || I2C0_SDA FPGA_BANK35_AD6N || - AD6_N || -Mount option
|-
|5 7 || PS_I2C0_CK FPGA_BANK35_AD7N || - AD7_N || -Mount option
|-
|6 10 || I2C0_SCL FPGA_BANK35_AD8P || - AD8_P || -Mount option
|-
|7, 8,<br>12, 13 11 || DGND FPGA_BANK35_AD9P || Ground AD9_P || -Mount option
|-
|9 12 || IO_L6P_T0_34 FPGA_BANK35_AD8N || CAN Transmitter AD8_N || -Mount option
|-
|10 13 || INA_ALERT FPGA_BANK35_AD9N || - AD9_N || -Mount option
|-
|11 16 || IO_L19P_T3_34 FPGA_BANK35_AD10P || CAN Receiver AD10_P || -Mount option
|-
|2, 3, 8,<br>9, 14 || IO_L3P_T0_DQS_PUDC_B_34 || - || -|-|, 15 || IO_25_34 || - || -|-|16 || IO_0_34 DGND || - || -
|-
|}
Please note that: * Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption ==== FPGA, WatchDog, RTC, RST - JP22 ====JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connectorJP32:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_INIT_BFPGA_BANK35_AD11P || - AD11_P || -Mount option
|-
|2 || RTC_32KHZ FPGA_BANK35_AD10N || - AD10_N || -Mount option
|-
|3 || FPGA_PROGRAM_BFPGA_BANK35_AD11N || - AD11_N || -Mount option
|-
|4 6 || RTC_RST FPGA_BANK35_AD12P || - AD12_P || -Mount option
|-
|5 7 || FPGA_DONE FPGA_BANK35_AD13P || - AD13_P || -Mount option
|-
|6 8 || RTC_INT/SQW FPGA_BANK35_AD12N || - AD12_N || -Mount option
|-
|7, 8 9 || DGND FPGA_BANK35_AD13N || Ground AD13_N || -Mount option
|-
|9 12 || WD_SET0 FPGA_BANK35_AD14P || - AD14_P || -Mount option
|-
|10 13 || SYS_RSTn FPGA_BANK35_AD15P || - AD15_P || -Mount option
|-
|11 14 || WD_SET1 FPGA_BANK35_AD14N || - AD14_N || -Mount option
|-
|12 15 || PORSTn FPGA_BANK35_AD15N || - AD15_N || -Mount option
|-
|13 || WD_SET2 || - || -|-|14 || MRSTn || - || -|-|15 || PS_MIO15_500 || - || -|-|4, 5, 10,<br>11, 16 || CB_PWR_GOOD DGND || - || -
|-
|}
 
=== Digilent Pmod™ Compatible headers ===
U0004
136
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