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BoraXEVB

2,474 bytes added, 10:02, 26 January 2022
→‎Bank 35 VDDIO selection connector (JP27)
{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
 
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/>
==Block Diagram==
====Bora Lite====
[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
 
<section end=Block Diagram/>
== Features ==
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
 
<section begin=Reset button/>
 
=== Reset button - S6 ===
 
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
 
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[:Category:BoraLite BORA Lite SOM|BoraLiteBORA Lite]] SOM module <section end=Boot Configurations/><section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
{| class="wikitable"
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/><section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
<section end=Ethernet1/>
=== BANK's Power GOOD signals - J28 ===
|-
|}
 
<section begin=JTAG/>
=== JTAG ===
|-
|}
<section end=JTAG/>
<section begin=Console/>
=== UART1 - J17 ===
|-
|}
<section end=Console/>
<section begin=USB OTG/>
=== USB OTG - J19 ===
|-
|}
<section end=USB OTG/>
<section begin=micro SD/>
=== MicroSD - J21 ===
|-
|}
<section end=micro SD/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) DWM_ADD-ON | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=DWM/>
 
<section begin=CAN/>
=== CAN - J24 ===
|-
|}
<section end=CAN/><section begin=Touchscreen/>
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
|-
|}
<section end=Touchscreen/><section begin=LVDS/>
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|-
|}
<section end=LVDS/><section begin=FMC/>
=== FPGA Mezzanine Card (FMC) Connector - J27 ===
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
| K40||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
<section end=FMC/><section begin=PinStrip/>
=== Pin strip connectors ===
|}
<section begin=RTC/>
<section end=PinStrip/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/>
==== AUX PINs - JP29 ====
|}
<section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
|-
|}
<section end=PMOD/> ===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
==PL's I/O voltage selections==
<section begin=Voltage selections/>
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
|-
| rowspan="2" |Bora Lite
|style="text-align: center;" | 7007S/7010(CLG400 package)| style="text-align: center;" |HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" |User defined
|-
|style="text-align: center;" | 7014S/7020(CLG400 package)| style="text-align: center;" |HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | User defined|style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" |User defined
|}
[1]
{| class="wikitable" style="text-align: center;"
|+Bank #34 (HPHR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
{{ImportantMessage|text=Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator.For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10.<br>Then, check and/or properly configure JP27 for selecting the required VDDIO_BANK35}}
===== Bank 34 and VADJ VDDIO selection connector (JP28) =====
The default configuration is:
# Jumper on 5-6 -> supply VADJ with 1.8V
<section end=Voltage selections/>
 
<section begin=SOM/>
==SoM's signals mapping==
===Bora Lite===
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''.
{| class="wikitable"
!Note
|-
| rowspan="5654" |34
| rowspan="2" |IO_0_34
| rowspan="2" |'''IO_0_VRN_34'''
|TP SMD
|-
| rowspan="2" |IO_L19P_T3_34|<s>IO_L19P_T3_34<n/s>a|J27D.G18n/a|FMC connAt the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.| rowspan="2" || rowspan="2" || rowspan="2" ||-|'''Used on adapter for CAN_RX'''|J24|CAN
|-
|IO_L1N_T0_34
|
|-
| rowspan="2" |IO_L6P_T0_34|<s>IO_L6P_T0_34<n/s>a|J27B.D14n/a|FMC connAt the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.| rowspan="2" || rowspan="2" || rowspan="2" ||-|'''Used on adapter for CAN_TX'''|J24|CAN
|-
|IO_L7N_T1_34
|-
| rowspan="26" |13
'''(not available on Zynq 7007S and 7010)'''
|IO_L11P_T1_SRCC_13
|'''IO_L23P_T3_13'''
|JP17.3
|PMOD [A]
|-
|IO_L11N_T1_SRCC_13
|'''IO_L23N_T3_13'''
|JP17.4
|PMOD [A]
|-
|IO_L12P_T1_MRCC_13
|'''IO_L9P_T1_DQS_13'''
|JP17.2
|PMOD [A]
|-
|IO_L12N_T1_MRCC_13
|'''IO_L9N_T1_DQS_13'''
|JP17.1
|PMOD [A]
|-
|IO_L13P_T2_MRCC_13
|'''IO_L7P_T1_13'''
|JP17.7
|PMOD [A]
|-
|IO_L13N_T2_MRCC_13
|'''IO_L7N_T1_13'''
|JP17.8
|PMOD [A]
|-
|IO_L14P_T2_SRCC_13
|'''IO_L15P_T2_DQS_13'''
|n/a
|ETH1_RXCK
|-
|IO_L14N_T2_SRCC_13
|'''IO_L15N_T2_DQS_13'''
|n/a
|ETH1_RXCTL
|-
|IO_L15P_T2_DQS_13
|'''IO_L5P_T0_13'''
|JP17.6
|PMOD [A]
|-
|IO_L15N_T2_DQS_13
|'''IO_L5N_T0_13'''
|JP17.5
|PMOD [A]
|NAND_CLE/VCFG0
|}
<section end=SOM/>
 
<section begin=Schematics/>
==Schematics==
* ORCAD: [[mirrorhttps:bora/hw/BoraXEVB/BORAXEVB-1www.6dave.1-BELK-dsn.zip|eu/links/p/yYW9VNsGutz6V0dd BORAXEVB-1.6.1-BELK-dsn.zip]]* PDF : [[mirrorhttps:bora/hw/www.dave.eu/links/p/hClB4N7blBdSG6AH BoraXEVB/-S-EVBBX0000C0R-1.6.1_color1.pdf|] ===BOM===* BoraXEVB-S-: [https://www.dave.eu/links/p/PU08ewKLvX9Z9tZJ BORAXEVB_S.EVBBX0000C0R-.1.6.10.CSV.pdf]zip]
==BOM=Layout===* BoraXEVB: [[mirrorhttps:bora/hw/BoraXEVB/BORAXEVB_Swww.EVBBX0000C0Rdave.1.6.0.CSV.zip|BORAXEVB_S.EVBBX0000C0R.1.6.0.CSV.zip]eu/links/p/cPT5UVAFNiSzj4NR CS143714 Assembly view]
==Layout==* [[mirror:bora/hw/BoraXEVB/boraxevb-CS143714_assem_view.pdf|boraxevb-CS143714_assem_view.pdf]]==PCB design (Mentor PADS)===* [[mirrorhttps:bora/hw/BoraXEVBwww.dave.eu/links/p/BCTblnPPoDiwPrAE CS143714.zip|CS143714.zip]]<section end=Schematics/><section begin=Mechanicals/>
==Mechanical==
* DXF: [[mirrorhttps:bora/hw/BoraXEVB/boraxevb-2D-CS143714www.dxfdave.zip|eu/links/p/s1k5AXL3AiCIo7Fj boraxevb-2D-CS143714.dxf.zip]]* IDF (3D): [[mirrorhttps:bora/hw/BoraXEVBwww.dave.eu/links/p/xeQvq2IvKig5vlfd boraxevb-3D-CS143714.zip|boraxevb-3D-CS143714.zip]]* STEP (3D): [[mirrorhttps:bora/hw/BoraXEVBwww.dave.eu/links/p/cj2s2AlBHkeY7tJ7 boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]<section end=Mechanicals/>
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