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→Bank 35 VDDIO selection connector (JP27)
{{InfoBoxTop}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/>
==Block Diagram==
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].
====BoraX====
[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
====Bora Lite====
[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
<section end=Block Diagram/>
== Features ==
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
<section begin=Reset button/>
=== Reset button - S6 ===
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
{| class="wikitable"
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/><section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
<section end=Ethernet1/>
=== BANK's Power GOOD signals - J28 ===
|-
|}
<section begin=JTAG/>
=== JTAG ===
|-
|}
<section end=JTAG/>
<section begin=Console/>
=== UART1 - J17 ===
|-
|}
<section end=Console/>
<section begin=USB OTG/>
=== USB OTG - J19 ===
|-
|}
<section end=USB OTG/>
<section begin=micro SD/>
=== MicroSD - J21 ===
|8 ||PS_SD0_DAT1||| - || -
|-
|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) DWM_ADD-ON | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=DWM/>
<section begin=CAN/>
=== CAN - J24 ===
|-
|}
<section end=CAN/><section begin=Touchscreen/>
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
|-
|}
<section end=Touchscreen/><section begin=LVDS/>
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|-
|12 ||LCD_LVDS_D2+ || - || -
|-
|14 ||LCD_LVDS_CLK- || - || -
|-
|15 ||LCD_LVDS_CLK+ || - || -
|-
|}
<section end=LVDS/><section begin=FMC/>
=== FPGA Mezzanine Card (FMC) Connector - J27 ===
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zip|link]] a spreadsheet providing the same information is available for download.
For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|this section]].
==== HPC Row A ====
| K40||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
<section end=FMC/><section begin=PinStrip/>
=== Pin strip connectors ===
|-
|}
==== Ethernet GPIO - JP18 ====
|-
|}
==== SPI,NAND - JP19 ====
|}
<section begin=RTC/>
<section end=PinStrip/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/>
==== AUX PINs - JP29 ====
|}
<section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
|-
|}
==== Digilent Pmod™ Compatible - JP23 ====
|-
|}
<section end=PMOD/> ===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
==PL's I/O voltage selections==
<section begin=Voltage selections/>
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
{|class="wikitable" style="text-align: center;"! rowspan="2" |SoM
! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34
| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
| rowspan="2" |BoraX
| style="text-align: center;" | 7015
(CLG485 package)
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|-| rowspan="2" |Bora Lite| style="text-align: center;" | 7007S/7010(CLG400 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|-| style="text-align: center;" | 7014S/7020(CLG400 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance
===BoraXEVB voltage selection jumpers===
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
Even if PL's banks are independent, default configuration of BoraXEVB is such that
*bank 34 and bank 35 have the same supply voltage
*this voltage is selected via JP28.
This configuration is in accordance with default routing of signals used for FMC connector.
====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====
{|class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
{|class="wikitable" style="text-align: center;"
|+Bank #35 (HP)
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
{|class="wikitable" style="text-align: center;"
|+Bank #34 (HP)
|-
====Examples of valid combinations for Zynq 7015-based SOMs====
{|class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
{|class="wikitable" style="text-align: center;"
|+Bank #35 (HR)
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
{|class="wikitable" style="text-align: center;"|+Bank #34 (HPHR)|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP28.1-2
|}
====Detailed jumpers Advanced information about voltage selection connectors========= BANK13 Bank 13 VDDIO selector - selection connector (JP25 ) =====
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
The DEFAULT default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
===== BANK35 Bank 35 VDDIO selector - selection connector (JP27 ) =====
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
{{ImportantMessage|text=Please note that:* By by default VDDIO_BANK35 is supplied by VADJ Regulator. For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10.<br>Then, check and/or properly configure JP27 for selecting the required VDDIO_BANK35}}
===== Bank 34 and VADJ VDDIO selector - selection connector (JP28 ) =====
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
# Jumper on 9-10 -> supply VADJ with 1.2V
The DEFAULT default configuration is:
# Jumper on 5-6 -> supply VADJ with 1.8V
<section end=Voltage selections/>
<section begin=SOM/>
==SoM's signals mapping==
===Bora Lite===
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''.
{| class="wikitable"
|+
! colspan="2" |SoM's signal
! colspan="6" |Routing options at carrier board level
|-
! rowspan="2" |Bank
! rowspan="2" |Name
! colspan="3" |Option #1
(default)
! colspan="3" |Option #2
|-
!Name
!Pin
!Note
!Name
!Pin
!Note
|-
| rowspan="54" |34
| rowspan="2" |IO_0_34
| rowspan="2" |'''IO_0_VRN_34'''
|J31.2
|Header
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J27D.H2
|FMC conn.
|-
| rowspan="2" |IO_25_34
| rowspan="2" |'''IO_25_VRP_35'''
|J31.4
|Header
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J27B.D1
|FMC conn.
|-
|IO_L10N_T1_34
|IO_L10N_T1_34
|J27D.H26
|FMC conn.
|
|
|
|-
|IO_L10P_T1_34
|IO_L10P_T1_34
|J27D.H25
|FMC conn.
|
|
|
|-
|IO_L11N_T1_SRCC_34
|IO_L11N_T1_SRCC_34
|J27D.G3
|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_34
|IO_L11P_T1_SRCC_34
|J27D.G2
|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_34
|IO_L12N_T1_MRCC_34
|J27D.H5
|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_34
|IO_L12P_T1_MRCC_34
|J27D.H4
|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_34
|'''IO_L13N_T1_MRCC_34'''
|J27D.G7
|FMC conn.
|
|
|
|-
|IO_L13P_T2_MRCC_34
|'''IO_L13P_T1_MRCC_34'''
|J27D.G6
|FMC conn.
|
|
|
|-
|IO_L14N_T2_SRCC_34
|IO_L14N_T2_SRCC_34
|J27B.D9
|FMC conn.
|
|
|
|-
|IO_L14P_T2_SRCC_34
|IO_L14P_T2_SRCC_34
|J27B.D8
|FMC conn.
|
|
|
|-
|IO_L15N_T2_DQS_34
|IO_L15N_T2_DQS_34
|J27B.D21
|FMC conn.
|
|
|
|-
|IO_L15P_T2_DQS_34
|IO_L15P_T2_DQS_34
|J27B.D20
|FMC conn.
|
|
|
|-
|IO_L16N_T2_34
|IO_L16N_T2_34
|J27B.C23
|FMC conn.
|
|
|
|-
|IO_L16P_T2_34
|IO_L16P_T2_34
|J27B.C22
|FMC conn.
|
|
|
|-
|IO_L17N_T2_34
|IO_L17N_T2_34
|J27D.G22
|FMC conn.
|
|
|
|-
|IO_L17P_T2_34
|IO_L17P_T2_34
|J27D.G21
|FMC conn.
|
|
|
|-
|IO_L18N_T2_34
|IO_L18N_T2_34
|J27D.H20
|FMC conn.
|
|
|
|-
|IO_L18P_T2_34
|IO_L18P_T2_34
|J27D.H19
|FMC conn.
|
|
|
|-
| rowspan="2" |IO_L19N_T3_VREF_34
| rowspan="2" |IO_L19N_T3_VREF_34
|J27D.G19
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP21
|TP SMD
|-
|IO_L19P_T3_34
|n/a
|n/a
|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L1N_T0_34
|IO_L1N_T0_34
|J27B.C19
|FMC conn.
|
|
|
|-
|IO_L1P_T0_34
|IO_L1P_T0_34
|J27B.C18
|FMC conn.
|
|
|
|-
|IO_L20N_T3_34
|IO_L20N_T3_34
|J27B.D18
|FMC conn.
|
|
|
|-
|IO_L20P_T3_34
|IO_L20P_T3_34
|J27B.D17
|FMC conn.
|
|
|
|-
|IO_L21N_T3_DQS_34
|IO_L21N_T3_DQS_34
|J27D.H17
|FMC conn.
|
|
|
|-
|IO_L21P_T3_DQS_34
|IO_L21P_T3_DQS_34
|J27D.H16
|FMC conn.
|
|
|
|-
|IO_L22N_T3_34
|IO_L22N_T3_34
|J27D.G16
|FMC conn.
|
|
|
|-
|IO_L22P_T3_34
|IO_L22P_T3_34
|J27D.G15
|FMC conn.
|
|
|
|-
|IO_L23N_T3_34
|IO_L23N_T3_34
|J27B.C11
|FMC conn.
|
|
|
|-
|IO_L23P_T3_34
|IO_L23P_T3_34
|J27B.C10
|FMC conn.
|
|
|
|-
|IO_L24N_T3_34
|IO_L24N_T3_34
|J27D.H23
|FMC conn.
|
|
|
|-
|IO_L24P_T3_34
|IO_L24P_T3_34
|J27D.H22
|FMC conn.
|
|
|
|-
|IO_L2N_T0_34
|IO_L2N_T0_34
|J27B.C15
|FMC conn.
|
|
|
|-
|IO_L2P_T0_34
|IO_L2P_T0_34
|J27B.C14
|FMC conn.
|
|
|
|-
|IO_L3N_T0_DQS_34
|IO_L3N_T0_DQS_34
|J27D.G13
|FMC conn.
|
|
|
|-
|IO_L3P_T0_DQS_PUDC_B_34
(10K pull-up on SoM)
|IO_L3P_T0_DQS_PUDC_B_34
|J27D.G12
|FMC conn.
|
|
|
|-
|IO_L4N_T0_34
|IO_L4N_T0_34
|J27D.G10
|FMC conn.
|
|
|
|-
|IO_L4P_T0_34
|IO_L4P_T0_34
|J27D.G9
|FMC conn.
|
|
|
|-
|IO_L5N_T0_34
|IO_L5N_T0_34
|J27D.H11
|FMC conn.
|
|
|
|-
|IO_L5P_T0_34
|IO_L5P_T0_34
|J27D.H10
|FMC conn.
|
|
|
|-
| rowspan="2" |IO_L6N_T0_VREF_34
| rowspan="2" |IO_L6N_T0_VREF_34
|J27B.D15
|FMC conn.
|
|
|
|-
|TP22
|TP SMD
|
|
|
|-
|IO_L6P_T0_34
|n/a
|n/a
|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L7N_T1_34
|IO_L7N_T1_34
|J27D.H8
|FMC conn.
|
|
|
|-
|IO_L7P_T1_34
|IO_L7P_T1_34
|J27D.H7
|FMC conn.
|
|
|
|-
|IO_L8N_T1_34
|IO_L8N_T1_34
|J27D.H14
|FMC conn.
|
|
|
|-
|IO_L8P_T1_34
|IO_L8P_T1_34
|J27D.H13
|FMC conn.
|
|
|
|-
|IO_L9N_T1_DQS_34
|IO_L9N_T1_DQS_34
|J27B.D12
|FMC conn.
|
|
|
|-
|IO_L9P_T1_DQS_34
|IO_L9P_T1_DQS_34
|J27B.D11
|FMC conn.
|
|
|
|-
|
|
|
|
|
|
|
|
|-
| rowspan="54" |35
| rowspan="2" |IO_0_35
| rowspan="2" |'''IO_0_VRN_35'''
|J27C.F1
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J31.1
|Header
|-
| rowspan="2" |IO_25_35
| rowspan="2" |'''IO_25_VRP_35'''
|J27E.K13
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J31.3
|Header
|-
|IO_L10N_T1_AD11N_35
|IO_L10N_T1_AD11N_35
|J27D.G34
|FMC conn.
|FPGA_BANK35_AD11N
|JP32.3
|Header
|-
|IO_L10P_T1_AD11P_35
|IO_L10P_T1_AD11P_35
|J27D.G33
|FMC conn.
|FPGA_BANK35_AD11P
|JP32.1
|Header
|-
|IO_L11N_T1_SRCC_35
|IO_L11N_T1_SRCC_35
|J27E.J3
|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_35
|IO_L11P_T1_SRCC_35
|J27E.J2
|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_35
|IO_L12N_T1_MRCC_35
|J27E.K5
|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_35
|IO_L12P_T1_MRCC_35
|J27E.K4
|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_35
|IO_L13N_T2_MRCC_35
|J27C.F5
|FMC conn.
|
|
|
|-
|IO_L13P_T2_MRCC_35
|IO_L13P_T2_MRCC_35
|J27C.F4
|FMC conn.
|
|
|
|-
|IO_L14N_T2_AD4N_SRCC_35
|IO_L14N_T2_AD4N_SRCC_35
|J27C.E3
|FMC conn.
|FPGA_BANK35_AD4N
|JP30.16
|Header
|-
|IO_L14P_T2_AD4P_SRCC_35
|IO_L14P_T2_AD4P_SRCC_35
|J27C.E2
|FMC conn.
|FPGA_BANK35_AD4P
|JP30.14
|Header
|-
|IO_L15N_T2_DQS_AD12N_35
|IO_L15N_T2_DQS_AD12N_35
|J27D.H38
|FMC conn.
|FPGA_BANK35_AD12N
|JP32.8
|Header
|-
|IO_L15P_T2_DQS_AD12P_35
|IO_L15P_T2_DQS_AD12P_35
|J27D.H37
|FMC conn.
|FPGA_BANK35_AD12P
|JP32.6
|Header
|-
|IO_L16N_T2_35
|IO_L16N_T2_35
|J27D.G37
|FMC conn.
|
|
|
|-
|IO_L16P_T2_35
|IO_L16P_T2_35
|J27D.G36
|FMC conn.
|
|
|
|-
|IO_L17N_T2_AD5N_35
|IO_L17N_T2_AD5N_35
|J27E.K8
|FMC conn.
|FPGA_BANK35_AD5N
|JP31.1
|Header
|-
|IO_L17P_T2_AD5P_35
|IO_L17P_T2_AD5P_35
|J27E.K7
|FMC conn.
|FPGA_BANK35_AD5P
|JP30.15
|Header
|-
|IO_L18N_T2_AD13N_35
|IO_L18N_T2_AD13N_35
|J27E.J7
|FMC conn.
|FPGA_BANK35_AD13N
|JP32.9
|Header
|-
|IO_L18P_T2_AD13P_35
|IO_L18P_T2_AD13P_35
|J27E.J6
|FMC conn.
|FPGA_BANK35_AD13P
|JP32.7
|Header
|-
| rowspan="2" |IO_L19N_T3_VREF_35
| rowspan="2" |IO_L19N_T3_VREF_35
|J27C.F8
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP24
|TP SMD
|-
|IO_L19P_T3_35
|IO_L19P_T3_35
|J27C.F7
|FMC conn.
|
|
|
|-
|IO_L1N_T0_AD0N_35
|IO_L1N_T0_AD0N_35
|J27D.G25
|FMC conn.
|FPGA_BANK35_AD0P
|JP30.4
|Header
|-
|IO_L1P_T0_AD0P_35
|IO_L1P_T0_AD0P_35
|J27D.G24
|FMC conn.
|FPGA_BANK35_AD0N
|JP30.2
|Header
|-
|IO_L20N_T3_AD6N_35
|IO_L20N_T3_AD6N_35
|J27C.E7
|FMC conn.
|FPGA_BANK35_AD6N
|JP31.6
|Header
|-
|IO_L20P_T3_AD6P_35
|IO_L20P_T3_AD6P_35
|J27C.E6
|FMC conn.
|FPGA_BANK35_AD6P
|JP31.4
|Header
|-
|IO_L21N_T3_DQS_AD14N_35
|IO_L21N_T3_DQS_AD14N_35
|J27E.K11
|FMC conn.
|FPGA_BANK35_AD14N
|JP32.14
|Header
|-
|IO_L21P_T3_DQS_AD14P_35
|IO_L21P_T3_DQS_AD14P_35
|J27E.K10
|FMC conn.
|FPGA_BANK35_AD14P
|JP32.12
|Header
|-
|IO_L22N_T3_AD7N_35
|IO_L22N_T3_AD7N_35
|J27E.J10
|FMC conn.
|FPGA_BANK35_AD7N
|JP31.7
|Header
|-
|IO_L22P_T3_AD7P_35
|IO_L22P_T3_AD7P_35
|J27E.J9
|FMC conn.
|FPGA_BANK35_AD7P
|JP31.5
|Header
|-
|IO_L23N_T3_35
|IO_L23N_T3_35
|J27C.F11
|FMC conn.
|
|
|
|-
|IO_L23P_T3_35
|IO_L23P_T3_35
|J27C.F10
|FMC conn.
|
|
|
|-
|IO_L24N_T3_AD15N_35
|IO_L24N_T3_AD15N_35
|J27C.E10
|FMC conn.
|FPGA_BANK35_AD15N
|JP32.15
|Header
|-
|IO_L24P_T3_AD15P_35
|IO_L24P_T3_AD15P_35
|J27C.E9
|FMC conn.
|FPGA_BANK35_AD15P
|JP32.13
|Header
|-
|IO_L2N_T0_AD8N_35
|IO_L2N_T0_AD8N_35
|J27B.D24
|FMC conn.
|FPGA_BANK35_AD8N
|JP31.12
|Header
|-
|IO_L2P_T0_AD8P_35
|IO_L2P_T0_AD8P_35
|J27B.D23
|FMC conn.
|FPGA_BANK35_AD8P
|JP31.10
|Header
|-
|IO_L3N_T0_DQS_AD1N_35
|IO_L3N_T0_DQS_AD1N_35
|J27D.H29
|FMC conn.
|FPGA_BANK35_AD1N
|JP30.5
|Header
|-
|IO_L3P_T0_DQS_AD1P_35
|IO_L3P_T0_DQS_AD1P_35
|J27D.H28
|FMC conn.
|FPGA_BANK35_AD1P
|JP30.3
|Header
|-
|IO_L4N_T0_35
|IO_L4N_T0_35
|J27D.G28
|FMC conn.
|
|
|
|-
|IO_L4P_T0_35
|IO_L4P_T0_35
|J27D.G27
|FMC conn.
|
|
|
|-
|IO_L5N_T0_AD9N_35
|IO_L5N_T0_AD9N_35
|J27B.D27
|FMC conn.
|FPGA_BANK35_AD9N
|JP31.13
|Header
|-
|IO_L5P_T0_AD9P_35
|IO_L5P_T0_AD9P_35
|J27B.D26
|FMC conn.
|FPGA_BANK35_AD9P
|JP31.11
|Header
|-
| rowspan="2" |IO_L6N_T0_VREF_35
| rowspan="2" |IO_L6N_T0_VREF_35
|J27B.C27
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP23
|TP SMD
|-
|IO_L6P_T0_35
|IO_L6P_T0_35
|J27B.C26
|FMC conn.
|
|
|
|-
|IO_L7N_T1_AD2N_35
|IO_L7N_T1_AD2N_35
|J27D.H32
|FMC conn.
|FPGA_BANK35_AD2N
|JP30.10
|Header
|-
|IO_L7P_T1_AD2P_35
|IO_L7P_T1_AD2P_35
|J27D.H31
|FMC conn.
|FPGA_BANK35_AD2P
|JP30.8
|Header
|-
|IO_L8N_T1_AD10N_35
|IO_L8N_T1_AD10N_35
|J27D.G31
|FMC conn.
|FPGA_BANK35_AD10N
|JP32.2
|Header
|-
|IO_L8P_T1_AD10P_35
|IO_L8P_T1_AD10P_35
|J27D.G30
|FMC conn.
|FPGA_BANK35_AD10P
|JP31.16
|Header
|-
|IO_L9N_T1_DQS_AD3N_35
|IO_L9N_T1_DQS_AD3N_35
|J27D.H35
|FMC conn.
|FPGA_BANK35_AD3N
|JP30.11
|Header
|-
|IO_L9P_T1_DQS_AD3P_35
|IO_L9P_T1_DQS_AD3P_35
|J27D.H34
|FMC conn.
|FPGA_BANK35_AD3P
|JP30.9
|Header
|-
|
|
|
|
|
|
|
|
|-
| rowspan="26" |13
'''(not available on Zynq 7007S and 7010)'''
|IO_L11P_T1_SRCC_13
|'''IO_L23P_T3_13'''
|JP17.3
|PMOD [A]
|
|
|
|-
|IO_L11N_T1_SRCC_13
|'''IO_L23N_T3_13'''
|JP17.4
|PMOD [A]
|
|
|
|-
|IO_L12P_T1_MRCC_13
|'''IO_L9P_T1_DQS_13'''
|JP17.2
|PMOD [A]
|IO_L9P_T1_DQS_13
|J30.1
|ONE PIECE
|-
|IO_L12N_T1_MRCC_13
|'''IO_L9N_T1_DQS_13'''
|JP17.1
|PMOD [A]
|IO_L9N_T1_DQS_13
|J30.3
|ONE PIECE
|-
|IO_L13P_T2_MRCC_13
|'''IO_L7P_T1_13'''
|JP17.7
|PMOD [A]
|IO_L7P_T1_13
|J30.24
|ONE PIECE
|-
|IO_L13N_T2_MRCC_13
|'''IO_L7N_T1_13'''
|JP17.8
|PMOD [A]
|IO_L7N_T1_13
|J30.26
|ONE PIECE
|-
|IO_L14P_T2_SRCC_13
|'''IO_L15P_T2_DQS_13'''
|n/a
|ETH1_RXCK
|IO_L15P_T2_DQS_13
|J30.25
|ONE PIECE
|-
|IO_L14N_T2_SRCC_13
|'''IO_L15N_T2_DQS_13'''
|n/a
|ETH1_RXCTL
|IO_L15N_T2_DQS_13
|J30.27
|ONE PIECE
|-
|IO_L15P_T2_DQS_13
|'''IO_L5P_T0_13'''
|JP17.6
|PMOD [A]
|IO_L5P_T0_13
|J30.20
|ONE PIECE
|-
|IO_L15N_T2_DQS_13
|'''IO_L5N_T0_13'''
|JP17.5
|PMOD [A]
|IO_L5N_T0_13
|J30.18
|ONE PIECE
|-
|IO_L16N_T2_13
|IO_L16N_T2_13
|n/a
|ETH1_TXCTL
|IO_L16N_T2_13
|J30.31
|ONE PIECE
|-
|IO_L16P_T2_13
|IO_L16P_T2_13
|n/a
|ETH1_TXCK
|IO_L16P_T2_13
|J30.29
|ONE PIECE
|-
|IO_L17N_T2_13
|IO_L17N_T2_13
|n/a
|ETH1_RXD1
|IO_L17N_T2_13
|J30.35
|ONE PIECE
|-
|IO_L17P_T2_13
|IO_L17P_T2_13
|n/a
|ETH1_RXD0
|IO_L17P_T2_13
|J30.33
|ONE PIECE
|-
|IO_L18N_T2_13
|IO_L18N_T2_13
|n/a
|ETH1_RXD3
|IO_L18N_T2_13
|J30.39
|ONE PIECE
|-
|IO_L18P_T2_13
|IO_L18P_T2_13
|n/a
|ETH1_RXD2
|IO_L18P_T2_13
|J30.37
|ONE PIECE
|-
|IO_L19N_T3_VREF_13
|IO_L19N_T3_VREF_13
|n/a
|ETH1_TXD1
|IO_L19N_T3_VREF_13
|J30.43
|ONE PIECE
|-
|IO_L19P_T3_13
|IO_L19P_T3_13
|n/a
|ETH1_TXD0
|IO_L19P_T3_13
|J30.41
|ONE PIECE
|-
|IO_L20N_T3_13
|IO_L20N_T3_13
|n/a
|ETH1_TXD3
|IO_L20N_T3_13
|J30.47
|ONE PIECE
|-
|IO_L20P_T3_13
|IO_L20P_T3_13
|n/a
|ETH1_TXD2
|IO_L20P_T3_13
|J30.45
|ONE PIECE
|-
|IO_L21N_T3_DQS_13
|IO_L21N_T3_DQS_13
|n/a
|ETH1_MDC
|IO_L21N_T3_DQS_13
|J30.51
|ONE PIECE
|-
|IO_L21P_T3_DQS_13
|IO_L21P_T3_DQS_13
|n/a
|ETH1_MDIO
|IO_L21P_T3_DQS_13
|J30.49
|ONE PIECE
|-
|IO_L22N_T3_13
|IO_L22N_T3_13
|
|
|IO_L22N_T3_13
|J30.55
|ONE PIECE
|-
|IO_L22P_T3_13
|IO_L22P_T3_13
|n/a
|DWM_WIFI_IRQ
|IO_L22P_T3_13
|J30.53
|ONE PIECE
|-
| rowspan="2" |IO_L6N_T0_VREF_13
| rowspan="2" |IO_L6N_T0_VREF_13
|JP23.3
|PMOD [B]
| rowspan="2" |IO_L6N_T0_VREF_13
| rowspan="2" |J30.30
| rowspan="2" |ONE PIECE
|-
|n/a
|USB1_OC
|}
==== BoraXEVB unavailable signals ====
Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector.
{| class="wikitable"
|+
BoraXEVB's signal that are not available when mated with Bora Lite SoM
!Bank
!Carrier's signal
|-
|13
|IO_25_13
|-
|13
|IO_L1P_T0_13
|-
|13
|IO_L1N_T0_13
|-
|13
|IO_L2P_T0_13
|-
|13
|IO_L2N_T0_13
|-
|13
|IO_L3P_T0_DQS_13
|-
|13
|IO_L3N_T0_DQS_13
|-
|13
|IO_L4P_T0_13
|-
|13
|IO_L4N_T0_13
|-
|500
|NAND_CS0/SPI0_CS1
|-
|500
|NAND_IO3
|-
|500
|NAND_IO4
|-
|500
|NAND_IO5
|-
|500
|NAND_IO6
|-
|500
|NAND_IO7
|-
|500
|NAND_RD_B/VCFG1
|-
|500
|NAND_CLE/VCFG0
|}
<section end=SOM/>
<section begin=Schematics/>
==Schematics==
* ORCAD: [https://www.dave.eu/links/p/yYW9VNsGutz6V0dd BORAXEVB-1.6.1-BELK-dsn.zip]
* PDF : [https://www.dave.eu/links/p/hClB4N7blBdSG6AH BoraXEVB-S-EVBBX0000C0R-1.6.1.pdf]
===BOM===* ORCADBoraXEVB: http[https://www.dave.eu/system/fileslinks/area-riservatap/boraxevb-1PU08ewKLvX9Z9tZJ BORAXEVB_S.0.3-BELK-dsnEVBBX0000C0R.zip* PDF : http://www.dave.eu/system/files/area-riservata/BoraXEVB-S-EVBBX0000C0R-1.26.0.pdfCSV.zip]
==BOM=Layout===* BoraXEVB: http[https://www.dave.eu/systemlinks/filesp/area-riservata/boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV_.zipcPT5UVAFNiSzj4NR CS143714 Assembly view]
==Layout=PCB design (Mentor PADS)===* http[https://www.dave.eu/systemlinks/p/filesBCTblnPPoDiwPrAE CS143714]<section end=Schematics/area-riservata><section begin=Mechanicals/boraxevb-CS143714_assembly_view.pdf>
==Mechanical==
* DXF: http[https://www.dave.eu/systemlinks/filesp/areas1k5AXL3AiCIo7Fj boraxevb-riservata/boraxevb_2D_CS143714.zip2D-CS143714]* IDF (3D): http[https://www.dave.eu/systemlinks/filesp/areaxeQvq2IvKig5vlfd boraxevb-3D-riservataCS143714]* STEP (3D): [https:/boraxevb_3D_CS143714/www.dave.zipeu/links/p/cj2s2AlBHkeY7tJ7 boraxevb_3D_step_cs143714]<section end=Mechanicals/>
