{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/> ==Block Diagram== The following picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options=PL's I/O voltage selections==PL's I/O FPGA banks voltage can be selected via configuration jumpers#12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]]. It is worth remembering that ====BoraX====[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]*'''each bank must be powered even if none of its I/Os is used'''*'''voltage selection must be done before powering up the board'''====Bora Lite====[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
The following table recaps the characteristics of the PL's I<section end=Block Diagram/O banks, in terms of allowable power supplies.>
{|class="wikitable" style="text-align: center;"! rowspanFeatures ="2" style="text-align: center; font-weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35|-| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting|-| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|-| style="text-align: center;" | 7030(SBG485 package)| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance
===BoraXEVB voltage selection settings===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.====Zynq 7030-based SOMs (default option for BXELK)========Zynq 7015-based SOMs======Block Diagram==The following picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]== Features == * 10/100/1000 Ethernet #0 (PS)* 10/100/1000 Ethernet #1 (Routed through EMIO)
* 1x USB 2.0 OTG (MicroAB connector)
* 1x Serial port (RS232 DB9)
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
<section begin=Reset button/>
=== Reset button - S6 ===
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
<section begin=JTAG/>== BANK13 VDDIO selector - JP25 = JTAG ===JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ==== J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" |-
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mVThe DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -<section begin=Console/> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11=== UART1 -12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator=== VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
The jumper configurations are:# Jumper on 1-2 -<section begin=USB OTG/> supply VADJ with 3.3V# Jumper on 3=== USB OTG -4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2VJ19 ===
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
{| class=== JTAG ==="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 ||USB_OTG_VBUS || - || -JTAG port is available as two different mechanical connectors:|-* |2.00mm||USBM1 || - || -|-|3 ||USBP1 || - || -|-|4 ||OTG_ID || - || -|-|5 ||USB_OTG_DGND || - || -pitch 7x2 header (Xilinx standard)* 2.54mm|-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations|6, 7, depending on bootstrap signals. In case split mode is selected8, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.9 ||USB_OTG_SHIELD || - || -|-|}* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI<section end=USB OTG/VITA FPGA Mezzanine Card (FMC) Standard.> <section begin=micro SD/>=== MicroSD - J21 ===
==== JTAG XILINX J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage- J13 ====level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
|14 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[DWM_ADD-ON | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
==== JTAG ARM - J18 ====
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
J17 === CAN - J24 ===J24 is a standard DB9 connector that routes 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the signals coming from the RS232 transceiver that CAN interface. This 2.5mm-pitch header is connected to compatible with commonly available IDC-10/DB9 flat cables. The following table reports the PS MIO signals pinout of the UART1 port.connector:
|34 |UART_EXT_TX|Transmit lineCAN_H |Connected to protection diode array|-|5|DGND|Ground||-|7, 8|N.C.|N.C.|Connected to protection diode array
|-
|}
<section end=CAN/><section begin=Touchscreen/>=== USB OTG Touch screen - J19 J25=== J19 J25 is a standard USB MICRO AB ZIF 4-pin 1.0mm pitch connector. It is connected that connects the touchscreen drive lines to the BORA touch screen controller on the BoORA Xpress USB 2.0 OTG peripheralEVB. The following table reports the pinout of the connector:
<section end=Touchscreen/><section begin=LVDS/>=== MicroSD LVDS - J21 J26 === J21 J26 is a microSD memory card connectorvertical double row straight 20-pin 1.25mm pitch header. It is connected This interface shows how to the BORA Xpress SOM through implement a bidirectional 1differential connection to an LCD screen.8VAs known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://3wiki.3V voltageanalog.com/resources/tools-software/linux-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8Vdrivers/platforms/zynq. The following table reports the pinout of the connector:
|13 14 |3.3V|LCD_LVDS_CLK- || - || ||Pull up to 3.3V with 10K Ohm -
|-
|15 ||LCD_LVDS_CLK+ || - || -|-|17 ||LCD_P17 || - || -|-|18 ||LCD_P18 || - || -|-|20 ||LCD_P20 || - || -|-|21,22 ||DGND || Ground || Shield|-|}<section end=LVDS/><section begin=FMC/>== DWM = FPGA Mezzanine Card (DAVE Wifi/BT moduleFMC) socket Connector - J23 J27 ===J23 J27 is a 52991400 pins ANSI/VITA 57.1-0308 2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector type (30 pins, vertical, 0.50mm picth). This socket connects the At this [[Wireless_Module_(DWM) :File:BoraXEVB-FMC-routing.zip| DWM Wireless Modulelink]] (optional) to a spreadsheet providing the BORA Xpress EVBsame information is available for download. The following table reports the pinout For more information about I/O voltage of the single-ended signals available on FMC connector:, please refer to [[#PL's I/O voltage selections|this section]]. ==== HPC Row A ==== {| class="wikitable"
|}=== CAN - J24 ===J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:{A21||DGND||GND|| class="wikitable"
|}=== Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:{A27||MGTxTXN2||DP2_C2M_N|| class="wikitable"
=== LVDS - J26 = HPC Row B ====J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|} B17||<span style=== FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.Please note that BoraXpress EVB FMC Connector is"color:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is #ff0000">not fully populated.The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipconnected</span>||DP6_M2C_N|link]] a spreadsheet providing the same information is available for download.==== HPC Row A ===={| class="wikitable"
| J23K40||DGND<span style="color:#ff0000">not connected</span>||GNDVIO_B_M2C|||}<section end=FMC/><section begin=PinStrip/>=== Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
| K16|} ==== Ethernet GPIO - JP18 ====JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|<span styleclass="color:#ff0000wikitable">not connected</span>||HA17_P_CC||
| K30} ==== SPI,NAND - JP19 ====JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 11, 12||DGND||GNDGround ||-
<section begin=RTC/><section end== Pin strip connectors ===PinStrip/>==== SPIFPGA, WatchDog, RTC,NAND RST - JP13 JP22 ==== JP13 JP22 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
==== Ethernet GPIO - JP18 ====JP18 is a JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following table tables reports the pinout of the connectorconnectors:
<section begin=PMOD/>===Digilent Pmod™ Compatible headers == AUX PINs = Please note that: * Digilent Pmod™ Interface Specification - JP29 defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP29 JP17 is a 1612-pin 8x2x26x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|11 || EXT_VMON2_V2 || } ==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12- pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{|| Mount optionclass="wikitable"
|}Please note that:* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption==== ADC ||PMOD_B1 || - JP30, JP31, JP32 ====JP30, JP31, JP32 are 16|| -pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:JP30:{| class="wikitable"
JP32:==== BoraXEVB unavailable signals ====Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector. {| class="wikitable" |-!Pin# +!Pin nameBoraXEVB's signal that are not available when mated with Bora Lite SoM!FunctionBank!Notes|-|1 || FPGA_BANK35_AD11P || AD11_P || Mount option|-|2 || FPGA_BANK35_AD10N || AD10_N || Mount option|-|3 || FPGA_BANK35_AD11N || AD11_N || Mount option|-|6 || FPGA_BANK35_AD12P || AD12_P || Mount option|-|7 || FPGA_BANK35_AD13P || AD13_P || Mount option|-|8 || FPGA_BANK35_AD12N || AD12_N || Mount option|-|9 || FPGA_BANK35_AD13N || AD13_N || Mount option|-|12 || FPGA_BANK35_AD14P || AD14_P || Mount optionCarrier's signal
|-
|13 || FPGA_BANK35_AD15P || AD15_P || Mount optionIO_25_13
|-
|14 13|| FPGA_BANK35_AD14N || AD14_N || Mount optionIO_L1P_T0_13
|-
|15 13|| FPGA_BANK35_AD15N || AD15_N || Mount optionIO_L1N_T0_13
|}13 === Digilent Pmod™ Compatible headers ===Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ====JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" IO_L2N_T0_13