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→Bank 35 VDDIO selection connector (JP27)
{{InfoBoxTop}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/> ==Block Diagram== The following picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]]. ====BoraX====[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]] ====Bora Lite===PL's I/O voltage selections=[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]] <section end=Block Diagram/>
* 1x MicroSD
* 1x FPGA Mezzanine Card (FMC) Connector
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
<section begin=Reset button/>
=== Reset button - S6 ===
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
{| class="wikitable"
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/><section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
<section end=Ethernet1/>
=== BANK's Power GOOD signals - J28 ===
|}
<section begin=JTAG/>== BANK13 VDDIO selector - JP25 = JTAG ===JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ==== J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" |-!Pin# !Pin name
!Function
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGND|| - || -|-|2 || LDO_B13_1V63.3V|| adds +1.6V to VDDIO_BANK13 - || -
|-
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
!Pin#
!Pin name
!Notes
|-
|1 || 3.3V|| - || -|-|2 || LDO_B35_1V63.3V|| adds +1- || -|-|3, 11, 17, 19 || N.C.6V to VDDIO_BANK35 || - || -
|-
|4 , 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_800mVDGND|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 5 || LDO_B35_400mVJTAG_TDI|| adds +400mV to VDDIO_BANK35 - || -
|-
|8 7 || LDO_B35_200mVJTAG_TMS|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 9 || LDO_B35_100mVJTAG_TCK|| adds +100mV to VDDIO_BANK35 - || -
|-
|12 13 || LDO_B35_50mVJTAG_TDO|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 15 || DGNDJTAG_TRSTn|| - || -
|-
|}
<section end=JTAG/>
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 || VADJ_FB (51K1)|| selects 1.8V VADJ |3| -UART_EXT_TX|-Transmit line|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -Connected to protection diode array
|-
|10 5|DGND| VADJ_FB (100K)Ground|| selects 1.2V VADJ || -
|-
|12 || RFU|7, 8| Reserved || -N.C.|-N.C.|1, 3, 5, 7, 9, 11 || DGND|| - || -Connected to protection diode array
|-
|}
<section end=Console/>
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
{| class=== JTAG ==="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 ||USB_OTG_VBUS || - || -JTAG port is available as two different mechanical connectors:|-* |2.00mm||USBM1 || - || -|-|3 ||USBP1 || - || -|-|4 ||OTG_ID || - || -|-|5 ||USB_OTG_DGND || - || -pitch 7x2 header (Xilinx standard)* 2.54mm|-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations|6, 7, depending on bootstrap signals. In case split mode is selected8, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.9 ||USB_OTG_SHIELD || - || -|-|}* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI<section end=USB OTG/VITA FPGA Mezzanine Card (FMC) Standard.> <section begin=micro SD/>=== MicroSD - J21 ===
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|4 3 || JTAG_TMSPS_SD0_CMD||| - || -
|-
|6 4 || JTAG_TCK3.3V||| - || -
|-
|8 5 || JTAG_TDOPS_SD0_CLK||| - || -|-|6, 9, 10, 11, 12 ||DGND||| - || -
|-
|10 7 || JTAG_TDIPS_SD0_DAT0||| - || -
|-
|12 8 || N.C.PS_SD0_DAT1||| - || -
|-
|14 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[DWM_ADD-ON | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 , 2 || 3.3V5V || - || -
|-
|2 3, 4 || 3.3V|| - || -
|-
|35, 116, 17<br> 9, 10,<br>19 || N.C.DGND || - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 207 || DGNDDWM_SD_CMD || - || -
|-
|5 8 || JTAG_TDIDWM_SD_CLK || - || -
|-
|7 11 || JTAG_TMSDWM_SD_DAT0 || - || -
|-
|9 12, 14,<br>16, 18,<br>20, 22 || JTAG_TCKN.C. || - || -
|-
|13 || JTAG_TDODWM_SD_DAT1 || - || -
|-
|15 || JTAG_TRSTnDWM_SD_DAT2 || - || -|-|17 ||DWM_SD_DAT3 || - || -|-|21 ||DWM_UART_RX || - || -|-|23 ||DWM_UART_CTS || - || -|-|24 ||DWM_BT_F5 || - || -|-|25 ||DWM_UART_TX || - || -|-|26 ||DWM_BT_F2 || - || -|-|27 ||DWM_UART_RTS || - || -|-|28 ||DWM_WIFI_IRQ || - || -|-|29 ||DWM_BT_EN || - || -|-|30 ||DWM_WIFI_EN || - || -
|-
|}
<section end=DWM/>
<section begin=== UART1 - J17 ===CAN/>
{| class="wikitable"
!Notes
|-
|1, 6, 4<br>7, 8,<br>9, 10 ||N.C.|| - || -|N.C.-|2, 5 ||CAN_SHIELD || - || -
|-
|23 |UART_EXT_RX|Receive lineCAN_L |Connected to protection diode array| - || -
|-
|34 |UART_EXT_TX|Transmit lineCAN_H |Connected to protection diode array|-|5|DGND|Ground||-|7, 8|N.C.|N.C.|Connected to protection diode array
|-
|}
<section end=CAN/><section begin=Touchscreen/>=== USB OTG Touch screen - J19 J25=== J19 J25 is a standard USB MICRO AB ZIF 4-pin 1.0mm pitch connector. It is connected that connects the touchscreen drive lines to the BORA touch screen controller on the BoORA Xpress USB 2.0 OTG peripheralEVB. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 ||USB_OTG_VBUS TSC_YP || - || -
|-
|2 ||USBM1 TSC_XP || - || -
|-
|3 ||USBP1 TSC_YM || - || -
|-
|4 ||OTG_ID || - || -|-|5 ||USB_OTG_DGND || - || -|-|6, 7, 8, 9 ||USB_OTG_SHIELD TSC_XM || - || -
|-
|}
<section end=Touchscreen/><section begin=LVDS/>=== MicroSD LVDS - J21 J26 === J21 J26 is a microSD memory card connectorvertical double row straight 20-pin 1.25mm pitch header. It is connected This interface shows how to the BORA Xpress SOM through implement a bidirectional 1differential connection to an LCD screen.8VAs known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://3wiki.3V voltageanalog.com/resources/tools-software/linux-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8Vdrivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 , 2 ||PS_SD0_DAT2|3.3V_LCD || - || -
|-
|2 3, 4, 7, 10,<br>13, 16, 19 ||PS_SD0_DAT3DGND ||| - Ground || -
|-
|3 5 ||PS_SD0_CMD|LCD_LVDS_D0- || - || -
|-
|4 6 ||3.3V|LCD_LVDS_D0+ || - || -
|-
|5 8 ||PS_SD0_CLK|LCD_LVDS_D1- || - || -
|-
|6, 9, 10, 11, 12 ||DGND|LCD_LVDS_D1+ || - || -
|-
|7 11 ||PS_SD0_DAT0|LCD_LVDS_D2- || - || -
|-
|8 12 ||PS_SD0_DAT1|LCD_LVDS_D2+ || - || -
|-
|13 14 |3.3V|LCD_LVDS_CLK- || - || ||Pull up to 3.3V with 10K Ohm -
|-
|15 ||LCD_LVDS_CLK+ || - || -|-|17 ||LCD_P17 || - || -|-|18 ||LCD_P18 || - || -|-|20 ||LCD_P20 || - || -|-|21,22 ||DGND || Ground || Shield|-|}<section end=LVDS/><section begin=FMC/>== DWM = FPGA Mezzanine Card (DAVE Wifi/BT moduleFMC) socket Connector - J23 J27 ===J23 J27 is a 52991400 pins ANSI/VITA 57.1-0308 2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector type (30 pins, vertical, 0.50mm picth). This socket connects the At this [[Wireless_Module_(DWM) :File:BoraXEVB-FMC-routing.zip| DWM Wireless Modulelink]] (optional) to a spreadsheet providing the BORA Xpress EVBsame information is available for download. The following table reports the pinout For more information about I/O voltage of the single-ended signals available on FMC connector:, please refer to [[#PL's I/O voltage selections|this section]]. ==== HPC Row A ==== {| class="wikitable"
|-
!Pin#
!Notes
|-
|1, 2 A1||5V DGND|| - GND|| -
|-
|3, 4 A2||3.3V MGTxRXP1|| - DP1_M2C_P|| -
|-
|5, 6,<br> 9, 10,<br>19 A3||DGND MGTxRXN1|| - DP1_M2C_N|| -
|-
|7 A4||DWM_SD_CMD DGND|| - GND|| -
|-
|8 A5||DWM_SD_CLK DGND||GND||| - | A6||MGTxRXP2||DP2_M2C_P|| -
|-
|11 A7||DWM_SD_DAT0 MGTxRXN2|| - DP2_M2C_N|| -
|-
|12, 14,<br>16, 18,<br>20, 22 A8||N.C. DGND|| - GND|| -
|-
|13 A9||DWM_SD_DAT1 DGND|| - GND|| -
|-
|15 A10||DWM_SD_DAT2 MGTxRXP3|| - DP3_M2C_P|| -
|-
|17 A11||DWM_SD_DAT3 MGTxRXN3|| - DP3_M2C_N|| -
|-
|21 A12||DWM_UART_RX DGND|| - GND|| -
|-
|23 A13||DWM_UART_CTS DGND|| - GND|| -
|-
|24 A14||DWM_BT_F5 <span style="color:#ff0000">not connected</span>|| - DP4_M2C_P|| -
|-
|25 A15||DWM_UART_TX <span style="color:#ff0000">not connected</span>|| - DP4_M2C_N|| -
|-
|26 A16||DWM_BT_F2 DGND|| - GND|| -
|-
|27 A17||DWM_UART_RTS DGND|| - GND|| -
|-
|28 A18||DWM_WIFI_IRQ <span style="color:#ff0000">not connected</span>|| - DP5_M2C_P|| -
|-
|29 A19||DWM_BT_EN <span style="color:#ff0000">not connected</span>|| - DP5_M2C_N|| -
|-
|30 A20||DWM_WIFI_EN DGND|| - GND|| -
|-
|} === CAN - J24 ===J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector: {A21||DGND||GND|| class="wikitable"
|-
|-
|1, 6,<br>7, 8,<br>9, 10 A23||N.C. MGTxTXN1|| - DP1_C2M_N|| -
|-
|2, 5 A24||CAN_SHIELD DGND|| - GND|| -
|-
|3 A25||CAN_L DGND|| - GND|| -
|-
|4 A26||CAN_H MGTxTXP2|| - DP2_C2M_P|| -
|-
|} === Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector: {A27||MGTxTXN2||DP2_C2M_N|| class="wikitable"
|-
|-
|1 A29||TSC_YP DGND||GND||| - | A30||MGTxTXP3||DP3_C2M_P||| -| A31||MGTxTXN3||DP3_C2M_N|||-| A32||DGND||GND|||-| A33||DGND||GND|||-| A34||<span style="color:#ff0000">not connected</span>||DP4_C2M_P|||-| A35||<span style="color:#ff0000">not connected</span>||DP4_C2M_N|||-| A36||DGND||GND||
|-
|2 A37||TSC_XP DGND|| - GND|| -
|-
|3 A38||TSC_YM <span style="color:#ff0000">not connected</span>|| - DP5_C2M_P|| -
|-
|4 A39||TSC_XM <span style="color:#ff0000">not connected</span>|| - DP5_C2M_N|| -
|-
| A40||DGND||GND||
|}
=== LVDS - J26 = HPC Row B ====J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2 B1||3.3V_LCD RSVD|| - RES1|| -
|-
|3, 4, 7, 10,<br>13, 16, 19 B2||DGND || Ground GND|| -
|-
|5 B3||LCD_LVDS_D0- DGND|| - GND|| -
|-
|6 B4||LCD_LVDS_D0+ <span style="color:#ff0000">not connected</span>||DP9_M2C_P||| - |B5||<span style="color:#ff0000">not connected</span>||DP9_M2C_N||| -| B6||DGND||GND|||-| B7||DGND||GND||
|-
|8 B8||LCD_LVDS_D1- <span style="color:#ff0000">not connected</span>|| - DP8_M2C_P|| -
|-
|9 B9||LCD_LVDS_D1+ <span style="color:#ff0000">not connected</span>|| - DP8_M2C_N|| -
|-
|11 B10||LCD_LVDS_D2- DGND|| - GND|| -
|-
|12 B11||LCD_LVDS_D2+ DGND|| - GND|| -
|-
|15 B12||LCD_LVDS_CLK+ <span style="color:#ff0000">not connected</span>|| - DP7_M2C_P|| -
|-
|17 B13||LCD_P17 <span style="color:#ff0000">not connected</span>|| - DP7_M2C_N|| -
|-
|18 B14||LCD_P18 DGND|| - GND|| -
|-
|20 B15||LCD_P20 DGND|| - GND|| -
|-
|21,22 B16||DGND <span style="color:#ff0000">not connected</span>|| Ground DP6_M2C_P|| Shield
|-
|} B17||<span style=== FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is"color:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is #ff0000">not fully populated. The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipconnected</span>||DP6_M2C_N|link]] a spreadsheet providing the same information is available for download. ==== HPC Row A ==== {| class="wikitable"
|-
|-
| A1B19||DGND||GND||
|-
| A2B20||MGTxRXP1MGTREFCLK1P||DP1_M2C_PGBTCLK1_M2C_P||
|-
| A3B21||MGTxRXN1MGTREFCLK1N||DP1_M2C_NGBTCLK1_M2C_N||
|-
| A4B22||DGND||GND||
|-
| A5B23||DGND||GND||
|-
| A6B24||MGTxRXP2<span style="color:#ff0000">not connected</span>||DP2_M2C_PDP9_C2M_P||
|-
| A7B25||MGTxRXN2<span style="color:#ff0000">not connected</span>||DP2_M2C_NDP9_C2M_N||
|-
| A8B26||DGND||GND||
|-
| A9B27||DGND||GND||
|-
| A10B28||MGTxRXP3<span style="color:#ff0000">not connected</span>||DP3_M2C_PDP8_C2M_P||
|-
| A11B29||MGTxRXN3<span style="color:#ff0000">not connected</span>||DP3_M2C_NDP8_C2M_N||
|-
| A12B30||DGND||GND||
|-
| A13B31||DGND||GND||
|-
| A14B32||<span style="color:#ff0000">not connected</span>||DP4_M2C_PDP7_C2M_P||
|-
| A15B33||<span style="color:#ff0000">not connected</span>||DP4_M2C_NDP7_C2M_N||
|-
| A16B34||DGND||GND||
|-
| A17B35||DGND||GND||
|-
| A18B36||<span style="color:#ff0000">not connected</span>||DP5_M2C_PDP6_C2M_P||
|-
| A19B37||<span style="color:#ff0000">not connected</span>||DP5_M2C_NDP6_C2M_N||
|-
| A20B38||DGND||GND||
|-
| A21B39||DGND||GND||
|-
| A22B40||MGTxTXP1RSVD||DP1_C2M_PRES0|||} ==== LPC Row C ==== {| class="wikitable"
|-
|-
| A24C1||DGND||GND||
|-
| A25C2||DGNDMGTxTXP0||GNDDP0_C2M_P||
|-
| A26C3||MGTxTXP2MGTxTXN0||DP2_C2M_PDP0_C2M_N||
|-
| A27C4||MGTxTXN2DGND||DP2_C2M_NGND||
|-
| A28C5||DGND||GND||
|-
| A29C6||DGNDMGTxRXP0||GNDDP0_M2C_P||
|-
| A30C7||MGTxTXP3MGTxRXN0||DP3_C2M_PDP0_M2C_N||
|-
| A31C8||MGTxTXN3DGND||DP3_C2M_NGND||
|-
| A32C9||DGND||GND||
|-
| A33C10||DGNDIO_L23P_T3_34||GNDLA06_P||
|-
| A34C11||<span style="color:#ff0000">not connected</span>IO_L23N_T3_34||DP4_C2M_PLA06_N||
|-
| A35C12||<span style="color:#ff0000">not connected</span>DGND||DP4_C2M_NGND||
|-
| A36C13||DGND||GND||
|-
| A37C14||DGNDIO_L2P_T0_34||GNDLA10_P||
|-
| A38C15||<span style="color:#ff0000">not connected</span>IO_L2N_T0_34||DP5_C2M_PLA10_N||
|-
| A39C16||<span style="color:#ff0000">not connected</span>DGND||DP5_C2M_NGND||
|-
| A40C17||DGND||GND|||} ==== HPC Row B ==== {| class="wikitable"
|-
|-
| B1C19||RSVDIO_L1N_T0_34||RES1LA14_N||
|-
| B2C20||DGND||GND||
|-
| B3C21||DGND||GND||
|-
| B4C22||<span style="color:#ff0000">not connected</span>IO_L16P_T2_34||DP9_M2C_PLA18_P_CC||
|-
| B5C23||<span style="color:#ff0000">not connected</span>IO_L16N_T2_34||DP9_M2C_NLA18_N_CC||
|-
| B6C24||DGND||GND||
|-
| B7C25||DGND||GND||
|-
| B8C26||<span style="color:#ff0000">not connected</span>IO_L6P_T0_35||DP8_M2C_PLA27_P||
|-
| B9C27||<span style="color:#ff0000">not connected</span>IO_L6N_T0_VREF_35||DP8_M2C_NLA27_N||
|-
| B10C28||DGND||GND||
|-
| B11C29||DGND||GND||
|-
| B12C30||<span style="color:#ff0000">not connected</span>I2C0_SCL||DP7_M2C_PSCL||
|-
| B13C31||<span style="color:#ff0000">not connected</span>I2C0_SDA||DP7_M2C_NSDA||
|-
| B14C32||DGND||GND||
|-
| B15C33||DGND||GND||
|-
| B16C34||<span style="color:#ff0000">not connected</span>GA0||DP6_M2C_PGA0||
|-
| B17C35||<span style="color:#ff0000">not connected</span>FMC_12P0V||DP6_M2C_N12P0V||
|-
| B18C36||DGND||GND||
|-
| B19C37||DGNDFMC_12P0V||GND12P0V||
|-
| B20C38||MGTREFCLK1PDGND||GBTCLK1_M2C_PGND||
|-
| B21C39||MGTREFCLK1NFMC_3P3V||GBTCLK1_M2C_N3P3V||
|-
| B22C40||DGND||GND|||} ==== LPC Row D ==== {| class="wikitable"
|-
|-
| B24D1||<span style="color:#ff0000">not connected</span>IO_25_VRP_34||DP9_C2M_PPG_C2M||
|-
| B25D2||<span style="color:#ff0000">not connected</span>DGND||DP9_C2M_NGND||
|-
| B26D3||DGND||GND||
|-
| B27D4||DGNDMGTREFCLK0P||GNDGBTCLK0_M2C_P||
|-
| B28D5||<span style="color:#ff0000">not connected</span>MGTREFCLK0N||DP8_C2M_PGBTCLK0_M2C_N||
|-
| B29D6||<span style="color:#ff0000">not connected</span>DGND||DP8_C2M_NGND||
|-
| B30D7||DGND||GND||
|-
| B31D8||DGNDIO_L14P_T2_SRCC_34||GNDLA01_P_CC||
|-
| B32D9||<span style="color:#ff0000">not connected</span>IO_L14N_T2_SRCC_34||DP7_C2M_PLA01_N_CC||
|-
| B33D10||<span style="color:#ff0000">not connected</span>DGND||DP7_C2M_NGND||
|-
| B34D11||DGNDIO_L9P_T1_DQS_34||GNDLA05_P||
|-
| B35D12||DGNDIO_L9N_T1_DQS_34||GNDLA05_N||
|-
| B36D13||<span style="color:#ff0000">not connected</span>DGND||DP6_C2M_PGND||
|-
| B37D14||<span style="color:#ff0000">not connected</span>IO_L6P_T0_34||DP6_C2M_NLA09_P||
|-
| B38D15||DGNDIO_L6N_T0_VREF_34||GNDLA09_N||
|-
| B39D16||DGND||GND||
|-
| B40D17||RSVDIO_L20P_T3_34||RES0LA13_P|||} ==== LPC Row C ==== {| class="wikitable"
|-
|-
| C1D19||DGND||GND||
|-
| C2D20||MGTxTXP0IO_L15P_T2_DQS_34||DP0_C2M_PLA17_P_CC||
|-
| C3D21||MGTxTXN0IO_L15N_T2_DQS_34||DP0_C2M_NLA17_N_CC||
|-
| C4D22||DGND||GND||
|-
| C5D23||DGNDIO_L2P_T0_AD8P_35||GNDLA23_P||
|-
| C6D24||MGTxRXP0IO_L2N_T0_AD8N_35||DP0_M2C_PLA23_N||
|-
| C7D25||MGTxRXN0DGND||DP0_M2C_NGND||
|-
| C8D26||DGNDIO_L5P_T0_AD9P_35||GNDLA26_P||
|-
| C9D27||DGNDIO_L5N_T0_AD9N_35||GNDLA26_N||
|-
| C10D28||IO_L23P_T3_34DGND||LA06_PGND||
|-
| C11D29||IO_L23N_T3_34JTAG_TCK||LA06_NTCK||
|-
| C12D30||DGNDJTAG_TDI||GNDTDI||
|-
| C13D31||DGNDFMC_TDO_ZYNQ_TDI||GNDTDO||
|-
| C14D32||IO_L2P_T0_34FMC_3P3VAUX||LA10_P3P3VAUX||
|-
| C15D33||IO_L2N_T0_34JTAG_TMS||LA10_NTMS||
|-
| C16D34||DGNDJTAG_TRSTn||GNDTRST_L||
|-
| C17D35||DGNDGA0||GNDGA1||
|-
| C18D36||IO_L1P_T0_34FMC_3P3V||LA14_P3P3V||
|-
| C19D37||IO_L1N_T0_34DGND||LA14_NGND||
|-
| C20D38||DGNDFMC_3P3V||GND3P3V||
|-
| C21D39||DGND||GND||
|-
| C22D40||IO_L16P_T2_34FMC_3P3V||LA18_P_CC3P3V|||-} ==== HPC Row E ==== {| C23||IO_L16N_T2_34||LA18_N_CC||class="wikitable"
|-
|-
| C25E1||DGND||GND||
|-
| C26E2||IO_L6P_T0_35IO_L14P_T2_AD4P_SRCC_35||LA27_PHA01_P_CC||
|-
| C27E3||IO_L6N_T0_VREF_35IO_L14N_T2_AD4N_SRCC_35||LA27_NHA01_N_CC||
|-
| C28E4||DGND||GND||
|-
| C29E5||DGND||GND||
|-
| C30E6||I2C0_SCLIO_L20P_T3_AD6P_35||SCLHA05_P||
|-
| C31E7||I2C0_SDAIO_L20N_T3_AD6N_35||SDAHA05_N||
|-
| C32E8||DGND||GND||
|-
| C33E9||DGNDIO_L24P_T3_AD15P_35||GNDHA09_P||
|-
| C34E10||GA0IO_L24N_T3_AD15N_35||GA0HA09_N||
|-
| C35E11||FMC_12P0VDGND||12P0VGND||
|-
| C36E12||DGND<span style="color:#ff0000">not connected</span>||GNDHA13_P||
|-
| C37E13||FMC_12P0V<span style="color:#ff0000">not connected</span>||12P0VHA13_N||
|-
| C38E14||DGND||GND||
|-
| C39E15||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHA16_P||
|-
| C40E16||DGND||GND<span style="color:#ff0000">not connected</span>||HA16_N|} ==== LPC Row D ==== {| class="wikitable"
|-
|-
| D1E18||IO_25_VRP_34<span style="color:#ff0000">not connected</span>||PG_C2MHA20_P||
|-
| D2E19||DGND<span style="color:#ff0000">not connected</span>||GNDHA20_N||
|-
| D3E20||DGND||GND||
|-
| D4E21||MGTREFCLK0P<span style="color:#ff0000">not connected</span>||GBTCLK0_M2C_PHB03_P||
|-
| D5E22||MGTREFCLK0N<span style="color:#ff0000">not connected</span>||GBTCLK0_M2C_NHB03_N||
|-
| D6E23||DGND||GND||
|-
| D7E24||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_P||
|-
| D8E25||IO_L14P_T2_SRCC_34<span style="color:#ff0000">not connected</span>||LA01_P_CCHB05_N||
|-
| D9E26||IO_L14N_T2_SRCC_34DGND||LA01_N_CCGND||
|-
| D10E27||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_P||
|-
| D11E28||IO_L9P_T1_DQS_34<span style="color:#ff0000">not connected</span>||LA05_PHB09_N||
|-
| D12E29||IO_L9N_T1_DQS_34DGND||LA05_NGND||
|-
| D13E30||DGND<span style="color:#ff0000">not connected</span>||GNDHB13_P||
|-
| D14E31||IO_L6P_T0_34<span style="color:#ff0000">not connected</span>||LA09_PHB13_N||
|-
| D15E32||IO_L6N_T0_VREF_34DGND||LA09_NGND||
|-
| D16E33||DGND<span style="color:#ff0000">not connected</span>||GNDHB19_P||
|-
| D17E34||IO_L20P_T3_34<span style="color:#ff0000">not connected</span>||LA13_PHB19_N||
|-
| D18E35||IO_L20N_T3_34DGND||LA13_NGND||
|-
| D19E36||DGND<span style="color:#ff0000">not connected</span>||GNDHB21_P||
|-
| D20E37||IO_L15P_T2_DQS_34<span style="color:#ff0000">not connected</span>||LA17_P_CCHB21_N||
|-
| D21E38||IO_L15N_T2_DQS_34DGND||LA17_N_CCGND||
|-
| D22E39||DGNDFMC_VADJ||GNDVADJ||
|-
| D23E40||IO_L2P_T0_AD8P_35DGND||LA23_PGND|||} ==== HPC Row F ==== {| class="wikitable"
|-
|-
| D25F1||DGNDIO_0_VRN_35||GNDPG_M2C||
|-
| D26F2||IO_L5P_T0_AD9P_35DGND||LA26_PGND||
|-
| D27F3||IO_L5N_T0_AD9N_35DGND||LA26_NGND||
|-
| D28F4||DGNDIO_L13P_T2_MRCC_35||GNDHA00_P_CC||
|-
| D29F5||JTAG_TCKIO_L13N_T2_MRCC_35||TCKHA00_N_CC||
|-
| D30F6||JTAG_TDIDGND||TDIGND||
|-
| D31F7||FMC_TDO_ZYNQ_TDIIO_L19P_T3_35||TDOHA04_P||
|-
| D32F8||FMC_3P3VAUXIO_L19N_T3_VREF_35||3P3VAUXHA04_N||
|-
| D33F9||JTAG_TMSDGND||TMSGND||
|-
| D34F10||JTAG_TRSTnIO_L23P_T3_35||TRST_LHA08_P||
|-
| D35F11||GA0IO_L23N_T3_35||GA1HA08_N||
|-
| D36F12||FMC_3P3VDGND||3P3VGND||
|-
| D37F13||DGND<span style="color:#ff0000">not connected</span>||GNDHA12_P||
|-
| D38F14||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHA12_N||
|-
| D39F15||DGND||GND||
|-
| D40F16||FMC_3P3V||3P3V<span style="color:#ff0000">not connected</span>||HA15_P|} ==== HPC Row E ==== {| class="wikitable"
|-
|-
| E1F18||DGND||GND||
|-
| E2F19||IO_L14P_T2_AD4P_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_P_CCHA19_P||
|-
| E3F20||IO_L14N_T2_AD4N_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_N_CCHA19_N||
|-
| E4F21||DGND||GND||
|-
| E5F22||DGND<span style="color:#ff0000">not connected</span>||GNDHB02_P||
|-
| E6F23||IO_L20P_T3_AD6P_35<span style="color:#ff0000">not connected</span>||HA05_PHB02_N||
|-
| E7F24||IO_L20N_T3_AD6N_35DGND||HA05_NGND||
|-
| E8F25||DGND<span style="color:#ff0000">not connected</span>||GNDHB04_P||
|-
| E9F26||IO_L24P_T3_AD15P_35<span style="color:#ff0000">not connected</span>||HA09_PHB04_N||
|-
| E10F27||IO_L24N_T3_AD15N_35DGND||HA09_NGND||
|-
| E11F28||DGND<span style="color:#ff0000">not connected</span>||GNDHB08_P||
|-
| E12F29||<span style="color:#ff0000">not connected</span>||HA13_PHB08_N||
|-
| E13F30||<span style="color:#ff0000">not connected</span>DGND||HA13_NGND||
|-
| E14F31||DGND<span style="color:#ff0000">not connected</span>||GNDHB12_P||
|-
| E15F32||<span style="color:#ff0000">not connected</span>||HA16_PHB12_N||
|-
| E16F33||<span style="color:#ff0000">not connected</span>DGND||HA16_NGND||
|-
| E17F34||DGND<span style="color:#ff0000">not connected</span>||GNDHB16_P||
|-
| E18F35||<span style="color:#ff0000">not connected</span>||HA20_PHB16_N||
|-
| E19F36||<span style="color:#ff0000">not connected</span>DGND||HA20_NGND||
|-
| E20F37||DGND<span style="color:#ff0000">not connected</span>||GNDHB20_P||
|-
| E21F38||<span style="color:#ff0000">not connected</span>||HB03_PHB20_N||
|-
| E22F39||<span style="color:#ff0000">not connected</span>DGND||HB03_NGND||
|-
| E23F40||DGNDFMC_VADJ||GNDVADJ|||} ==== LPC Row G ==== {| class="wikitable"
|-
|-
| E25G1||<span style="color:#ff0000">not connected</span>DGND||HB05_NGND||
|-
| E26G2||DGNDIO_L11P_T1_SRCC_34||GNDCLK0_C2M_P||
|-
| E27G3||<span style="color:#ff0000">not connected</span>IO_L11N_T1_SRCC_34||HB09_PCLK0_C2M_N||
|-
| E28G4||<span style="color:#ff0000">not connected</span>DGND||HB09_NGND||
|-
| E29G5||DGND||GND||
|-
| E30G6||<span style="color:#ff0000">not connected</span>IO_L13P_T1_MRCC_34||HB13_PLA00_P_CC||
|-
| E31G7||<span style="color:#ff0000">not connected</span>IO_L13N_T1_MRCC_34||HB13_NLA00_N_CC||
|-
| E32G8||DGND||GND||
|-
| E33G9||<span style="color:#ff0000">not connected</span>IO_L4P_T0_34||HB19_PLA03_P||
|-
| E34G10||<span style="color:#ff0000">not connected</span>IO_L4N_T0_34||HB19_NLA03_N||
|-
| E35G11||DGND||GND||
|-
| E36G12||<span style="color:#ff0000">not connected</span>IO_L3P_T0_DQS_PUDC_B_34||HB21_PLA08_P||
|-
| E37G13||<span style="color:#ff0000">not connected</span>IO_L3N_T0_DQS_34||HB21_NLA08_N||
|-
| E38G14||DGND||GND||
|-
| E39G15||FMC_VADJIO_L22P_T3_34||VADJLA12_P||
|-
| E40G16||DGNDIO_L22N_T3_34||GNDLA12_N|||} ==== HPC Row F ==== {| class="wikitable"
|-
|-
| F1G18||IO_0_VRN_35IO_L19P_T3_34||PG_M2CLA16_P||
|-
| F2G19||DGNDIO_L19N_T3_VREF_34||GNDLA16_N||
|-
| F3G20||DGND||GND||
|-
| F4G21||IO_L13P_T2_MRCC_35IO_L17P_T2_34||HA00_P_CCLA20_P||
|-
| F5G22||IO_L13N_T2_MRCC_35IO_L17N_T2_34||HA00_N_CCLA20_N||
|-
| F6G23||DGND||GND||
|-
| F7G24||IO_L19P_T3_35IO_L1P_T0_AD0P_35||HA04_PLA22_P||
|-
| F8G25||IO_L19N_T3_VREF_35IO_L1N_T0_AD0N_35||HA04_NLA22_N||
|-
| F9G26||DGND||GND||
|-
| F10G27||IO_L23P_T3_35IO_L4P_T0_35||HA08_PLA25_P||
|-
| F11G28||IO_L23N_T3_35IO_L4N_T0_35||HA08_NLA25_N||
|-
| F12G29||DGND||GND||
|-
| F13G30||<span style="color:#ff0000">not connected</span>IO_L8P_T1_AD10P_35||HA12_PLA29_P||
|-
| F14G31||<span style="color:#ff0000">not connected</span>IO_L8N_T1_AD10N_35||HA12_NLA29_N||
|-
| F15G32||DGND||GND||
|-
| F16G33||<span style="color:#ff0000">not connected</span>IO_L10P_T1_AD11P_35||HA15_PLA31_P||
|-
| F17G34||<span style="color:#ff0000">not connected</span>IO_L10N_T1_AD11N_35||HA15_NLA31_N||
|-
| F18G35||DGND||GND||
|-
| F19G36||<span style="color:#ff0000">not connected</span>IO_L16P_T2_35||HA19_PLA33_P||
|-
| F20G37||<span style="color:#ff0000">not connected</span>IO_L16N_T2_35||HA19_NLA33_N||
|-
| F21G38||DGND||GND||
|-
| F22G39||<span style="color:#ff0000">not connected</span>FMC_VADJ||HB02_PVADJ||
|-
| F23G40||<span style="color:#ff0000">not connected</span>DGND||GND||HB02_N|} ==== LPC Row H ==== {|class="wikitable"
|-
|-
| F25H1||<span style="color:#ff0000">not connected</span>FMC_VREF_A_M2C||HB04_PVREF_A_M2C||
|-
| F26H2||<span style="color:#ff0000">not connected</span>FMC_PRSNT_M2C_L||HB04_NPRSNT_M2C_L||
|-
| F27H3||DGND||GND||
|-
| F28H4||<span style="color:#ff0000">not connected</span>IO_L12P_T1_MRCC_34||HB08_PCLK0_M2C_P||
|-
| F29H5||<span style="color:#ff0000">not connected</span>IO_L12N_T1_MRCC_34||HB08_NCLK0_M2C_N||
|-
| F30H6||DGND||GND||
|-
| F31H7||<span style="color:#ff0000">not connected</span>IO_L7P_T1_34||HB12_PLA02_P||
|-
| F32H8||<span style="color:#ff0000">not connected</span>IO_L7N_T1_34||HB12_NLA02_N||
|-
| F33H9||DGND||GND||
|-
| F34H10||<span style="color:#ff0000">not connected</span>IO_L5P_T0_34||HB16_PLA04_P||
|-
| F35H11||<span style="color:#ff0000">not connected</span>IO_L5N_T0_34||HB16_NLA04_N||
|-
| F36H12||DGND||GND||
|-
| F37H13||<span style="color:#ff0000">not connected</span>IO_L8P_T1_34||HB20_PLA07_P||
|-
| F38H14||<span style="color:#ff0000">not connected</span>IO_L8N_T1_34||HB20_NLA07_N||
|-
| F39H15||DGND||GND||
|-
| F40H16||FMC_VADJIO_L21P_T3_DQS_34||VADJLA11_P|||} ==== LPC Row G ==== {| class="wikitable"
|-
|-
| G1H18||DGND||GND||
|-
| G2H19||IO_L11P_T1_SRCC_34IO_L18P_T2_34||CLK0_C2M_PLA15_P||
|-
| G3H20||IO_L11N_T1_SRCC_34IO_L18N_T2_34||CLK0_C2M_NLA15_N||
|-
| G4H21||DGND||GND||
|-
| G5H22||DGNDIO_L24P_T3_34||GNDLA19_P||
|-
| G6H23||IO_L13P_T1_MRCC_34IO_L24N_T3_34||LA00_P_CCLA19_N||
|-
| G7H24||IO_L13N_T1_MRCC_34DGND||LA00_N_CCGND||
|-
| G8H25||DGNDIO_L10P_T1_34||GNDLA21_P||
|-
| G9H26||IO_L4P_T0_34IO_L10N_T1_34||LA03_PLA21_N||
|-
| G10H27||IO_L4N_T0_34DGND||LA03_NGND||
|-
| G11H28||DGNDIO_L3P_T0_DQS_AD1P_35||GNDLA24_P||
|-
| G12H29||IO_L3P_T0_DQS_PUDC_B_34IO_L3N_T0_DQS_AD1N_35||LA08_PLA24_N||
|-
| G13H30||IO_L3N_T0_DQS_34DGND||LA08_NGND||
|-
| G14H31||DGNDIO_L7P_T1_AD2P_35||GNDLA28_P||
|-
| G15H32||IO_L22P_T3_34IO_L7N_T1_AD2N_35||LA12_PLA28_N||
|-
| G16H33||IO_L22N_T3_34DGND||LA12_NGND||
|-
| G17H34||DGNDIO_L9P_T1_DQS_AD3P_35||GNDLA30_P||
|-
| G18H35||IO_L19P_T3_34IO_L9N_T1_DQS_AD3N_35||LA16_PLA30_N||
|-
| G19H36||IO_L19N_T3_VREF_34DGND||LA16_NGND||
|-
| G20H37||DGNDIO_L15P_T2_DQS_AD12P_35||GNDLA32_P||
|-
| G21H38||IO_L17P_T2_34IO_L15N_T2_DQS_AD12N_35||LA20_PLA32_N||
|-
| G22H39||IO_L17N_T2_34DGND||LA20_NGND||
|-
| G23H40||DGNDFMC_VADJ||GNDVADJ|||} ==== HPC Row J ==== {| class="wikitable"
|-
|-
| G25J1||IO_L1N_T0_AD0N_35DGND||LA22_NGND||
|-
| G26J2||DGNDIO_L11P_T1_SRCC_35||GNDCLK1_C2M_P||
|-
| G27J3||IO_L4P_T0_35IO_L11N_T1_SRCC_35||LA25_PCLK1_C2M_N||
|-
| G28J4||IO_L4N_T0_35DGND||LA25_NGND||
|-
| G29J5||DGND||GND||
|-
| G30J6||IO_L8P_T1_AD10P_35IO_L18P_T2_AD13P_35||LA29_PHA03_P||
|-
| G31J7||IO_L8N_T1_AD10N_35IO_L18N_T2_AD13N_35||LA29_NHA03_N||
|-
| G32J8||DGND||GND||
|-
| G33J9||IO_L10P_T1_AD11P_35IO_L22P_T3_AD7P_35||LA31_PHA07_P||
|-
| G34J10||IO_L10N_T1_AD11N_35IO_L22N_T3_AD7N_35||LA31_NHA07_N||
|-
| G35J11||DGND||GND||
|-
| G36J12||IO_L16P_T2_35<span style="color:#ff0000">not connected</span>||LA33_PHA11_P||
|-
| G37J13||IO_L16N_T2_35<span style="color:#ff0000">not connected</span>||LA33_NHA11_N||
|-
| G38J14||DGND||GND||
|-
| G39J15||FMC_VADJ<span style="color:#ff0000">not connected</span>||VADJHA14_P||
|-
| G40J16||DGND||GND<span style="color:#ff0000">not connected</span>||HA14_N|} ==== LPC Row H ==== {| class="wikitable"
|-
|-
| H1J18||FMC_VREF_A_M2C<span style="color:#ff0000">not connected</span>||VREF_A_M2CHA18_P||
|-
| H2J19||FMC_PRSNT_M2C_L<span style="color:#ff0000">not connected</span>||PRSNT_M2C_LHA18_N||
|-
| H3J20||DGND||GND||
|-
| H4J21||IO_L12P_T1_MRCC_34<span style="color:#ff0000">not connected</span>||CLK0_M2C_PHA22_P||
|-
| H5J22||IO_L12N_T1_MRCC_34<span style="color:#ff0000">not connected</span>||CLK0_M2C_NHA22_N||
|-
| H6J23||DGND||GND||
|-
| H7J24||IO_L7P_T1_34<span style="color:#ff0000">not connected</span>||LA02_PHB01_P||
|-
| H8J25||IO_L7N_T1_34<span style="color:#ff0000">not connected</span>||LA02_NHB01_N||
|-
| H9J26||DGND||GND||
|-
| H10J27||IO_L5P_T0_34<span style="color:#ff0000">not connected</span>||LA04_PHB07_P||
|-
| H11J28||IO_L5N_T0_34<span style="color:#ff0000">not connected</span>||LA04_NHB07_N||
|-
| H12J29||DGND||GND||
|-
| H13J30||IO_L8P_T1_34<span style="color:#ff0000">not connected</span>||LA07_PHB11_P||
|-
| H14J31||IO_L8N_T1_34<span style="color:#ff0000">not connected</span>||LA07_NHB11_N||
|-
| H15J32||DGND||GND||
|-
| H16J33||IO_L21P_T3_DQS_34<span style="color:#ff0000">not connected</span>||LA11_PHB15_P||
|-
| H17J34||IO_L21N_T3_DQS_34<span style="color:#ff0000">not connected</span>||LA11_NHB15_N||
|-
| H18J35||DGND||GND||
|-
| H19J36||IO_L18P_T2_34<span style="color:#ff0000">not connected</span>||LA15_PHB18_P||
|-
| H20J37||IO_L18N_T2_34<span style="color:#ff0000">not connected</span>||LA15_NHB18_N||
|-
| H21J38||DGND||GND||
|-
| H22J39||IO_L24P_T3_34<span style="color:#ff0000">not connected</span>||LA19_PVIO_B_M2C||
|-
| H23J40||IO_L24N_T3_34DGND||LA19_NGND|||} ==== HPC Row K ==== {| class="wikitable"
|-
|-
| H25K1||IO_L10P_T1_34<span style="color:#ff0000">not connected</span>||LA21_PVREF_B_M2C||
|-
| H26K2||IO_L10N_T1_34DGND||LA21_NGND||
|-
| H27K3||DGND||GND||
|-
| H28K4||IO_L3P_T0_DQS_AD1P_35IO_L12P_T1_MRCC_35||LA24_PCLK1_M2C_P||
|-
| H29K5||IO_L3N_T0_DQS_AD1N_35IO_L12N_T1_MRCC_35||LA24_NCLK1_M2C_N||
|-
| H30K6||DGND||GND||
|-
| H31K7||IO_L7P_T1_AD2P_35IO_L17P_T2_AD5P_35||LA28_PHA02_P||
|-
| H32K8||IO_L7N_T1_AD2N_35IO_L17N_T2_AD5N_35||LA28_NHA02_N||
|-
| H33K9||DGND||GND||
|-
| H34K10||IO_L9P_T1_DQS_AD3P_35IO_L21P_T3_DQS_AD14P_35||LA30_PHA06_P||
|-
| H35K11||IO_L9N_T1_DQS_AD3N_35IO_L21N_T3_DQS_AD14N_35||LA30_NHA06_N||
|-
| H36K12||DGND||GND||
|-
| H37K13||IO_L15P_T2_DQS_AD12P_35IO_25_VRP_35||LA32_PHA10_P||
|-
| H38K14||IO_L15N_T2_DQS_AD12N_35<span style="color:#ff0000">not connected</span>||LA32_NHA10_N||
|-
| H39K15||DGND||GND||
|-
| H40K16||FMC_VADJ||VADJ<span style="color:#ff0000">not connected</span>||HA17_P_CC|} ==== HPC Row J ==== {| class="wikitable"
|-
|-
| J1K18||DGND||GND||
|-
| J2K19||IO_L11P_T1_SRCC_35<span style="color:#ff0000">not connected</span>||CLK1_C2M_PHA21_P||
|-
| J3K20||IO_L11N_T1_SRCC_35<span style="color:#ff0000">not connected</span>||CLK1_C2M_NHA21_N||
|-
| J4K21||DGND||GND||
|-
| J5K22||DGND<span style="color:#ff0000">not connected</span>||GNDHA23_P||
|-
| J6K23||IO_L18P_T2_AD13P_35<span style="color:#ff0000">not connected</span>||HA03_PHA23_N||
|-
| J7K24||IO_L18N_T2_AD13N_35DGND||HA03_NGND||
|-
| J8K25||DGND<span style="color:#ff0000">not connected</span>||GNDHB00_P_CC||
|-
| J9K26||IO_L22P_T3_AD7P_35<span style="color:#ff0000">not connected</span>||HA07_PHB00_N_CC||
|-
| J10K27||IO_L22N_T3_AD7N_35DGND||HA07_NGND||
|-
| J11K28||DGND<span style="color:#ff0000">not connected</span>||GNDHB06_P_CC||
|-
| J12K29||<span style="color:#ff0000">not connected</span>||HA11_PHB06_N_CC||
|-
| J13K30||<span style="color:#ff0000">not connected</span>DGND||HA11_NGND||
|-
| J14K31||DGND<span style="color:#ff0000">not connected</span>||GNDHB10_P||
|-
| J15K32||<span style="color:#ff0000">not connected</span>||HA14_PHB10_N||
|-
| J16K33||<span style="color:#ff0000">not connected</span>DGND||HA14_NGND||
|-
| J17K34||DGND<span style="color:#ff0000">not connected</span>||GNDHB14_P||
|-
| J18K35||<span style="color:#ff0000">not connected</span>||HA18_PHB14_N||
|-
| J19K36||<span style="color:#ff0000">not connected</span>DGND||HA18_NGND||
|-
| J20K37||DGND<span style="color:#ff0000">not connected</span>||GNDHB17_P_CC||
|-
| J21K38||<span style="color:#ff0000">not connected</span>||HA22_PHB17_N_CC||
|-
| J22K39||<span style="color:#ff0000">not connected</span>DGND||HA22_NGND||
|-
| J23K40||DGND<span style="color:#ff0000">not connected</span>||GNDVIO_B_M2C|||}<section end=FMC/><section begin=PinStrip/>=== Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
|-
| J251, 4, 9, 12 ||<span style="color:#ff0000">not connected</span>DGND ||HB01_NGround ||-
|-
| J262 ||DGNDSPI0_CS0n ||GND- ||-
|-
| J273 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_SCLK/span>NAND_IO1 ||HB07_P- ||-
|-
| J285 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ0/span>NAND_ALE ||HB07_N- ||-
|-
| J296 ||DGNDNAND_CS0/SPI0_CS1 ||GND- ||-
|-
| J307 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ2/span>NAND_IO2 ||HB11_P- ||-
|-
| J318 ||<span style="color:#ff0000">not connected<ZYNQ_SPI0_DQ1/span>NAND_WE ||HB11_N- ||-
|-
| J3210 ||DGNDZYNQ_SPI0_DQ3/NAND_IO0 ||GND- ||-
|-
| J3311 ||<span style="color:#ff0000">not connected</span>ZYNQ_NAND_RD_B ||HB15_P|||-| J34||<span style="color:#ff0000">not connected</span>||HB15_N|||-| J35||DGND||GND|||-| J36||<span style="color:#ff0000">not connected</span>||HB18_P|||-| J37||<span style="color:#ff0000">not connected</span>||HB18_N|||-| J38||DGND||GND|||-| J39||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|-
|}
==== HPC Row K Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
| K11 ||<span style="color:#ff0000">not connected</span>MON_VCCPLL ||VREF_B_M2C- ||-
|-
| K22 ||DGNDMON_3.3V ||GND- ||-
|-
| K33 ||DGNDMON_XADC_VCC ||GND- ||-
|-
| K44 ||IO_L12P_T1_MRCC_35MON_1V2_ETH ||CLK1_M2C_P- ||-
|-
| K55 ||IO_L12N_T1_MRCC_35MON_FPGA_VDDIO_BANK35 ||CLK1_M2C_N- ||-
|-
| K66 ||DGNDMON_VDDQ_1V5 ||GND- ||-
|-
| K77 ||IO_L17P_T2_AD5P_35MON_FPGA_VDDIO_BANK34 ||HA02_P- ||-
|-
| K88 ||IO_L17N_T2_AD5N_35MON_1.8V ||HA02_N- ||-
|-
| K99 ||DGNDMON_FPGA_VDDIO_BANK13 ||GND- ||-
|-
| K1010 ||IO_L21P_T3_DQS_AD14P_35MON_1.0V ||HA06_P- ||-
|-
| K1111 ||IO_L21N_T3_DQS_AD14N_35MON_1.8V_IO ||HA06_N- ||-
|-
| K1212 ||DGNDMON_MGTAVCC ||GND- ||-
|-
| K1313 ||IO_25_VRP_35MON_MGTAVTT ||HA10_P- ||-
|-
| K1414 ||<span style="color:#ff0000">not connected</span>MON_MGTAVCCAUX ||HA10_N- ||-
|-
| K1515, 16 ||DGND||GNDGround ||-
|-
| K16|} ==== Ethernet GPIO - JP18 ====JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|<span styleclass="color:#ff0000wikitable">not connected</span>||HA17_P_CC||
|-
|-
| K181, 2, 5,<br>6, 16||DGND||GNDGround ||-
|-
| K193 ||<span style="color:#ff0000">not connected</span>CLK125_NDO||HA21_P- ||-
|-
| K204 ||<span style="color:#ff0000">not connected</span>ETH1_CLK125_NDO ||HA21_N- ||-
|-
| K217 ||DGNDETH_MDC ||GND- ||-
|-
| K228 ||<span style="color:#ff0000">not connected</span>ETH1_MDC ||HA23_P- ||-
|-
| K239 ||<span style="color:#ff0000">not connected</span>ETH_MDIO ||HA23_N- ||-
|-
| K2410 ||DGNDETH1_MDIO ||GND- ||-
|-
| K2511 ||<span style="color:#ff0000">not connected</span>ETH_INTn ||HB00_P_CC- ||-
|-
| K2612 ||<span style="color:#ff0000">not connected</span>ETH1_INTn ||HB00_N_CC- ||-
|-
| K2713 ||DGNDPS_MIO51_501 ||GND- ||-
|-
| K2814 ||<span style="color:#ff0000">not connected</span>ETH1_RESETn ||HB06_P_CC- ||-
|-
| K2915 ||<span style="color:#ff0000">not connected</span>PS_MIO50_501 ||HB06_N_CC- ||-
|-
| K30} ==== SPI,NAND - JP19 ====JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 11, 12||DGND||GNDGround ||-
|-
| K312 ||<span style="color:#ff0000">not connected</span>NAND_BUSY||HB10_P- ||-
|-
| K323 ||<span style="color:#ff0000">not connected</span>ZYNQ_NAND_CLE ||HB10_N- ||-
|-
| K334 ||DGNDNAND_IO3 ||GND- ||-
|-
| K345 ||<span style="color:#ff0000">not connected</span>NAND_IO4 ||HB14_P- ||-
|-
| K356 ||<span style="color:#ff0000">not connected</span>NAND_IO5 ||HB14_N- ||-
|-
| K367 ||DGNDNAND_IO6 ||GND- ||-
|-
| K378 ||<span style="color:#ff0000">not connected</span>NAND_IO7 ||HB17_P_CC- ||-
|-
| K389 ||<span style="color:#ff0000">not connected</span>CONN_SPI_RSTn ||HB17_N_CC- ||-
|-
| K3910 ||DGNDMEM_WPn ||GND- ||-
|-
|}
<section begin=RTC/><section end== Pin strip connectors ===PinStrip/>==== SPIFPGA, WatchDog, RTC,NAND RST - JP13 JP22 ==== JP13 JP22 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 4, 9, 12 || DGND FPGA_INIT_B|| Ground - || -
|-
|2 || SPI0_CS0n RTC_32KHZ || - || -
|-
|3 || ZYNQ_SPI0_SCLK/NAND_IO1 FPGA_PROGRAM_B|| - || -
|-
|5 4 || ZYNQ_SPI0_DQ0/NAND_ALE RTC_RST || - || -
|-
|6 5 || NAND_CS0/SPI0_CS1 FPGA_DONE || - || -
|-
|7 6 || ZYNQ_SPI0_DQ2RTC_INT/NAND_IO2 SQW || - || -
|-
|7, 8 || ZYNQ_SPI0_DQ1/NAND_WE DGND || - Ground || -
|-
|10 9 || ZYNQ_SPI0_DQ3/NAND_IO0 WD_SET0 || - || -
|-
|11 10 || ZYNQ_NAND_RD_B SYS_RSTn || - || -
|-
|11 || WD_SET1 || - || -|-|12 || PORSTn || - || -|-|13 || WD_SET2 || - || -|-|14 || MRSTn || - || -|-|15 || PS_MIO15_500 || - || -|-|16 || CB_PWR_GOOD || - || -|-|}<section end=RTC/> ==== Voltage Monitor AUX PINs - JP15 JP29 ==== JP15 JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
!Pin#
!Notes
|-
|1 || MON_VCCPLL EVB_1.8V || - || -
|-
|2 || MON_33.3V || - || -
|-
|3 || MON_XADC_VCC PS_I2C0_DAT|| - || -
|-
|4 || MON_1V2_ETH I2C0_SDA || - || -
|-
|5 || MON_FPGA_VDDIO_BANK35 PS_I2C0_CK || - || -
|-
|6 || MON_VDDQ_1V5 I2C0_SCL || - || -
|-
|7 , 8,<br>13 || MON_FPGA_VDDIO_BANK34 DGND || - Ground || -
|-
|8 9 || MON_1.8V EXT_VMON2_V1 || - || -Mount option
|-
|9 10, 16 || MON_FPGA_VDDIO_BANK13 XADC_AGND || - Analog Ground || -
|-
|10 11 || MON_1.0V EXT_VMON2_V2 || - || -Mount option
|-
|11 12 || MON_1.8V_IO XADC_VN_R || - || -
|-
|12 14 || MON_MGTAVCC XADC_VP_R || - || -
|-
|13 || MON_MGTAVTT || - || -|-15 |14 || MON_MGTAVCCAUX INA_ALERT || - || -|-|15, 16 || DGND || Ground || -
|-
|}
Please note that:
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
JP30:
{| class="wikitable"
|-
!Notes
|-
|1, 2, 5,<br>6, 16|| DGND FPGA_BANK35_AD0N || Ground AD0_N || -Mount option
|-
|3 || CLK125_NDOFPGA_BANK35_AD1P || - AD1_P || -Mount option
|-
|4 || ETH1_CLK125_NDO FPGA_BANK35_AD0P || - AD0_P || -Mount option
|-
|7 5 || ETH_MDC FPGA_BANK35_AD1N || - AD1_N || -Mount option
|-
|8 || ETH1_MDC FPGA_BANK35_AD2P || - AD2_P || -Mount option
|-
|9 || ETH_MDIO FPGA_BANK35_AD3P || - AD3_P || -Mount option
|-
|10 || ETH1_MDIO FPGA_BANK35_AD2N || - AD2_N || -Mount option
|-
|11 ||ETH_INTn FPGA_BANK35_AD3N || - AD3_N || -Mount option
|-
|12 14 || ETH1_INTn FPGA_BANK35_AD4P || - AD4_P || -Mount option
|-
|13 15 || PS_MIO51_501 FPGA_BANK35_AD5P || - AD5_P || -Mount option
|-
|14 16 || ETH1_RESETn FPGA_BANK35_AD4N || - AD4_N || -Mount option
|-
|15 1, 6, 7,<br>12, 13 || PS_MIO50_501 DGND || - || -
|-
|}
{| class="wikitable"
|-
!Notes
|-
|1, 11, 12|| DGND FPGA_BANK35_AD5N || Ground AD5_N || -Mount option
|-
|2 4 || NAND_BUSYFPGA_BANK35_AD6P || - AD6_P || -Mount option
|-
|3 5 || ZYNQ_NAND_CLE FPGA_BANK35_AD7P || - AD7_P || -Mount option
|-
|4 6 || NAND_IO3 FPGA_BANK35_AD6N || - AD6_N || -Mount option
|-
|5 7 || NAND_IO4 FPGA_BANK35_AD7N || AD7_N || Mount option| - |10 | -| FPGA_BANK35_AD8P || AD8_P || Mount option
|-
|6 11 || NAND_IO5 FPGA_BANK35_AD9P || - AD9_P || -Mount option
|-
|7 12 || NAND_IO6 FPGA_BANK35_AD8N || - AD8_N || -Mount option
|-
|8 13 || NAND_IO7 FPGA_BANK35_AD9N || - AD9_N || -Mount option
|-
|9 16 || CONN_SPI_RSTn FPGA_BANK35_AD10P || - AD10_P || -Mount option
|-
|10 2, 3, 8,<br>9, 14, 15 || MEM_WPn DGND || - || -
|-
|}
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_INIT_BFPGA_BANK35_AD11P || - AD11_P || -Mount option
|-
|2 || RTC_32KHZ FPGA_BANK35_AD10N || - AD10_N || -Mount option
|-
|3 || FPGA_PROGRAM_BFPGA_BANK35_AD11N || - AD11_N || -Mount option
|-
|4 6 || RTC_RST FPGA_BANK35_AD12P || - AD12_P || -Mount option
|-
|5 7 || FPGA_DONE FPGA_BANK35_AD13P || - AD13_P || -Mount option
|-
|6 8 || RTC_INT/SQW FPGA_BANK35_AD12N || - AD12_N || -Mount option
|-
|7, 8 9 || DGND FPGA_BANK35_AD13N || Ground AD13_N || -Mount option
|-
|9 12 || WD_SET0 FPGA_BANK35_AD14P || - AD14_P || -Mount option
|-
|10 13 || SYS_RSTn FPGA_BANK35_AD15P || - AD15_P || -Mount option
|-
|11 14 || WD_SET1 FPGA_BANK35_AD14N || - AD14_N || -Mount option
|-
|12 15 || PORSTn FPGA_BANK35_AD15N || - AD15_N || -Mount option
|-
|13 || WD_SET2 || - || -|-|14 || MRSTn || - || -|-|15 || PS_MIO15_500 || - || -|-|4, 5, 10,<br>11, 16 || CB_PWR_GOOD DGND || - || -
|-
|}
<section begin=PMOD/>===Digilent Pmod™ Compatible headers == AUX PINs = Please note that: * Digilent Pmod™ Interface Specification - JP29 defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP29 JP17 is a 1612-pin 8x2x26x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 || EVB_1.8V PMOD_A0 || - || -
|-
|2 || 3.3V PMOD_A4 || - || -
|-
|3 || PS_I2C0_DATPMOD_A1 || || - |-|4 ||PMOD_A5 || || -
|-
|4 5 || I2C0_SDA PMOD_A2 || - || -
|-
|5 6 || PS_I2C0_CK PMOD_A6 || - || -
|-
|6 7 || I2C0_SCL PMOD_A3 || - || -
|-
|7, 8,<br>13 || DGND PMOD_A7 || Ground || -
|-
|9 , 10 || EXT_VMON2_V1 DGND || - Ground || Mount option-
|-
|1011, 16 12 || XADC_AGND 3.3V || Analog Ground || -
|-
|11 || EXT_VMON2_V2 || } ==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12- pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{|| Mount optionclass="wikitable"
|-
|-
|14 1 || XADC_VP_R PMOD_B0 || - || -
|-
|15 2 || INA_ALERT PMOD_B4 || - || -
|-
|} Please note that: * Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption ==== ADC ||PMOD_B1 || - JP30, JP31, JP32 ==== JP30, JP31, JP32 are 16|| -pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors: JP30:{| class="wikitable"
|-
|-
|2 5 || FPGA_BANK35_AD0N PMOD_B2 || AD0_N - || Mount option-
|-
|3 6 || FPGA_BANK35_AD1P PMOD_B6 || AD1_P - || Mount option-
|-
|4 7 || FPGA_BANK35_AD0P PMOD_B3 || AD0_P - || Mount option-
|-
|5 8 || FPGA_BANK35_AD1N PMOD_B7 || AD1_N - || Mount option-
|-
|8 9, 10 || FPGA_BANK35_AD2P DGND || AD2_P Ground || Mount option-
|-
|-
|}
<section end=PMOD/>
===JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
==PL's I/O voltage selections==
<section begin=Voltage selections/>
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
*'''voltage selection must be done before powering up the board'''.
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
|-
|-
|rowspan="2" |BoraX| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1 .2 - 3.3V)|style="text-align: center;" | FPGA_BANK35_AD5N User defined|style="text-align: center;" | AD5_N HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)|style="text-align: center;" | Mount optionUser defined
|-
|4 style="text-align: center;" |7030(SBG485 package)| FPGA_BANK35_AD6P style="text-align: center;" |HP(1.2 - 1.8V)| AD6_P style="text-align: center;" |User defined| Mount optionstyle="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined
|-
|5 rowspan="2" |Bora Lite| FPGA_BANK35_AD7P style="text-align: center;" |7007S/7010(CLG400 package)| AD7_P style="text-align: center;" || Mount optionHR|(1.2 -3.3V)|6 style="text-align: center;" |User defined| FPGA_BANK35_AD6N || AD6_N style="text-align: center;" || Mount optionHR|(1.2 -3.3V)|7 style="text-align: center;" |User defined| FPGA_BANK35_AD7N style="text-align: center;" |HR(1.2 - 3.3V)| AD7_N |style="text-align: center;" | Mount optionUser defined
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|10 style="text-align: center;" |7014S/7020(CLG400 package)| FPGA_BANK35_AD8P style="text-align: center;" |HR(1.2 - 3.3V)| AD8_P style="text-align: center;" |User defined| Mount style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance ===BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''. Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details. Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default optionfor BXELK)===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)
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! style="text-align: center; font-weight: bold;" |11 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP25.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD9P JP25.3-4! style="text-align: center; font-weight: bold;" |JP25.5-6! style="text-align: center; font-weight: bold;" | AD9_P JP25.7-8! style="text-align: center; font-weight: bold;" |JP25.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP25.11-12
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|12 style="text-align: center;" |1.2| FPGA_BANK35_AD8N style="text-align: center;" |open| AD8_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
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|13 style="text-align: center;" |1.5| FPGA_BANK35_AD9N style="text-align: center;" |open| AD9_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
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|16 style="text-align: center;" |1.8| FPGA_BANK35_AD10P style="text-align: center;" |open| AD10_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
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| style="text-align: center;" |2, 3, 8,<br>9, 14, 15 .5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" |'''closed'''| DGND style="text-align: center;" |open| style="text- align: center;" |open| style="text-align: center;" | open
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| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
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| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6!Pinstyle="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Examples of valid combinations for Zynq 7015-based SOMs===={| class="wikitable" style="text-align: center;"|+Bank # 13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #35 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6!Pin namestyle="text-align: center; font-weight: bold;" | JP27.7-8!Functionstyle="text-align: center; font-weight: bold;" | JP27.9-10!Notesstyle="text-align: center; font-weight: bold;" | JP27.11-12
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| style="text-align: center;" |1 .2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''|style="text-align: center;" | FPGA_BANK35_AD11P '''closed'''|style="text-align: center;" | AD11_P '''closed'''|style="text-align: center;" | Mount optionopen
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|2 style="text-align: center;" |1.5| FPGA_BANK35_AD10N style="text-align: center;" |open| AD10_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open
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|3 style="text-align: center;" |1.8| FPGA_BANK35_AD11N style="text-align: center;" |open| AD11_N style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
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|6 style="text-align: center;" |2.5| FPGA_BANK35_AD12P style="text-align: center;" |'''closed'''| AD12_P style="text-align: center;" |open| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
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|7 style="text-align: center;" |3.3| FPGA_BANK35_AD13P style="text-align: center;" |'''closed'''| AD13_P style="text-align: center;" |'''closed'''| Mount optionstyle="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open |} {| class="wikitable" style="text-align: center;"|+Bank #34 (HR)
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! style="text-align: center; font-weight: bold;" |8 Nominal voltage [V]! style="text-align: center; font-weight: bold;" |JP28.1-2! style="text-align: center; font-weight: bold;" | FPGA_BANK35_AD12N JP28.3-4! style="text-align: center; font-weight: bold;" |JP28.5-6! style="text-align: center; font-weight: bold;" | AD12_N JP28.7-8! style="text-align: center; font-weight: bold;" |JP28.9-10! style="text-align: center; font-weight: bold;" | Mount optionJP28.11-12
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|9 style="text-align: center;" |1.2| FPGA_BANK35_AD13N style="text-align: center;" |open| AD13_N style="text-align: center;" |open| Mount optionstyle="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open
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| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Advanced information about voltage selection connectors========= Bank 13 VDDIO selection connector (JP25) =====JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -|-|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -|-|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -|-|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -|-|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -|-|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 {{ImportantMessage|text=Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10.<br>Then, check and/or properly configure JP27 for selecting the required VDDIO_BANK35}} ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V<section end=Voltage selections/> <section begin=SOM/> ==SoM's signals mapping=====Bora Lite===As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''. {| class="wikitable"|+! colspan="2" |SoM's signal! colspan="6" |Routing options at carrier board level|-! rowspan="2" |Bank! rowspan="2" |Name! colspan="3" |Option #1(default)! colspan="3" |Option #2|-!Name!Pin!Note!Name!Pin!Note|-| rowspan="54" |34| rowspan="2" |IO_0_34| rowspan="2" |'''IO_0_VRN_34'''|J31.2|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27D.H2|FMC conn.|-| rowspan="2" |IO_25_34| rowspan="2" |'''IO_25_VRP_35'''|J31.4|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27B.D1|FMC conn.|-|IO_L10N_T1_34|IO_L10N_T1_34|J27D.H26|FMC conn.||||-|IO_L10P_T1_34|IO_L10P_T1_34|J27D.H25|FMC conn.||||-|IO_L11N_T1_SRCC_34|IO_L11N_T1_SRCC_34|J27D.G3|FMC conn.||||-|IO_L11P_T1_SRCC_34|IO_L11P_T1_SRCC_34|J27D.G2|FMC conn.||||-|IO_L12N_T1_MRCC_34|IO_L12N_T1_MRCC_34|J27D.H5|FMC conn.||||-|IO_L12P_T1_MRCC_34|IO_L12P_T1_MRCC_34|J27D.H4|FMC conn.||||-|IO_L13N_T2_MRCC_34|'''IO_L13N_T1_MRCC_34'''|J27D.G7|FMC conn.||||-|IO_L13P_T2_MRCC_34|'''IO_L13P_T1_MRCC_34'''|J27D.G6|FMC conn.||||-|IO_L14N_T2_SRCC_34|IO_L14N_T2_SRCC_34|J27B.D9|FMC conn.||||-|IO_L14P_T2_SRCC_34|IO_L14P_T2_SRCC_34|J27B.D8|FMC conn.||||-|IO_L15N_T2_DQS_34|IO_L15N_T2_DQS_34|J27B.D21|FMC conn.||||-|IO_L15P_T2_DQS_34|IO_L15P_T2_DQS_34|J27B.D20|FMC conn.||||-|IO_L16N_T2_34|IO_L16N_T2_34|J27B.C23|FMC conn.||||-|IO_L16P_T2_34|IO_L16P_T2_34|J27B.C22|FMC conn.||||-|IO_L17N_T2_34|IO_L17N_T2_34|J27D.G22|FMC conn.||||-|IO_L17P_T2_34|IO_L17P_T2_34|J27D.G21|FMC conn.||||-|IO_L18N_T2_34|IO_L18N_T2_34|J27D.H20|FMC conn.||||-|IO_L18P_T2_34|IO_L18P_T2_34|J27D.H19|FMC conn.||||-| rowspan="2" |IO_L19N_T3_VREF_34| rowspan="2" |IO_L19N_T3_VREF_34|J27D.G19|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP21|TP SMD|-|IO_L19P_T3_34|n/a|n/a|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L1N_T0_34|IO_L1N_T0_34|J27B.C19|FMC conn.||||-|IO_L1P_T0_34|IO_L1P_T0_34|J27B.C18|FMC conn.||||-|IO_L20N_T3_34|IO_L20N_T3_34|J27B.D18|FMC conn.||||-|IO_L20P_T3_34|IO_L20P_T3_34|J27B.D17|FMC conn.||||-|IO_L21N_T3_DQS_34|IO_L21N_T3_DQS_34|J27D.H17|FMC conn.||||-|IO_L21P_T3_DQS_34|IO_L21P_T3_DQS_34|J27D.H16|FMC conn.||||-|IO_L22N_T3_34|IO_L22N_T3_34|J27D.G16|FMC conn.||||-|IO_L22P_T3_34|IO_L22P_T3_34|J27D.G15|FMC conn.||||-|IO_L23N_T3_34|IO_L23N_T3_34|J27B.C11|FMC conn.||||-|IO_L23P_T3_34|IO_L23P_T3_34|J27B.C10|FMC conn.||||-|IO_L24N_T3_34|IO_L24N_T3_34|J27D.H23|FMC conn.||||-|IO_L24P_T3_34|IO_L24P_T3_34|J27D.H22|FMC conn.||||-|IO_L2N_T0_34|IO_L2N_T0_34|J27B.C15|FMC conn.||||-|IO_L2P_T0_34|IO_L2P_T0_34|J27B.C14|FMC conn.||||-|IO_L3N_T0_DQS_34|IO_L3N_T0_DQS_34|J27D.G13|FMC conn.||||-|IO_L3P_T0_DQS_PUDC_B_34(10K pull-up on SoM)|IO_L3P_T0_DQS_PUDC_B_34|J27D.G12|FMC conn.||||-|IO_L4N_T0_34|IO_L4N_T0_34|J27D.G10|FMC conn.||||-|IO_L4P_T0_34|IO_L4P_T0_34|J27D.G9|FMC conn.||||-|IO_L5N_T0_34|IO_L5N_T0_34|J27D.H11|FMC conn.||||-|IO_L5P_T0_34|IO_L5P_T0_34|J27D.H10|FMC conn.||||-| rowspan="2" |IO_L6N_T0_VREF_34| rowspan="2" |IO_L6N_T0_VREF_34|J27B.D15|FMC conn.||||-|TP22|TP SMD||||-|IO_L6P_T0_34|n/a|n/a|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L7N_T1_34|IO_L7N_T1_34|J27D.H8|FMC conn.||||-|IO_L7P_T1_34|IO_L7P_T1_34|J27D.H7|FMC conn.||||-|IO_L8N_T1_34|IO_L8N_T1_34|J27D.H14|FMC conn.||||-|IO_L8P_T1_34|IO_L8P_T1_34|J27D.H13|FMC conn.||||-|IO_L9N_T1_DQS_34|IO_L9N_T1_DQS_34|J27B.D12|FMC conn.||||-|IO_L9P_T1_DQS_34|IO_L9P_T1_DQS_34|J27B.D11|FMC conn.||||-|||||||||-| rowspan="54" |35| rowspan="2" |IO_0_35| rowspan="2" |'''IO_0_VRN_35'''|J27C.F1|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.1|Header|-| rowspan="2" |IO_25_35| rowspan="2" |'''IO_25_VRP_35'''|J27E.K13|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.3|Header|-|IO_L10N_T1_AD11N_35|IO_L10N_T1_AD11N_35|J27D.G34|FMC conn.|FPGA_BANK35_AD11N|JP32.3|Header|-|IO_L10P_T1_AD11P_35|IO_L10P_T1_AD11P_35|J27D.G33|FMC conn.|FPGA_BANK35_AD11P|JP32.1|Header|-|IO_L11N_T1_SRCC_35|IO_L11N_T1_SRCC_35|J27E.J3|FMC conn.||||-|IO_L11P_T1_SRCC_35|IO_L11P_T1_SRCC_35|J27E.J2|FMC conn.||||-|IO_L12N_T1_MRCC_35|IO_L12N_T1_MRCC_35|J27E.K5|FMC conn.||||-|IO_L12P_T1_MRCC_35|IO_L12P_T1_MRCC_35|J27E.K4|FMC conn.||||-|IO_L13N_T2_MRCC_35|IO_L13N_T2_MRCC_35|J27C.F5|FMC conn.||||-|IO_L13P_T2_MRCC_35|IO_L13P_T2_MRCC_35|J27C.F4|FMC conn.||||-|IO_L14N_T2_AD4N_SRCC_35|IO_L14N_T2_AD4N_SRCC_35|J27C.E3|FMC conn.|FPGA_BANK35_AD4N|JP30.16|Header|-|IO_L14P_T2_AD4P_SRCC_35|IO_L14P_T2_AD4P_SRCC_35|J27C.E2|FMC conn.|FPGA_BANK35_AD4P|JP30.14|Header|-|IO_L15N_T2_DQS_AD12N_35|IO_L15N_T2_DQS_AD12N_35|J27D.H38|FMC conn.|FPGA_BANK35_AD12N|JP32.8|Header|-|IO_L15P_T2_DQS_AD12P_35|IO_L15P_T2_DQS_AD12P_35|J27D.H37|FMC conn.|FPGA_BANK35_AD12P|JP32.6|Header|-|IO_L16N_T2_35|IO_L16N_T2_35|J27D.G37|FMC conn.||||-|IO_L16P_T2_35|IO_L16P_T2_35|J27D.G36|FMC conn.||||-|IO_L17N_T2_AD5N_35|IO_L17N_T2_AD5N_35|J27E.K8|FMC conn.|FPGA_BANK35_AD5N|JP31.1|Header|-|IO_L17P_T2_AD5P_35|IO_L17P_T2_AD5P_35|J27E.K7|FMC conn.|FPGA_BANK35_AD5P|JP30.15|Header|-|IO_L18N_T2_AD13N_35|IO_L18N_T2_AD13N_35|J27E.J7|FMC conn.|FPGA_BANK35_AD13N|JP32.9|Header|-|IO_L18P_T2_AD13P_35|IO_L18P_T2_AD13P_35|J27E.J6|FMC conn.|FPGA_BANK35_AD13P|JP32.7|Header|-| rowspan="2" |IO_L19N_T3_VREF_35| rowspan="2" |IO_L19N_T3_VREF_35|J27C.F8|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP24|TP SMD|-|IO_L19P_T3_35|IO_L19P_T3_35|J27C.F7|FMC conn.||||-|IO_L1N_T0_AD0N_35|IO_L1N_T0_AD0N_35|J27D.G25|FMC conn.|FPGA_BANK35_AD0P|JP30.4|Header|-|IO_L1P_T0_AD0P_35|IO_L1P_T0_AD0P_35|J27D.G24|FMC conn.|FPGA_BANK35_AD0N|JP30.2|Header|-|IO_L20N_T3_AD6N_35|IO_L20N_T3_AD6N_35|J27C.E7|FMC conn.|FPGA_BANK35_AD6N|JP31.6|Header|-|IO_L20P_T3_AD6P_35|IO_L20P_T3_AD6P_35|J27C.E6|FMC conn.|FPGA_BANK35_AD6P|JP31.4|Header|-|IO_L21N_T3_DQS_AD14N_35|IO_L21N_T3_DQS_AD14N_35|J27E.K11|FMC conn.|FPGA_BANK35_AD14N|JP32.14|Header|-|IO_L21P_T3_DQS_AD14P_35|IO_L21P_T3_DQS_AD14P_35|J27E.K10|FMC conn.| FPGA_BANK35_AD14P |JP32.12|Header|-|IO_L22N_T3_AD7N_35|IO_L22N_T3_AD7N_35|J27E.J10|FMC conn.|FPGA_BANK35_AD7N|JP31.7|Header|-|IO_L22P_T3_AD7P_35|IO_L22P_T3_AD7P_35|J27E.J9|FMC conn.|FPGA_BANK35_AD7P|JP31.5|Header|-|IO_L23N_T3_35|IO_L23N_T3_35|J27C.F11|FMC conn.||||-|IO_L23P_T3_35|IO_L23P_T3_35|J27C.F10|FMC conn.||||-|IO_L24N_T3_AD15N_35|IO_L24N_T3_AD15N_35|J27C.E10|FMC conn.|FPGA_BANK35_AD15N|JP32.15|Header|-|IO_L24P_T3_AD15P_35|IO_L24P_T3_AD15P_35|J27C.E9|FMC conn.|FPGA_BANK35_AD15P|JP32.13|Header|-|IO_L2N_T0_AD8N_35|IO_L2N_T0_AD8N_35|J27B.D24|FMC conn.|FPGA_BANK35_AD8N|JP31.12|Header|-|IO_L2P_T0_AD8P_35|IO_L2P_T0_AD8P_35|J27B.D23|FMC conn.|FPGA_BANK35_AD8P|JP31.10|Header|-|IO_L3N_T0_DQS_AD1N_35|IO_L3N_T0_DQS_AD1N_35|J27D.H29|FMC conn.|FPGA_BANK35_AD1N|JP30.5|Header|-|IO_L3P_T0_DQS_AD1P_35|IO_L3P_T0_DQS_AD1P_35|J27D.H28|FMC conn.|FPGA_BANK35_AD1P|JP30.3|Header|-|IO_L4N_T0_35|IO_L4N_T0_35|J27D.G28|FMC conn.||||-|IO_L4P_T0_35|IO_L4P_T0_35|J27D.G27|FMC conn.||||-|IO_L5N_T0_AD9N_35|IO_L5N_T0_AD9N_35|J27B.D27|FMC conn.|FPGA_BANK35_AD9N|JP31.13|Header|-|IO_L5P_T0_AD9P_35|IO_L5P_T0_AD9P_35|J27B.D26|FMC conn.|FPGA_BANK35_AD9P|JP31.11|Header|-| rowspan="2" |IO_L6N_T0_VREF_35| rowspan="2" |IO_L6N_T0_VREF_35|J27B.C27|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP23|TP SMD|-|IO_L6P_T0_35|IO_L6P_T0_35|J27B.C26|FMC conn.||||-|IO_L7N_T1_AD2N_35|IO_L7N_T1_AD2N_35|J27D.H32|FMC conn.|FPGA_BANK35_AD2N|JP30.10|Header|-|IO_L7P_T1_AD2P_35|IO_L7P_T1_AD2P_35|J27D.H31|FMC conn.|FPGA_BANK35_AD2P|JP30.8|Header|-|IO_L8N_T1_AD10N_35|IO_L8N_T1_AD10N_35|J27D.G31|FMC conn.|FPGA_BANK35_AD10N|JP32.2|Header|-|IO_L8P_T1_AD10P_35|IO_L8P_T1_AD10P_35|J27D.G30|FMC conn.|FPGA_BANK35_AD10P|JP31.16|Header|-|IO_L9N_T1_DQS_AD3N_35|IO_L9N_T1_DQS_AD3N_35|J27D.H35|FMC conn.|FPGA_BANK35_AD3N|JP30.11|Header|-|IO_L9P_T1_DQS_AD3P_35|IO_L9P_T1_DQS_AD3P_35|J27D.H34|FMC conn.|FPGA_BANK35_AD3P|JP30.9|Header|-|||||||||-| rowspan="26" |13'''(not available on Zynq 7007S and 7010)'''|IO_L11P_T1_SRCC_13|'''IO_L23P_T3_13'''|JP17.3|PMOD [A]||||-|IO_L11N_T1_SRCC_13|'''IO_L23N_T3_13'''|JP17.4|PMOD [A]||||-|IO_L12P_T1_MRCC_13|'''IO_L9P_T1_DQS_13'''|JP17.2|PMOD [A]|IO_L9P_T1_DQS_13|J30.1|ONE PIECE|-|IO_L12N_T1_MRCC_13|'''IO_L9N_T1_DQS_13'''|JP17.1|PMOD [A]|IO_L9N_T1_DQS_13|J30.3|ONE PIECE|-|IO_L13P_T2_MRCC_13|'''IO_L7P_T1_13'''|JP17.7|PMOD [A]|IO_L7P_T1_13|J30.24|ONE PIECE|-|IO_L13N_T2_MRCC_13|'''IO_L7N_T1_13'''|JP17.8|PMOD [A]|IO_L7N_T1_13|J30.26|ONE PIECE|-|IO_L14P_T2_SRCC_13|'''IO_L15P_T2_DQS_13'''|n/a|ETH1_RXCK|IO_L15P_T2_DQS_13|J30.25|ONE PIECE|-|IO_L14N_T2_SRCC_13|'''IO_L15N_T2_DQS_13'''|n/a|ETH1_RXCTL|IO_L15N_T2_DQS_13|J30.27|ONE PIECE|-|IO_L15P_T2_DQS_13|'''IO_L5P_T0_13'''|JP17.6|PMOD [A]|IO_L5P_T0_13|J30.20|ONE PIECE|-|IO_L15N_T2_DQS_13|'''IO_L5N_T0_13'''|JP17.5|PMOD [A]|IO_L5N_T0_13|J30.18|ONE PIECE|-|IO_L16N_T2_13|IO_L16N_T2_13|n/a|ETH1_TXCTL|IO_L16N_T2_13|J30.31|ONE PIECE|-|IO_L16P_T2_13|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE|-|IO_L17N_T2_13|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE|-|IO_L17P_T2_13|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE|-|IO_L18N_T2_13|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE|-|IO_L18P_T2_13|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE|-|IO_L19N_T3_VREF_13|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE|-|IO_L19P_T3_13|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|J30.41|ONE PIECE|-|IO_L20N_T3_13|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE|-|IO_L20P_T3_13|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE|-|IO_L21N_T3_DQS_13|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE|-|IO_L21P_T3_DQS_13|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE|-|IO_L22N_T3_13|IO_L22N_T3_13|||IO_L22N_T3_13|J30.55|ONE PIECE|-|IO_L22P_T3_13|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE|-| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |IO_L6N_T0_VREF_13|JP23.3|PMOD [B]| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |J30.30| rowspan="2" |ONE PIECE|-|n/a|USB1_OC| AD14_P } ==== BoraXEVB unavailable signals ====Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector. {|class="wikitable"| Mount option+BoraXEVB's signal that are not available when mated with Bora Lite SoM!Bank!Carrier's signal
|-
|13 || FPGA_BANK35_AD15P || AD15_P || Mount optionIO_25_13
|-
|14 13|| FPGA_BANK35_AD14N || AD14_N || Mount optionIO_L1P_T0_13
|-
|15 13|| FPGA_BANK35_AD15N || AD15_N || Mount optionIO_L1N_T0_13
|-
|4, 5, 10,<br>11, 16 13|| DGND || - || -IO_L2P_T0_13
|-
|}13 === Digilent Pmod™ Compatible headers === Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" IO_L2N_T0_13
|-
|-
|1 13||PMOD_A0 || || -IO_L3N_T0_DQS_13
|-
|2 13||PMOD_A4 || || -IO_L4P_T0_13
|-
|3 13||PMOD_A1 || || -IO_L4N_T0_13
|-
|4 500||PMOD_A5 || || -NAND_CS0/SPI0_CS1
|-
|5 500||PMOD_A2 || || -NAND_IO3
|-
|6 500||PMOD_A6 || || -NAND_IO4
|-
|7 500||PMOD_A3 || || -NAND_IO5
|-
|8 500||PMOD_A7 || || -NAND_IO6
|-
|9, 10 500||DGND ||Ground || -NAND_IO7
|-
|11, 12 500||3.3V || || -NAND_RD_B/VCFG1
|-
|500
|NAND_CLE/VCFG0
|}
<section end=SOM/>
<section begin==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 ||PMOD_B0 || - || -|-|2 ||PMOD_B4 || - || -|-|3 ||PMOD_B1 || - || -|-|4 ||PMOD_B5 || - || -|-|5 ||PMOD_B2 || - || -|-|6 ||PMOD_B6 || - || -|-|7 ||PMOD_B3 || - || -|-|8 ||PMOD_B7 || - || -|-|9, 10 ||DGND ||Ground || -|-|11, 12 ||3.3V || - || -|-|}Schematics/>
==Schematics==
* ORCAD: [https://www.dave.eu/links/p/yYW9VNsGutz6V0dd BORAXEVB-1.6.1-BELK-dsn.zip]
* PDF : [https://www.dave.eu/links/p/hClB4N7blBdSG6AH BoraXEVB-S-EVBBX0000C0R-1.6.1.pdf]
===BOM===* ORCADBoraXEVB: http[https://www.dave.eu/system/fileslinks/area-riservatap/boraxevb-1PU08ewKLvX9Z9tZJ BORAXEVB_S.0.3-BELK-dsnEVBBX0000C0R.zip* PDF : http://www.dave.eu/system/files/area-riservata/BoraXEVB-S-EVBBX0000C0R-1.26.0.pdfCSV.zip]
==BOM=Layout===* BoraXEVB: http[https://www.dave.eu/systemlinks/filesp/area-riservata/boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV_.zipcPT5UVAFNiSzj4NR CS143714 Assembly view]
==Layout=PCB design (Mentor PADS)===* http[https://www.dave.eu/systemlinks/p/filesBCTblnPPoDiwPrAE CS143714]<section end=Schematics/area-riservata><section begin=Mechanicals/boraxevb-CS143714_assembly_view.pdf>
==Mechanical==
* DXF: http[https://www.dave.eu/systemlinks/filesp/areas1k5AXL3AiCIo7Fj boraxevb-riservata/boraxevb_2D_CS143714.zip2D-CS143714]* IDF (3D): http[https://www.dave.eu/systemlinks/filesp/areaxeQvq2IvKig5vlfd boraxevb-3D-riservataCS143714]* STEP (3D): [https:/boraxevb_3D_CS143714/www.dave.zipeu/links/p/cj2s2AlBHkeY7tJ7 boraxevb_3D_step_cs143714]<section end=Mechanicals/>
