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BoraXEVB

34,542 bytes added, 10:02, 26 January 2022
→‎Bank 35 VDDIO selection connector (JP27)
{{InfoBoxTop}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
 
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SoM when it is sold with BoraX. When it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead.
 
Nevertheless, BoarX can host different models of BoraX and Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
 
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin==Introduction==Bora Xpress EVB is a carrier board designed to host [[BoraXpress SOM|Bora Xpress system-on-module]].Block Diagram/>
==Block Diagram==
The following picture shows Bora BORA Xpress EVB block diagram:
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]
===Configurable routing options===
FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.
 
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].
 
====BoraX====
[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
 
====Bora Lite====
[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
 
<section end=Block Diagram/>
== Features ==
|-
| FMC connector
| The FMC For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
|-
|}
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
 
<section begin=Reset button/>
 
=== Reset button - S6 ===
 
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
 
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
 
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
 
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora BORA Xpress module watchdog.For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
{| class="wikitable"
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
 
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/><section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
<section end=Ethernet1/>
=== BANK's Power GOOD signals - J28 ===
|}
<section begin=JTAG/>== BANK13 VDDIO selector - JP25 = JTAG ===JP25 JTAG port is a 12available as two different mechanical connectors:* 2.00mm-pin 6x2x2pitch 7x2 header (Xilinx standard)* 2.54 54mm-pitch vertical 10x2 header used for the selection - through jumpers - of the bank supply voltages(ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. The following table reports the pinout of * JTAG on BORA Xpress EVB is also connected to the FMC connector:. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ====
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|2 1, 3, 5, 7, 9, 11, 13 || LDO_B13_1V6DGND|| adds +1.6V to VDDIO_BANK13 - || -
|-
|2 || 3.3V|| - || -|-|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: 
{| class="wikitable"
|-
!Notes
|-
|1 || 3.3V|| - || -|-|2 || LDO_B35_1V63.3V|| adds +1- || -|-|3, 11, 17, 19 || N.C.6V to VDDIO_BANK35 || - || -
|-
|4 , 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| LDO_B35_800mVDGND|| adds +800mV to VDDIO_BANK35 - || -
|-
|6 5 || LDO_B35_400mVJTAG_TDI|| adds +400mV to VDDIO_BANK35 - || -
|-
|8 7 || LDO_B35_200mVJTAG_TMS|| adds +200mV to VDDIO_BANK35 - || -
|-
|10 9 || LDO_B35_100mVJTAG_TCK|| adds +100mV to VDDIO_BANK35 - || -
|-
|12 13 || LDO_B35_50mVJTAG_TDO|| adds +50mV to VDDIO_BANK35 - || -
|-
|1, 3, 5, 7, 9, 11 15 || DGNDJTAG_TRSTn|| - || -
|-
|}
<section end=JTAG/>
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -<section begin=Console/> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11=== UART1 -12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator === VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|2 1, 6, 4, 9|N.C.| VADJ_FB (22K)|| selects 3N.C.3V VADJ || -
|-
|4 2|UART_EXT_RX| VADJ_FB (30K9)|| selects 2.5V VADJ |Receive line| -Connected to protection diode array
|-
|6 3|UART_EXT_TX| VADJ_FB (51K1)Transmit line|| selects 1.8V VADJ || -Connected to protection diode array
|-
|8 5|DGND| VADJ_FB (68K)Ground|| selects 1.5V VADJ || -
|-
|10 7, 8|N.C.| VADJ_FB (100K)|| selects 1N.C.2V VADJ || -Connected to protection diode array
|-
|12 || RFU|| Reserved || -}|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|}<section end=Console/>
The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -<section begin=USB OTG/> supply VADJ with 1.8V# Jumper on 7=== USB OTG -8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The DEFAULT configuration is:# Jumper on 5-6 -> supply VADJ with 1.8VJ19 ===
=== JTAG ===J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
JTAG port is available as two different mechanical connectors:
* 2.00mm-pitch 7x2 header (Xilinx standard)
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
 
==== JTAG XILINX - J13 ====
 
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGNDUSB_OTG_VBUS || - || -
|-
|2 || 3.3VUSBM1 || - || -
|-
|4 3 || JTAG_TMSUSBP1 || - || -
|-
|6 4 || JTAG_TCKOTG_ID || - || -
|-
|8 5 || JTAG_TDOUSB_OTG_DGND || - || -
|-
|10 6, 7, 8, 9 || JTAG_TDI|| - || -|-|12 || N.C.|| - || -|-|14 || JTAG_TRSTnUSB_OTG_SHIELD || - || -
|-
|}
<section end=USB OTG/>
 
<section begin=micro SD/>
=== MicroSD - J21 ===
 
J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
==== JTAG ARM - J18 ====
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || 3.3VPS_SD0_DAT2||| - || -
|-
|2 || 3.3VPS_SD0_DAT3||| - || -
|-
|3, 11, 17, 19 || N.C.PS_SD0_CMD||| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND3.3V||| - || -
|-
|5 || JTAG_TDIPS_SD0_CLK||| - || -
|-
|7 6, 9, 10, 11, 12 || JTAG_TMSDGND||| - || -
|-
|9 7 || JTAG_TCKPS_SD0_DAT0||| - || -
|-
|13 8 || JTAG_TDOPS_SD0_DAT1||| - || -
|-
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[DWM_ADD-ON | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
{| class="wikitable"
!Notes
|-
|1, 62 ||5V || - || -|-|3, 4, 9|N|3.C.3V || - |N.C.|-
|-
|25, 6,<br> 9, 10,<br>19 |UART_EXT_RX|Receive lineDGND |Connected to protection diode array| - || -
|-
|37 |UART_EXT_TX|Transmit lineDWM_SD_CMD |Connected to protection diode array| - || -
|-
|58 |DGND|GroundDWM_SD_CLK || - || -
|-
|7, 811 |N.C.|N.C.DWM_SD_DAT0 |Connected to protection diode array| - || -
|-
|} === USB OTG - J19 === J19 is a standard USB MICRO AB connector12, 14,<br>16, 18,<br>20, 22 ||N. It is connected to the Bora Xpress USB 2C.0 OTG peripheral. The following table reports the pinout of the connector:|| - || -|-{| class="wikitable" 13 ||DWM_SD_DAT1 || - || -
|-
!Pin# !Pin name!Function!Notes|15 ||DWM_SD_DAT2 || - || -
|-
|1 17 ||USB_OTG_VBUS DWM_SD_DAT3 || - || -
|-
|2 21 ||USBM1 DWM_UART_RX || - || -
|-
|3 23 ||USBP1 DWM_UART_CTS || - || -
|-
|4 24 ||OTG_ID DWM_BT_F5 || - || -
|-
|5 25 ||USB_OTG_DGND DWM_UART_TX || - || -
|-
|6, 7, 8, 9 26 ||USB_OTG_SHIELD DWM_BT_F2 || - || -
|-
|} === MicroSD 27 ||DWM_UART_RTS || - J21 === J21 is a microSD memory card connector. It is connected to the Bora Xpress SOM through a bidirectional 1.8V/3.3V voltage|| -level translator mounted on the Bora Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector: {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes|28 ||DWM_WIFI_IRQ || - || -
|-
|1 29 ||PS_SD0_DAT2|DWM_BT_EN || - || -
|-
|2 30 ||PS_SD0_DAT3DWM_WIFI_EN ||| - || -|-|3 ||PS_SD0_CMD||| - || -|-|4 ||3.3V||| - || -|-|5 ||PS_SD0_CLK||| - || -|-|6, 9, 10, 11, 12 ||DGND||| - || -|-|7 ||PS_SD0_DAT0||| - || -|-|8 ||PS_SD0_DAT1||| - || -|-|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=DWM/>
 
<section begin=CAN/>
=== DWM (DAVE Wifi/BT module) socket CAN - J23 J24 ===J23 J24 is a 5299110-0308 connector type (30 pins, pin 5x2x2.54mm pitch vertical, 0header directly connected to BORA Xpress SoM's transceiver for the CAN interface.50mm picth)This 2. This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVB5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1, 2 6,<br>7, 8,<br>9, 10 ||5V N.C. || - || -
|-
|32, 4 5 ||3.3V CAN_SHIELD || - || -
|-
|5, 6,<br> 9, 10,<br>19 3 ||DGND CAN_L || - || -
|-
|7 4 ||DWM_SD_CMD CAN_H || - || -
|-
|8 ||DWM_SD_CLK || }<section end=CAN/><section begin=Touchscreen/>=== Touch screen - J25===J25 is a ZIF 4- pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector: {|| -class="wikitable"
|-
|11 ||DWM_SD_DAT0 || - || -!Pin# !Pin name!Function!Notes
|-
|12, 14,<br>16, 18,<br>20, 22 1 ||N.C. TSC_YP || - || -
|-
|13 2 ||DWM_SD_DAT1 TSC_XP || - || -
|-
|15 3 ||DWM_SD_DAT2 TSC_YM || - || -
|-
|17 4 ||DWM_SD_DAT3 TSC_XM || - || -
|-
|21 ||DWM_UART_RX || }<section end=Touchscreen/><section begin=LVDS/>=== LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux- drivers/platforms/zynq. The following table reports the pinout of the connector: {|| -class="wikitable"
|-
|23 ||DWM_UART_CTS || - || -!Pin# !Pin name!Function!Notes
|-
|24 1, 2 ||DWM_BT_F5 3.3V_LCD || - || -
|-
|25 3, 4, 7, 10,<br>13, 16, 19 ||DWM_UART_TX DGND || - Ground || -
|-
|26 5 ||DWM_BT_F2 LCD_LVDS_D0- || - || -
|-
|27 6 ||DWM_UART_RTS LCD_LVDS_D0+ || - || -
|-
|28 8 ||DWM_WIFI_IRQ LCD_LVDS_D1- || - || -
|-
|29 9 ||DWM_BT_EN LCD_LVDS_D1+ || - || -
|-
|30 11 ||DWM_WIFI_EN LCD_LVDS_D2- || - || -
|-
|} === CAN 12 ||LCD_LVDS_D2+ || - J24 ===J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC|| -10/DB9 flat cables. The following table reports the pinout of the connector: {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes|14 ||LCD_LVDS_CLK- || - || -
|-
|1, 6,<br>7, 8,<br>9, 10 15 ||N.C. LCD_LVDS_CLK+ || - || -
|-
|2, 5 17 ||CAN_SHIELD LCD_P17 || - || -
|-
|3 18 ||CAN_L LCD_P18 || - || -
|-
|4 20 ||CAN_H LCD_P20 || - || -|-|21,22 ||DGND || Ground || Shield
|-
|}
<section end=LVDS/>
<section begin=FMC/>
=== FPGA Mezzanine Card (FMC) Connector - J27 ===
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
 
Please note that BoraXpress EVB FMC Connector is:
* fully compliant to FMC LPC
* partially compliant to FMC HPC because HPC side is not fully populated.
 
The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zip|link]] a spreadsheet providing the same information is available for download.
 
For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|this section]].
=== Touch screen - J25= HPC Row A ====J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
!Notes
|-
|1 A1||TSC_YP DGND||GND||| - | A2||MGTxRXP1||DP1_M2C_P|| -
|-
|2 A3||TSC_XP MGTxRXN1|| - DP1_M2C_N|| -
|-
|3 A4||TSC_YM DGND|| - GND|| -
|-
|4 A5||TSC_XM DGND|| - GND|| -
|-
|} === LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector: {A6||MGTxRXP2||DP2_M2C_P|| class="wikitable"
|-
!Pin# | A7||MGTxRXN2||DP2_M2C_N||!Pin name|-!Function!Notes| A8||DGND||GND||
|-
|1, 2 A9||3.3V_LCD DGND|| - GND|| -
|-
|3, 4, 7, 10,<br>13, 16, 19 A10||DGND MGTxRXP3|| Ground DP3_M2C_P|| -
|-
|5 A11||LCD_LVDS_D0- MGTxRXN3|| - DP3_M2C_N|| -
|-
|6 A12||LCD_LVDS_D0+ DGND|| - GND|| -
|-
|8 A13||LCD_LVDS_D1- DGND|| - GND|| -
|-
|9 A14||LCD_LVDS_D1+ <span style="color:#ff0000">not connected</span>|| - DP4_M2C_P|| -
|-
|11 A15||LCD_LVDS_D2- <span style="color:#ff0000">not connected</span>|| - DP4_M2C_N|| -
|-
|12 A16||LCD_LVDS_D2+ DGND|| - GND|| -
|-
|15 A17||LCD_LVDS_CLK+ DGND|| - GND|| -
|-
|17 A18||LCD_P17 <span style="color:#ff0000">not connected</span>|| - DP5_M2C_P|| -
|-
|18 A19||LCD_P18 <span style="color:#ff0000">not connected</span>|| - DP5_M2C_N|| -
|-
|20 A20||LCD_P20 DGND|| - GND|| -
|-
|21,22 A21||DGND || Ground GND|| Shield
|-
|} === FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards. Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated. ==== HPC Row A ==== {A22||MGTxTXP1||DP1_C2M_P|| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| A23||MGTxTXN1||DP1_C2M_N||
|-
| A1A24||DGND||GND||
|-
| A2A25||MGTxRXP1DGND||DP1_M2C_PGND||
|-
| A3A26||MGTxRXN1MGTxTXP2||DP1_M2C_NDP2_C2M_P||
|-
| A4A27||DGNDMGTxTXN2||GNDDP2_C2M_N||
|-
| A5A28||DGND||GND||
|-
| A6A29||MGTxRXP2DGND||DP2_M2C_PGND||
|-
| A7A30||MGTxRXN2MGTxTXP3||DP2_M2C_NDP3_C2M_P||
|-
| A8A31||DGNDMGTxTXN3||GNDDP3_C2M_N||
|-
| A9A32||DGND||GND||
|-
| A10A33||MGTxRXP3DGND||DP3_M2C_PGND||
|-
| A11A34||MGTxRXN3<span style="color:#ff0000">not connected</span>||DP3_M2C_NDP4_C2M_P||
|-
| A12A35||DGND<span style="color:#ff0000">not connected</span>||GNDDP4_C2M_N||
|-
| A13A36||DGND||GND||
|-
| A14A37||NCDGND||DP4_M2C_PGND||
|-
| A15A38||NC<span style="color:#ff0000">not connected</span>||DP4_M2C_NDP5_C2M_P||
|-
| A16A39||DGND<span style="color:#ff0000">not connected</span>||GNDDP5_C2M_N||
|-
| A17A40||DGND||GND|||} ==== HPC Row B ==== {| class="wikitable"
|-
| A18||NC||DP5_M2C_P||!Pin# !Pin name!Function!Notes
|-
| A19B1||NCRSVD||DP5_M2C_NRES1||
|-
| A20B2||DGND||GND||
|-
| A21B3||DGND||GND||
|-
| A22B4||MGTxTXP1<span style="color:#ff0000">not connected</span>||DP1_C2M_PDP9_M2C_P||
|-
| A23B5||MGTxTXN1<span style="color:#ff0000">not connected</span>||DP1_C2M_NDP9_M2C_N||
|-
| A24B6||DGND||GND||
|-
| A25B7||DGND||GND||
|-
| A26B8||MGTxTXP2<span style="color:#ff0000">not connected</span>||DP2_C2M_PDP8_M2C_P||
|-
| A27B9||MGTxTXN2<span style="color:#ff0000">not connected</span>||DP2_C2M_NDP8_M2C_N||
|-
| A28B10||DGND||GND||
|-
| A29B11||DGND||GND||
|-
| A30B12||MGTxTXP3<span style="color:#ff0000">not connected</span>||DP3_C2M_PDP7_M2C_P||
|-
| A31B13||MGTxTXN3<span style="color:#ff0000">not connected</span>||DP3_C2M_NDP7_M2C_N||
|-
| A32B14||DGND||GND||
|-
| A33B15||DGND||GND||
|-
| A34B16||NC<span style="color:#ff0000">not connected</span>||DP4_C2M_PDP6_M2C_P||
|-
| A35B17||NC<span style="color:#ff0000">not connected</span>||DP4_C2M_NDP6_M2C_N||
|-
| A36B18||DGND||GND||
|-
| A37B19||DGND||GND||
|-
| A38B20||NCMGTREFCLK1P||DP5_C2M_PGBTCLK1_M2C_P||
|-
| A39B21||NCMGTREFCLK1N||DP5_C2M_NGBTCLK1_M2C_N||
|-
| A40B22||DGND||GND|||} ==== HPC Row B ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| B23||DGND||GND||
|-
| B1B24||RSVD<span style="color:#ff0000">not connected</span>||RES1DP9_C2M_P||
|-
| B2B25||DGND<span style="color:#ff0000">not connected</span>||GNDDP9_C2M_N||
|-
| B3B26||DGND||GND||
|-
| B4B27||NCDGND||DP9_M2C_PGND||
|-
| B5B28||NC<span style="color:#ff0000">not connected</span>||DP9_M2C_NDP8_C2M_P||
|-
| B6B29||DGND<span style="color:#ff0000">not connected</span>||GNDDP8_C2M_N||
|-
| B7B30||DGND||GND||
|-
| B8B31||NCDGND||DP8_M2C_PGND||
|-
| B9B32||NC<span style="color:#ff0000">not connected</span>||DP8_M2C_NDP7_C2M_P||
|-
| B10B33||DGND<span style="color:#ff0000">not connected</span>||GNDDP7_C2M_N||
|-
| B11B34||DGND||GND||
|-
| B12B35||NCDGND||DP7_M2C_PGND||
|-
| B13B36||NC<span style="color:#ff0000">not connected</span>||DP7_M2C_NDP6_C2M_P||
|-
| B14B37||DGND<span style="color:#ff0000">not connected</span>||GNDDP6_C2M_N||
|-
| B15B38||DGND||GND||
|-
| B16B39||NCDGND||DP6_M2C_PGND||
|-
| B17B40||NCRSVD||DP6_M2C_NRES0|||} ==== LPC Row C ==== {| class="wikitable"
|-
| B18||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| B19C1||DGND||GND||
|-
| B20C2||MGTREFCLK1PMGTxTXP0||GBTCLK1_M2C_PDP0_C2M_P||
|-
| B21C3||MGTREFCLK1NMGTxTXN0||GBTCLK1_M2C_NDP0_C2M_N||
|-
| B22C4||DGND||GND||
|-
| B23C5||DGND||GND||
|-
| B24C6||NCMGTxRXP0||DP9_C2M_PDP0_M2C_P||
|-
| B25C7||NCMGTxRXN0||DP9_C2M_NDP0_M2C_N||
|-
| B26C8||DGND||GND||
|-
| B27C9||DGND||GND||
|-
| B28C10||NCIO_L23P_T3_34||DP8_C2M_PLA06_P||
|-
| B29C11||NCIO_L23N_T3_34||DP8_C2M_NLA06_N||
|-
| B30C12||DGND||GND||
|-
| B31C13||DGND||GND||
|-
| B32C14||NCIO_L2P_T0_34||DP7_C2M_PLA10_P||
|-
| B33C15||NCIO_L2N_T0_34||DP7_C2M_NLA10_N||
|-
| B34C16||DGND||GND||
|-
| B35C17||DGND||GND||
|-
| B36C18||NCIO_L1P_T0_34||DP6_C2M_PLA14_P||
|-
| B37C19||NCIO_L1N_T0_34||DP6_C2M_NLA14_N||
|-
| B38C20||DGND||GND||
|-
| B39C21||DGND||GND||
|-
| B40C22||RSVDIO_L16P_T2_34||RES0LA18_P_CC|||} ==== LPC Row C ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| C23||IO_L16N_T2_34||LA18_N_CC||
|-
| C1C24||DGND||GND||
|-
| C2C25||MGTxTXP0DGND||DP0_C2M_PGND||
|-
| C3C26||MGTxTXN0IO_L6P_T0_35||DP0_C2M_NLA27_P||
|-
| C4C27||DGNDIO_L6N_T0_VREF_35||GNDLA27_N||
|-
| C5C28||DGND||GND||
|-
| C6C29||MGTxRXP0DGND||DP0_M2C_PGND||
|-
| C7C30||MGTxRXN0I2C0_SCL||DP0_M2C_NSCL||
|-
| C8C31||DGNDI2C0_SDA||GNDSDA||
|-
| C9C32||DGND||GND||
|-
| C10C33||IO_L23P_T3_34DGND||LA06_PGND||
|-
| C11C34||IO_L23N_T3_34GA0||LA06_NGA0||
|-
| C12C35||DGNDFMC_12P0V||GND12P0V||
|-
| C13C36||DGND||GND||
|-
| C14C37||IO_L2P_T0_34FMC_12P0V||LA10_P12P0V||
|-
| C15C38||IO_L2N_T0_34DGND||LA10_NGND||
|-
| C16C39||DGNDFMC_3P3V||GND3P3V||
|-
| C17C40||DGND||GND|||} ==== LPC Row D ==== {| class="wikitable"
|-
| C18||IO_L1P_T0_34||LA14_P||!Pin# !Pin name!Function!Notes
|-
| C19D1||IO_L1N_T0_34IO_25_VRP_34||LA14_NPG_C2M||
|-
| C20D2||DGND||GND||
|-
| C21D3||DGND||GND||
|-
| C22D4||IO_L16P_T2_34MGTREFCLK0P||LA18_P_CCGBTCLK0_M2C_P||
|-
| C23D5||IO_L16N_T2_34MGTREFCLK0N||LA18_N_CCGBTCLK0_M2C_N||
|-
| C24D6||DGND||GND||
|-
| C25D7||DGND||GND||
|-
| C26D8||IO_L6P_T0_35IO_L14P_T2_SRCC_34||LA27_PLA01_P_CC||
|-
| C27D9||IO_L6N_T0_VREF_35IO_L14N_T2_SRCC_34||LA27_NLA01_N_CC||
|-
| C28D10||DGND||GND||
|-
| C29D11||DGNDIO_L9P_T1_DQS_34||GNDLA05_P||
|-
| C30D12||I2C0_SCLIO_L9N_T1_DQS_34||SCLLA05_N||
|-
| C31D13||I2C0_SDADGND||SDAGND||
|-
| C32D14||DGNDIO_L6P_T0_34||GNDLA09_P||
|-
| C33D15||DGNDIO_L6N_T0_VREF_34||GNDLA09_N||
|-
| C34D16||GA0DGND||GA0GND||
|-
| C35D17||FMC_12P0VIO_L20P_T3_34||12P0VLA13_P||
|-
| C36D18||DGNDIO_L20N_T3_34||GNDLA13_N||
|-
| C37D19||FMC_12P0VDGND||12P0VGND||
|-
| C38D20||DGNDIO_L15P_T2_DQS_34||GNDLA17_P_CC||
|-
| C39D21||FMC_3P3VIO_L15N_T2_DQS_34||3P3VLA17_N_CC||
|-
| C40D22||DGND||GND|||} ==== LPC Row D ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| D23||IO_L2P_T0_AD8P_35||LA23_P||
|-
| D1D24||IO_25_VRP_34IO_L2N_T0_AD8N_35||PG_C2MLA23_N||
|-
| D2D25||DGND||GND||
|-
| D3D26||DGNDIO_L5P_T0_AD9P_35||GNDLA26_P||
|-
| D4D27||MGTREFCLK0PIO_L5N_T0_AD9N_35||GBTCLK0_M2C_PLA26_N||
|-
| D5D28||MGTREFCLK0NDGND||GBTCLK0_M2C_NGND||
|-
| D6D29||DGNDJTAG_TCK||GNDTCK||
|-
| D7D30||DGNDJTAG_TDI||GNDTDI||
|-
| D8D31||IO_L14P_T2_SRCC_34FMC_TDO_ZYNQ_TDI||LA01_P_CCTDO||
|-
| D9D32||IO_L14N_T2_SRCC_34FMC_3P3VAUX||LA01_N_CC3P3VAUX||
|-
| D10D33||DGNDJTAG_TMS||GNDTMS||
|-
| D11D34||IO_L9P_T1_DQS_34JTAG_TRSTn||LA05_PTRST_L||
|-
| D12D35||IO_L9N_T1_DQS_34GA0||LA05_NGA1||
|-
| D13D36||DGNDFMC_3P3V||GND3P3V||
|-
| D14D37||IO_L6P_T0_34DGND||LA09_PGND||
|-
| D15D38||IO_L6N_T0_VREF_34FMC_3P3V||LA09_N3P3V||
|-
| D16D39||DGND||GND||
|-
| D17D40||IO_L20P_T3_34FMC_3P3V||LA13_P3P3V|||} ==== HPC Row E ==== {| class="wikitable"
|-
| D18||IO_L20N_T3_34||LA13_N||!Pin# !Pin name!Function!Notes
|-
| D19E1||DGND||GND||
|-
| D20E2||IO_L15P_T2_DQS_34IO_L14P_T2_AD4P_SRCC_35||LA17_P_CCHA01_P_CC||
|-
| D21E3||IO_L15N_T2_DQS_34IO_L14N_T2_AD4N_SRCC_35||LA17_N_CCHA01_N_CC||
|-
| D22E4||DGND||GND||
|-
| D23E5||IO_L2P_T0_AD8P_35DGND||LA23_PGND||
|-
| D24E6||IO_L2N_T0_AD8N_35IO_L20P_T3_AD6P_35||LA23_NHA05_P||
|-
| D25E7||DGNDIO_L20N_T3_AD6N_35||GNDHA05_N||
|-
| D26E8||IO_L5P_T0_AD9P_35DGND||LA26_PGND||
|-
| D27E9||IO_L5N_T0_AD9N_35IO_L24P_T3_AD15P_35||LA26_NHA09_P||
|-
| D28E10||DGNDIO_L24N_T3_AD15N_35||GNDHA09_N||
|-
| D29E11||JTAG_TCKDGND||TCKGND||
|-
| D30E12||JTAG_TDI<span style="color:#ff0000">not connected</span>||TDIHA13_P||
|-
| D31E13||FMC_TDO_ZYNQ_TDI<span style="color:#ff0000">not connected</span>||TDOHA13_N||
|-
| D32E14||FMC_3P3VAUXDGND||3P3VAUXGND||
|-
| D33E15||JTAG_TMS<span style="color:#ff0000">not connected</span>||TMSHA16_P||
|-
| D34E16||JTAG_TRSTn<span style="color:#ff0000">not connected</span>||TRST_LHA16_N||
|-
| D35E17||GA0DGND||GA1GND||
|-
| D36E18||FMC_3P3V<span style="color:#ff0000">not connected</span>||3P3VHA20_P||
|-
| D37E19||DGND<span style="color:#ff0000">not connected</span>||GNDHA20_N||
|-
| D38E20||FMC_3P3VDGND||3P3VGND||
|-
| D39E21||DGND<span style="color:#ff0000">not connected</span>||GNDHB03_P||
|-
| D40E22||FMC_3P3V||3P3V<span style="color:#ff0000">not connected</span>||HB03_N|} ==== HPC Row E ==== {| class="wikitable"
|-
!Pin# !Pin name!Function!Notes| E23||DGND||GND||
|-
| E1E24||DGND<span style="color:#ff0000">not connected</span>||GNDHB05_P||
|-
| E2E25||IO_L14P_T2_AD4P_SRCC_35<span style="color:#ff0000">not connected</span>||HA01_P_CCHB05_N||
|-
| E3E26||IO_L14N_T2_AD4N_SRCC_35DGND||HA01_N_CCGND||
|-
| E4E27||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_P||
|-
| E5E28||DGND<span style="color:#ff0000">not connected</span>||GNDHB09_N||
|-
| E6E29||IO_L20P_T3_AD6P_35DGND||HA05_PGND||
|-
| E7E30||IO_L20N_T3_AD6N_35<span style="color:#ff0000">not connected</span>||HA05_NHB13_P||
|-
| E8E31||DGND<span style="color:#ff0000">not connected</span>||GNDHB13_N||
|-
| E9E32||IO_L24P_T3_AD15P_35DGND||HA09_PGND||
|-
| E10E33||IO_L24N_T3_AD15N_35<span style="color:#ff0000">not connected</span>||HA09_NHB19_P||
|-
| E11E34||DGND<span style="color:#ff0000">not connected</span>||GNDHB19_N||
|-
| E12E35||NCDGND||HA13_PGND||
|-
| E13E36||NC<span style="color:#ff0000">not connected</span>||HA13_NHB21_P||
|-
| E14E37||DGND<span style="color:#ff0000">not connected</span>||GNDHB21_N||
|-
| E15||NC||HA16_P|||-| E16||NC||HA16_N|||-| E17||DGND||GND|||-| E18||NC||HA20_P|||-| E19||NC||HA20_N|||-| E20||DGND||GND|||-| E21||NC||HB03_P|||-| E22||NC||HB03_N|||-| E23||DGND||GND|||-| E24||NC||HB05_P|||-| E25||NC||HB05_N|||-| E26||DGND||GND|||-| E27||NC||HB09_P|||-| E28||NC||HB09_N|||-| E29||DGND||GND|||-| E30||NC||HB13_P|||-| E31||NC||HB13_N|||-| E32||DGND||GND|||-| E33||NC||HB19_P|||-| E34||NC||HB19_N|||-| E35||DGND||GND|||-| E36||NC||HB21_P|||-| E37||NC||HB21_N|||-| E38||DGND||GND||
|-
| E39||FMC_VADJ||VADJ||
| F12||DGND||GND||
|-
| F13||NC<span style="color:#ff0000">not connected</span>||HA12_P||
|-
| F14||NC<span style="color:#ff0000">not connected</span>||HA12_N||
|-
| F15||DGND||GND||
|-
| F16||NC<span style="color:#ff0000">not connected</span>||HA15_P||
|-
| F17||NC<span style="color:#ff0000">not connected</span>||HA15_N||
|-
| F18||DGND||GND||
|-
| F19||NC<span style="color:#ff0000">not connected</span>||HA19_P||
|-
| F20||NC<span style="color:#ff0000">not connected</span>||HA19_N||
|-
| F21||DGND||GND||
|-
| F22||NC<span style="color:#ff0000">not connected</span>||HB02_P||
|-
| F23||NC<span style="color:#ff0000">not connected</span>||HB02_N||
|-
| F24||DGND||GND||
|-
| F25||NC<span style="color:#ff0000">not connected</span>||HB04_P||
|-
| F26||NC<span style="color:#ff0000">not connected</span>||HB04_N||
|-
| F27||DGND||GND||
|-
| F28||NC<span style="color:#ff0000">not connected</span>||HB08_P||
|-
| F29||NC<span style="color:#ff0000">not connected</span>||HB08_N||
|-
| F30||DGND||GND||
|-
| F31||NC<span style="color:#ff0000">not connected</span>||HB12_P||
|-
| F32||NC<span style="color:#ff0000">not connected</span>||HB12_N||
|-
| F33||DGND||GND||
|-
| F34||NC<span style="color:#ff0000">not connected</span>||HB16_P||
|-
| F35||NC<span style="color:#ff0000">not connected</span>||HB16_N||
|-
| F36||DGND||GND||
|-
| F37||NC<span style="color:#ff0000">not connected</span>||HB20_P||
|-
| F38||NC<span style="color:#ff0000">not connected</span>||HB20_N||
|-
| F39||DGND||GND||
| J11||DGND||GND||
|-
| J12||NC<span style="color:#ff0000">not connected</span>||HA11_P||
|-
| J13||NC<span style="color:#ff0000">not connected</span>||HA11_N||
|-
| J14||DGND||GND||
|-
| J15||NC<span style="color:#ff0000">not connected</span>||HA14_P||
|-
| J16||NC<span style="color:#ff0000">not connected</span>||HA14_N||
|-
| J17||DGND||GND||
|-
| J18||NC<span style="color:#ff0000">not connected</span>||HA18_P||
|-
| J19||NC<span style="color:#ff0000">not connected</span>||HA18_N||
|-
| J20||DGND||GND||
|-
| J21||NC<span style="color:#ff0000">not connected</span>||HA22_P||
|-
| J22||NC<span style="color:#ff0000">not connected</span>||HA22_N||
|-
| J23||DGND||GND||
|-
| J24||NC<span style="color:#ff0000">not connected</span>||HB01_P||
|-
| J25||NC<span style="color:#ff0000">not connected</span>||HB01_N||
|-
| J26||DGND||GND||
|-
| J27||NC<span style="color:#ff0000">not connected</span>||HB07_P||
|-
| J28||NC<span style="color:#ff0000">not connected</span>||HB07_N||
|-
| J29||DGND||GND||
|-
| J30||NC<span style="color:#ff0000">not connected</span>||HB11_P||
|-
| J31||NC<span style="color:#ff0000">not connected</span>||HB11_N||
|-
| J32||DGND||GND||
|-
| J33||NC<span style="color:#ff0000">not connected</span>||HB15_P||
|-
| J34||NC<span style="color:#ff0000">not connected</span>||HB15_N||
|-
| J35||DGND||GND||
|-
| J36||NC<span style="color:#ff0000">not connected</span>||HB18_P||
|-
| J37||NC<span style="color:#ff0000">not connected</span>||HB18_N||
|-
| J38||DGND||GND||
|-
| J39||NC<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|-
| J40||DGND||GND||
!Notes
|-
| K1||NC<span style="color:#ff0000">not connected</span>||VREF_B_M2C||
|-
| K2||DGND||GND||
| K13||IO_25_VRP_35||HA10_P||
|-
| K14||NC<span style="color:#ff0000">not connected</span>||HA10_N||
|-
| K15||DGND||GND||
|-
| K16||NC<span style="color:#ff0000">not connected</span>||HA17_P_CC||
|-
| K17||NC<span style="color:#ff0000">not connected</span>||HA17_N_CC||
|-
| K18||DGND||GND||
|-
| K19||NC<span style="color:#ff0000">not connected</span>||HA21_P||
|-
| K20||NC<span style="color:#ff0000">not connected</span>||HA21_N||
|-
| K21||DGND||GND||
|-
| K22||NC<span style="color:#ff0000">not connected</span>||HA23_P||
|-
| K23||NC<span style="color:#ff0000">not connected</span>||HA23_N||
|-
| K24||DGND||GND||
|-
| K25||NC<span style="color:#ff0000">not connected</span>||HB00_P_CC||
|-
| K26||NC<span style="color:#ff0000">not connected</span>||HB00_N_CC||
|-
| K27||DGND||GND||
|-
| K28||NC<span style="color:#ff0000">not connected</span>||HB06_P_CC||
|-
| K29||NC<span style="color:#ff0000">not connected</span>||HB06_N_CC||
|-
| K30||DGND||GND||
|-
| K31||NC<span style="color:#ff0000">not connected</span>||HB10_P||
|-
| K32||NC<span style="color:#ff0000">not connected</span>||HB10_N||
|-
| K33||DGND||GND||
|-
| K34||NC<span style="color:#ff0000">not connected</span>||HB14_P||
|-
| K35||NC<span style="color:#ff0000">not connected</span>||HB14_N||
|-
| K36||DGND||GND||
|-
| K37||NC<span style="color:#ff0000">not connected</span>||HB17_P_CC||
|-
| K38||NC<span style="color:#ff0000">not connected</span>||HB17_N_CC||
|-
| K39||DGND||GND||
|-
| K40||NC<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
<section end=FMC/><section begin=PinStrip/>
=== Pin strip connectors ===
|-
|}
 
==== Ethernet GPIO - JP18 ====
|-
|}
 
==== SPI,NAND - JP19 ====
|}
<section begin=RTC/>
<section end=PinStrip/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/>
==== AUX PINs - JP29 ====
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
|}
<section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
|-
|}
 
==== Digilent Pmod™ Compatible - JP23 ====
|-
|}
<section end=PMOD/>
 
===JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
 
==PL's I/O voltage selections==
<section begin=Voltage selections/>
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
*'''voltage selection must be done before powering up the board'''.
 
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
 
{| class="wikitable" style="text-align: center;"
! rowspan="2" |SoM
! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35
|-
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
| rowspan="2" |BoraX
| style="text-align: center;" | 7015
(CLG485 package)
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
|-
| style="text-align: center;" | 7030
(SBG485 package)
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|-
| rowspan="2" |Bora Lite
| style="text-align: center;" | 7007S/7010
(CLG400 package)
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
|-
| style="text-align: center;" | 7014S/7020
(CLG400 package)
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
 
===BoraXEVB voltage selection jumpers===
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
 
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
 
Even if PL's banks are independent, default configuration of BoraXEVB is such that
*bank 34 and bank 35 have the same supply voltage
*this voltage is selected via JP28.
This configuration is in accordance with default routing of signals used for FMC connector.
====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====
{| class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP25.1-2
! style="text-align: center; font-weight: bold;" | JP25.3-4
! style="text-align: center; font-weight: bold;" | JP25.5-6
! style="text-align: center; font-weight: bold;" | JP25.7-8
! style="text-align: center; font-weight: bold;" | JP25.9-10
! style="text-align: center; font-weight: bold;" | JP25.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 2.5
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
 
{| class="wikitable" style="text-align: center;"
|+Bank #35 (HP)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP27.1-2
! style="text-align: center; font-weight: bold;" | JP27.3-4
! style="text-align: center; font-weight: bold;" | JP27.5-6
! style="text-align: center; font-weight: bold;" | JP27.7-8
! style="text-align: center; font-weight: bold;" | JP27.9-10
! style="text-align: center; font-weight: bold;" | JP27.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|}
 
{| class="wikitable" style="text-align: center;"
|+Bank #34 (HP)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP28.1-2
! style="text-align: center; font-weight: bold;" | JP28.3-4
! style="text-align: center; font-weight: bold;" | JP28.5-6
! style="text-align: center; font-weight: bold;" | JP28.7-8
! style="text-align: center; font-weight: bold;" | JP28.9-10
! style="text-align: center; font-weight: bold;" | JP28.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
 
====Examples of valid combinations for Zynq 7015-based SOMs====
{| class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP25.1-2
! style="text-align: center; font-weight: bold;" | JP25.3-4
! style="text-align: center; font-weight: bold;" | JP25.5-6
! style="text-align: center; font-weight: bold;" | JP25.7-8
! style="text-align: center; font-weight: bold;" | JP25.9-10
! style="text-align: center; font-weight: bold;" | JP25.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 2.5
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
 
{| class="wikitable" style="text-align: center;"
|+Bank #35 (HR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP27.1-2
! style="text-align: center; font-weight: bold;" | JP27.3-4
! style="text-align: center; font-weight: bold;" | JP27.5-6
! style="text-align: center; font-weight: bold;" | JP27.7-8
! style="text-align: center; font-weight: bold;" | JP27.9-10
! style="text-align: center; font-weight: bold;" | JP27.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 2.5
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
 
|}
 
{| class="wikitable" style="text-align: center;"
|+Bank #34 (HR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
! style="text-align: center; font-weight: bold;" | JP28.1-2
! style="text-align: center; font-weight: bold;" | JP28.3-4
! style="text-align: center; font-weight: bold;" | JP28.5-6
! style="text-align: center; font-weight: bold;" | JP28.7-8
! style="text-align: center; font-weight: bold;" | JP28.9-10
! style="text-align: center; font-weight: bold;" | JP28.11-12
|-
| style="text-align: center;" | 1.2
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 1.8
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 2.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|-
| style="text-align: center;" | 3.3
| style="text-align: center;" | '''closed'''
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
| style="text-align: center;" | open
|}
 
====Advanced information about voltage selection connectors====
===== Bank 13 VDDIO selection connector (JP25) =====
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -
|-
|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -
|-
|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -
|-
|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -
|-
|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -
|-
|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -
|-
|1, 3, 5, 7, 9, 11 || DGND|| - || -
|-
|}
 
The jumper configurations are:
# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
 
The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
 
===== Bank 35 VDDIO selection connector (JP27) =====
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -
|-
|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -
|-
|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -
|-
|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -
|-
|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -
|-
|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -
|-
|1, 3, 5, 7, 9, 11 || DGND|| - || -
|-
|}
 
The jumper configurations are:
# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV
 
The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
 
{{ImportantMessage|text=Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10.<br>
Then, check and/or properly configure JP27 for selecting the required VDDIO_BANK35}}
 
===== Bank 34 and VADJ VDDIO selection connector (JP28) =====
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -
|-
|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -
|-
|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -
|-
|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -
|-
|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -
|-
|12 || RFU|| Reserved || -
|-
|1, 3, 5, 7, 9, 11 || DGND|| - || -
|-
|}
 
The jumper configurations are:
# Jumper on 1-2 -> supply VADJ with 3.3V
# Jumper on 3-4 -> supply VADJ with 2.5V
# Jumper on 5-6 -> supply VADJ with 1.8V
# Jumper on 7-8 -> supply VADJ with 1.5V
# Jumper on 9-10 -> supply VADJ with 1.2V
 
The default configuration is:
# Jumper on 5-6 -> supply VADJ with 1.8V
<section end=Voltage selections/>
 
<section begin=SOM/>
 
==SoM's signals mapping==
===Bora Lite===
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''.
 
{| class="wikitable"
|+
! colspan="2" |SoM's signal
! colspan="6" |Routing options at carrier board level
|-
! rowspan="2" |Bank
! rowspan="2" |Name
! colspan="3" |Option #1
(default)
! colspan="3" |Option #2
|-
!Name
!Pin
!Note
!Name
!Pin
!Note
|-
| rowspan="54" |34
| rowspan="2" |IO_0_34
| rowspan="2" |'''IO_0_VRN_34'''
|J31.2
|Header
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J27D.H2
|FMC conn.
|-
| rowspan="2" |IO_25_34
| rowspan="2" |'''IO_25_VRP_35'''
|J31.4
|Header
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J27B.D1
|FMC conn.
|-
|IO_L10N_T1_34
|IO_L10N_T1_34
|J27D.H26
|FMC conn.
|
|
|
|-
|IO_L10P_T1_34
|IO_L10P_T1_34
|J27D.H25
|FMC conn.
|
|
|
|-
|IO_L11N_T1_SRCC_34
|IO_L11N_T1_SRCC_34
|J27D.G3
|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_34
|IO_L11P_T1_SRCC_34
|J27D.G2
|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_34
|IO_L12N_T1_MRCC_34
|J27D.H5
|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_34
|IO_L12P_T1_MRCC_34
|J27D.H4
|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_34
|'''IO_L13N_T1_MRCC_34'''
|J27D.G7
|FMC conn.
|
|
|
|-
|IO_L13P_T2_MRCC_34
|'''IO_L13P_T1_MRCC_34'''
|J27D.G6
|FMC conn.
|
|
|
|-
|IO_L14N_T2_SRCC_34
|IO_L14N_T2_SRCC_34
|J27B.D9
|FMC conn.
|
|
|
|-
|IO_L14P_T2_SRCC_34
|IO_L14P_T2_SRCC_34
|J27B.D8
|FMC conn.
|
|
|
|-
|IO_L15N_T2_DQS_34
|IO_L15N_T2_DQS_34
|J27B.D21
|FMC conn.
|
|
|
|-
|IO_L15P_T2_DQS_34
|IO_L15P_T2_DQS_34
|J27B.D20
|FMC conn.
|
|
|
|-
|IO_L16N_T2_34
|IO_L16N_T2_34
|J27B.C23
|FMC conn.
|
|
|
|-
|IO_L16P_T2_34
|IO_L16P_T2_34
|J27B.C22
|FMC conn.
|
|
|
|-
|IO_L17N_T2_34
|IO_L17N_T2_34
|J27D.G22
|FMC conn.
|
|
|
|-
|IO_L17P_T2_34
|IO_L17P_T2_34
|J27D.G21
|FMC conn.
|
|
|
|-
|IO_L18N_T2_34
|IO_L18N_T2_34
|J27D.H20
|FMC conn.
|
|
|
|-
|IO_L18P_T2_34
|IO_L18P_T2_34
|J27D.H19
|FMC conn.
|
|
|
|-
| rowspan="2" |IO_L19N_T3_VREF_34
| rowspan="2" |IO_L19N_T3_VREF_34
|J27D.G19
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP21
|TP SMD
|-
|IO_L19P_T3_34
|n/a
|n/a
|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L1N_T0_34
|IO_L1N_T0_34
|J27B.C19
|FMC conn.
|
|
|
|-
|IO_L1P_T0_34
|IO_L1P_T0_34
|J27B.C18
|FMC conn.
|
|
|
|-
|IO_L20N_T3_34
|IO_L20N_T3_34
|J27B.D18
|FMC conn.
|
|
|
|-
|IO_L20P_T3_34
|IO_L20P_T3_34
|J27B.D17
|FMC conn.
|
|
|
|-
|IO_L21N_T3_DQS_34
|IO_L21N_T3_DQS_34
|J27D.H17
|FMC conn.
|
|
|
|-
|IO_L21P_T3_DQS_34
|IO_L21P_T3_DQS_34
|J27D.H16
|FMC conn.
|
|
|
|-
|IO_L22N_T3_34
|IO_L22N_T3_34
|J27D.G16
|FMC conn.
|
|
|
|-
|IO_L22P_T3_34
|IO_L22P_T3_34
|J27D.G15
|FMC conn.
|
|
|
|-
|IO_L23N_T3_34
|IO_L23N_T3_34
|J27B.C11
|FMC conn.
|
|
|
|-
|IO_L23P_T3_34
|IO_L23P_T3_34
|J27B.C10
|FMC conn.
|
|
|
|-
|IO_L24N_T3_34
|IO_L24N_T3_34
|J27D.H23
|FMC conn.
|
|
|
|-
|IO_L24P_T3_34
|IO_L24P_T3_34
|J27D.H22
|FMC conn.
|
|
|
|-
|IO_L2N_T0_34
|IO_L2N_T0_34
|J27B.C15
|FMC conn.
|
|
|
|-
|IO_L2P_T0_34
|IO_L2P_T0_34
|J27B.C14
|FMC conn.
|
|
|
|-
|IO_L3N_T0_DQS_34
|IO_L3N_T0_DQS_34
|J27D.G13
|FMC conn.
|
|
|
|-
|IO_L3P_T0_DQS_PUDC_B_34
(10K pull-up on SoM)
|IO_L3P_T0_DQS_PUDC_B_34
|J27D.G12
|FMC conn.
|
|
|
|-
|IO_L4N_T0_34
|IO_L4N_T0_34
|J27D.G10
|FMC conn.
|
|
|
|-
|IO_L4P_T0_34
|IO_L4P_T0_34
|J27D.G9
|FMC conn.
|
|
|
|-
|IO_L5N_T0_34
|IO_L5N_T0_34
|J27D.H11
|FMC conn.
|
|
|
|-
|IO_L5P_T0_34
|IO_L5P_T0_34
|J27D.H10
|FMC conn.
|
|
|
|-
| rowspan="2" |IO_L6N_T0_VREF_34
| rowspan="2" |IO_L6N_T0_VREF_34
|J27B.D15
|FMC conn.
|
|
|
|-
|TP22
|TP SMD
|
|
|
|-
|IO_L6P_T0_34
|n/a
|n/a
|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.
|
|
|
|-
|IO_L7N_T1_34
|IO_L7N_T1_34
|J27D.H8
|FMC conn.
|
|
|
|-
|IO_L7P_T1_34
|IO_L7P_T1_34
|J27D.H7
|FMC conn.
|
|
|
|-
|IO_L8N_T1_34
|IO_L8N_T1_34
|J27D.H14
|FMC conn.
|
|
|
|-
|IO_L8P_T1_34
|IO_L8P_T1_34
|J27D.H13
|FMC conn.
|
|
|
|-
|IO_L9N_T1_DQS_34
|IO_L9N_T1_DQS_34
|J27B.D12
|FMC conn.
|
|
|
|-
|IO_L9P_T1_DQS_34
|IO_L9P_T1_DQS_34
|J27B.D11
|FMC conn.
|
|
|
|-
|
|
|
|
|
|
|
|
|-
| rowspan="54" |35
| rowspan="2" |IO_0_35
| rowspan="2" |'''IO_0_VRN_35'''
|J27C.F1
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J31.1
|Header
|-
| rowspan="2" |IO_25_35
| rowspan="2" |'''IO_25_VRP_35'''
|J27E.K13
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|J31.3
|Header
|-
|IO_L10N_T1_AD11N_35
|IO_L10N_T1_AD11N_35
|J27D.G34
|FMC conn.
|FPGA_BANK35_AD11N
|JP32.3
|Header
|-
|IO_L10P_T1_AD11P_35
|IO_L10P_T1_AD11P_35
|J27D.G33
|FMC conn.
|FPGA_BANK35_AD11P
|JP32.1
|Header
|-
|IO_L11N_T1_SRCC_35
|IO_L11N_T1_SRCC_35
|J27E.J3
|FMC conn.
|
|
|
|-
|IO_L11P_T1_SRCC_35
|IO_L11P_T1_SRCC_35
|J27E.J2
|FMC conn.
|
|
|
|-
|IO_L12N_T1_MRCC_35
|IO_L12N_T1_MRCC_35
|J27E.K5
|FMC conn.
|
|
|
|-
|IO_L12P_T1_MRCC_35
|IO_L12P_T1_MRCC_35
|J27E.K4
|FMC conn.
|
|
|
|-
|IO_L13N_T2_MRCC_35
|IO_L13N_T2_MRCC_35
|J27C.F5
|FMC conn.
|
|
|
|-
|IO_L13P_T2_MRCC_35
|IO_L13P_T2_MRCC_35
|J27C.F4
|FMC conn.
|
|
|
|-
|IO_L14N_T2_AD4N_SRCC_35
|IO_L14N_T2_AD4N_SRCC_35
|J27C.E3
|FMC conn.
|FPGA_BANK35_AD4N
|JP30.16
|Header
|-
|IO_L14P_T2_AD4P_SRCC_35
|IO_L14P_T2_AD4P_SRCC_35
|J27C.E2
|FMC conn.
|FPGA_BANK35_AD4P
|JP30.14
|Header
|-
|IO_L15N_T2_DQS_AD12N_35
|IO_L15N_T2_DQS_AD12N_35
|J27D.H38
|FMC conn.
|FPGA_BANK35_AD12N
|JP32.8
|Header
|-
|IO_L15P_T2_DQS_AD12P_35
|IO_L15P_T2_DQS_AD12P_35
|J27D.H37
|FMC conn.
|FPGA_BANK35_AD12P
|JP32.6
|Header
|-
|IO_L16N_T2_35
|IO_L16N_T2_35
|J27D.G37
|FMC conn.
|
|
|
|-
|IO_L16P_T2_35
|IO_L16P_T2_35
|J27D.G36
|FMC conn.
|
|
|
|-
|IO_L17N_T2_AD5N_35
|IO_L17N_T2_AD5N_35
|J27E.K8
|FMC conn.
|FPGA_BANK35_AD5N
|JP31.1
|Header
|-
|IO_L17P_T2_AD5P_35
|IO_L17P_T2_AD5P_35
|J27E.K7
|FMC conn.
|FPGA_BANK35_AD5P
|JP30.15
|Header
|-
|IO_L18N_T2_AD13N_35
|IO_L18N_T2_AD13N_35
|J27E.J7
|FMC conn.
|FPGA_BANK35_AD13N
|JP32.9
|Header
|-
|IO_L18P_T2_AD13P_35
|IO_L18P_T2_AD13P_35
|J27E.J6
|FMC conn.
|FPGA_BANK35_AD13P
|JP32.7
|Header
|-
| rowspan="2" |IO_L19N_T3_VREF_35
| rowspan="2" |IO_L19N_T3_VREF_35
|J27C.F8
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP24
|TP SMD
|-
|IO_L19P_T3_35
|IO_L19P_T3_35
|J27C.F7
|FMC conn.
|
|
|
|-
|IO_L1N_T0_AD0N_35
|IO_L1N_T0_AD0N_35
|J27D.G25
|FMC conn.
|FPGA_BANK35_AD0P
|JP30.4
|Header
|-
|IO_L1P_T0_AD0P_35
|IO_L1P_T0_AD0P_35
|J27D.G24
|FMC conn.
|FPGA_BANK35_AD0N
|JP30.2
|Header
|-
|IO_L20N_T3_AD6N_35
|IO_L20N_T3_AD6N_35
|J27C.E7
|FMC conn.
|FPGA_BANK35_AD6N
|JP31.6
|Header
|-
|IO_L20P_T3_AD6P_35
|IO_L20P_T3_AD6P_35
|J27C.E6
|FMC conn.
|FPGA_BANK35_AD6P
|JP31.4
|Header
|-
|IO_L21N_T3_DQS_AD14N_35
|IO_L21N_T3_DQS_AD14N_35
|J27E.K11
|FMC conn.
|FPGA_BANK35_AD14N
|JP32.14
|Header
|-
|IO_L21P_T3_DQS_AD14P_35
|IO_L21P_T3_DQS_AD14P_35
|J27E.K10
|FMC conn.
|FPGA_BANK35_AD14P
|JP32.12
|Header
|-
|IO_L22N_T3_AD7N_35
|IO_L22N_T3_AD7N_35
|J27E.J10
|FMC conn.
|FPGA_BANK35_AD7N
|JP31.7
|Header
|-
|IO_L22P_T3_AD7P_35
|IO_L22P_T3_AD7P_35
|J27E.J9
|FMC conn.
|FPGA_BANK35_AD7P
|JP31.5
|Header
|-
|IO_L23N_T3_35
|IO_L23N_T3_35
|J27C.F11
|FMC conn.
|
|
|
|-
|IO_L23P_T3_35
|IO_L23P_T3_35
|J27C.F10
|FMC conn.
|
|
|
|-
|IO_L24N_T3_AD15N_35
|IO_L24N_T3_AD15N_35
|J27C.E10
|FMC conn.
|FPGA_BANK35_AD15N
|JP32.15
|Header
|-
|IO_L24P_T3_AD15P_35
|IO_L24P_T3_AD15P_35
|J27C.E9
|FMC conn.
|FPGA_BANK35_AD15P
|JP32.13
|Header
|-
|IO_L2N_T0_AD8N_35
|IO_L2N_T0_AD8N_35
|J27B.D24
|FMC conn.
|FPGA_BANK35_AD8N
|JP31.12
|Header
|-
|IO_L2P_T0_AD8P_35
|IO_L2P_T0_AD8P_35
|J27B.D23
|FMC conn.
|FPGA_BANK35_AD8P
|JP31.10
|Header
|-
|IO_L3N_T0_DQS_AD1N_35
|IO_L3N_T0_DQS_AD1N_35
|J27D.H29
|FMC conn.
|FPGA_BANK35_AD1N
|JP30.5
|Header
|-
|IO_L3P_T0_DQS_AD1P_35
|IO_L3P_T0_DQS_AD1P_35
|J27D.H28
|FMC conn.
|FPGA_BANK35_AD1P
|JP30.3
|Header
|-
|IO_L4N_T0_35
|IO_L4N_T0_35
|J27D.G28
|FMC conn.
|
|
|
|-
|IO_L4P_T0_35
|IO_L4P_T0_35
|J27D.G27
|FMC conn.
|
|
|
|-
|IO_L5N_T0_AD9N_35
|IO_L5N_T0_AD9N_35
|J27B.D27
|FMC conn.
|FPGA_BANK35_AD9N
|JP31.13
|Header
|-
|IO_L5P_T0_AD9P_35
|IO_L5P_T0_AD9P_35
|J27B.D26
|FMC conn.
|FPGA_BANK35_AD9P
|JP31.11
|Header
|-
| rowspan="2" |IO_L6N_T0_VREF_35
| rowspan="2" |IO_L6N_T0_VREF_35
|J27B.C27
|FMC conn.
| rowspan="2" |
| rowspan="2" |
| rowspan="2" |
|-
|TP23
|TP SMD
|-
|IO_L6P_T0_35
|IO_L6P_T0_35
|J27B.C26
|FMC conn.
|
|
|
|-
|IO_L7N_T1_AD2N_35
|IO_L7N_T1_AD2N_35
|J27D.H32
|FMC conn.
|FPGA_BANK35_AD2N
|JP30.10
|Header
|-
|IO_L7P_T1_AD2P_35
|IO_L7P_T1_AD2P_35
|J27D.H31
|FMC conn.
|FPGA_BANK35_AD2P
|JP30.8
|Header
|-
|IO_L8N_T1_AD10N_35
|IO_L8N_T1_AD10N_35
|J27D.G31
|FMC conn.
|FPGA_BANK35_AD10N
|JP32.2
|Header
|-
|IO_L8P_T1_AD10P_35
|IO_L8P_T1_AD10P_35
|J27D.G30
|FMC conn.
|FPGA_BANK35_AD10P
|JP31.16
|Header
|-
|IO_L9N_T1_DQS_AD3N_35
|IO_L9N_T1_DQS_AD3N_35
|J27D.H35
|FMC conn.
|FPGA_BANK35_AD3N
|JP30.11
|Header
|-
|IO_L9P_T1_DQS_AD3P_35
|IO_L9P_T1_DQS_AD3P_35
|J27D.H34
|FMC conn.
|FPGA_BANK35_AD3P
|JP30.9
|Header
|-
|
|
|
|
|
|
|
|
|-
| rowspan="26" |13
'''(not available on Zynq 7007S and 7010)'''
|IO_L11P_T1_SRCC_13
|'''IO_L23P_T3_13'''
|JP17.3
|PMOD [A]
|
|
|
|-
|IO_L11N_T1_SRCC_13
|'''IO_L23N_T3_13'''
|JP17.4
|PMOD [A]
|
|
|
|-
|IO_L12P_T1_MRCC_13
|'''IO_L9P_T1_DQS_13'''
|JP17.2
|PMOD [A]
|IO_L9P_T1_DQS_13
|J30.1
|ONE PIECE
|-
|IO_L12N_T1_MRCC_13
|'''IO_L9N_T1_DQS_13'''
|JP17.1
|PMOD [A]
|IO_L9N_T1_DQS_13
|J30.3
|ONE PIECE
|-
|IO_L13P_T2_MRCC_13
|'''IO_L7P_T1_13'''
|JP17.7
|PMOD [A]
|IO_L7P_T1_13
|J30.24
|ONE PIECE
|-
|IO_L13N_T2_MRCC_13
|'''IO_L7N_T1_13'''
|JP17.8
|PMOD [A]
|IO_L7N_T1_13
|J30.26
|ONE PIECE
|-
|IO_L14P_T2_SRCC_13
|'''IO_L15P_T2_DQS_13'''
|n/a
|ETH1_RXCK
|IO_L15P_T2_DQS_13
|J30.25
|ONE PIECE
|-
|IO_L14N_T2_SRCC_13
|'''IO_L15N_T2_DQS_13'''
|n/a
|ETH1_RXCTL
|IO_L15N_T2_DQS_13
|J30.27
|ONE PIECE
|-
|IO_L15P_T2_DQS_13
|'''IO_L5P_T0_13'''
|JP17.6
|PMOD [A]
|IO_L5P_T0_13
|J30.20
|ONE PIECE
|-
|IO_L15N_T2_DQS_13
|'''IO_L5N_T0_13'''
|JP17.5
|PMOD [A]
|IO_L5N_T0_13
|J30.18
|ONE PIECE
|-
|IO_L16N_T2_13
|IO_L16N_T2_13
|n/a
|ETH1_TXCTL
|IO_L16N_T2_13
|J30.31
|ONE PIECE
|-
|IO_L16P_T2_13
|IO_L16P_T2_13
|n/a
|ETH1_TXCK
|IO_L16P_T2_13
|J30.29
|ONE PIECE
|-
|IO_L17N_T2_13
|IO_L17N_T2_13
|n/a
|ETH1_RXD1
|IO_L17N_T2_13
|J30.35
|ONE PIECE
|-
|IO_L17P_T2_13
|IO_L17P_T2_13
|n/a
|ETH1_RXD0
|IO_L17P_T2_13
|J30.33
|ONE PIECE
|-
|IO_L18N_T2_13
|IO_L18N_T2_13
|n/a
|ETH1_RXD3
|IO_L18N_T2_13
|J30.39
|ONE PIECE
|-
|IO_L18P_T2_13
|IO_L18P_T2_13
|n/a
|ETH1_RXD2
|IO_L18P_T2_13
|J30.37
|ONE PIECE
|-
|IO_L19N_T3_VREF_13
|IO_L19N_T3_VREF_13
|n/a
|ETH1_TXD1
|IO_L19N_T3_VREF_13
|J30.43
|ONE PIECE
|-
|IO_L19P_T3_13
|IO_L19P_T3_13
|n/a
|ETH1_TXD0
|IO_L19P_T3_13
|J30.41
|ONE PIECE
|-
|IO_L20N_T3_13
|IO_L20N_T3_13
|n/a
|ETH1_TXD3
|IO_L20N_T3_13
|J30.47
|ONE PIECE
|-
|IO_L20P_T3_13
|IO_L20P_T3_13
|n/a
|ETH1_TXD2
|IO_L20P_T3_13
|J30.45
|ONE PIECE
|-
|IO_L21N_T3_DQS_13
|IO_L21N_T3_DQS_13
|n/a
|ETH1_MDC
|IO_L21N_T3_DQS_13
|J30.51
|ONE PIECE
|-
|IO_L21P_T3_DQS_13
|IO_L21P_T3_DQS_13
|n/a
|ETH1_MDIO
|IO_L21P_T3_DQS_13
|J30.49
|ONE PIECE
|-
|IO_L22N_T3_13
|IO_L22N_T3_13
|
|
|IO_L22N_T3_13
|J30.55
|ONE PIECE
|-
|IO_L22P_T3_13
|IO_L22P_T3_13
|n/a
|DWM_WIFI_IRQ
|IO_L22P_T3_13
|J30.53
|ONE PIECE
|-
| rowspan="2" |IO_L6N_T0_VREF_13
| rowspan="2" |IO_L6N_T0_VREF_13
|JP23.3
|PMOD [B]
| rowspan="2" |IO_L6N_T0_VREF_13
| rowspan="2" |J30.30
| rowspan="2" |ONE PIECE
|-
|n/a
|USB1_OC
|}
 
==== BoraXEVB unavailable signals ====
Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector.
 
{| class="wikitable"
|+
BoraXEVB's signal that are not available when mated with Bora Lite SoM
!Bank
!Carrier's signal
|-
|13
|IO_25_13
|-
|13
|IO_L1P_T0_13
|-
|13
|IO_L1N_T0_13
|-
|13
|IO_L2P_T0_13
|-
|13
|IO_L2N_T0_13
|-
|13
|IO_L3P_T0_DQS_13
|-
|13
|IO_L3N_T0_DQS_13
|-
|13
|IO_L4P_T0_13
|-
|13
|IO_L4N_T0_13
|-
|500
|NAND_CS0/SPI0_CS1
|-
|500
|NAND_IO3
|-
|500
|NAND_IO4
|-
|500
|NAND_IO5
|-
|500
|NAND_IO6
|-
|500
|NAND_IO7
|-
|500
|NAND_RD_B/VCFG1
|-
|500
|NAND_CLE/VCFG0
|}
<section end=SOM/>
 
<section begin=Schematics/>
==Schematics==
* ORCAD: [https://www.dave.eu/links/p/yYW9VNsGutz6V0dd BORAXEVB-1.6.1-BELK-dsn.zip]
* PDF : [https://www.dave.eu/links/p/hClB4N7blBdSG6AH BoraXEVB-S-EVBBX0000C0R-1.6.1.pdf]
===BOM===* ORCADBoraXEVB: http[https://www.dave.eu/system/fileslinks/area-riservatap/boraxevb-1PU08ewKLvX9Z9tZJ BORAXEVB_S.0.3-BELK-dsnEVBBX0000C0R.zip* PDF : http://www.dave.eu/system/files/area-riservata/BoraXEVB-S-EVBBX0000C0R-1.26.0.pdfCSV.zip]
==BOM=Layout===* BoraXEVB: http[https://www.dave.eu/systemlinks/filesp/area-riservata/boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV_.zipcPT5UVAFNiSzj4NR CS143714 Assembly view]
==Layout=PCB design (Mentor PADS)===* http[https://www.dave.eu/systemlinks/p/filesBCTblnPPoDiwPrAE CS143714]<section end=Schematics/area-riservata><section begin=Mechanicals/boraxevb-CS143714_assembly_view.pdf>
==Mechanical==
* DXF: http[https://www.dave.eu/systemlinks/filesp/areas1k5AXL3AiCIo7Fj boraxevb-riservata/boraxevb_2D_CS143714.zip2D-CS143714]* IDF (3D): http[https://www.dave.eu/systemlinks/filesp/areaxeQvq2IvKig5vlfd boraxevb-3D-riservataCS143714]* STEP (3D): [https:/boraxevb_3D_CS143714/www.dave.zipeu/links/p/cj2s2AlBHkeY7tJ7 boraxevb_3D_step_cs143714]<section end=Mechanicals/>
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