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BoraXEVB

14,651 bytes added, 17:18, 25 January 2021
→‎Block Diagram
{{InfoBoxTop}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
 
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/>
==Block Diagram==
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].
 
====BoraX====
[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
 
====Bora Lite====
[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
 
<section end=Block Diagram/>
== Features ==
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress module]].
<section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
 
<section begin=Reset button/>
 
=== Reset button - S6 ===
 
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
 
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
|}
<b>(*)</b> Boot mode from NAND in not supported '''ONLY''' on actual BSP version[[:Category:BoraLite |BoraLite]] SOM module <section end=Boot Configurations/>  <section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/>
<section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
<section end=Ethernet1/>
=== BANK's Power GOOD signals - J28 ===
|-
|}
 
<section begin=JTAG/>
=== JTAG ===
|-
|}
<section end=JTAG/>
<section begin=Console/>
=== UART1 - J17 ===
|-
|}
<section end=Console/>
<section begin=USB OTG/>
=== USB OTG - J19 ===
|-
|}
<section end=USB OTG/>
<section begin=micro SD/>
=== MicroSD - J21 ===
|8 ||PS_SD0_DAT1||| - || -
|-
|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
|-
|}
<section end=DWM/>
<section begin=CAN/>
=== CAN - J24 ===
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
|-
|}
<section end=CAN/>
<section begin=Touchscreen/>
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
|-
|}
<section end=Touchscreen/>
<section begin=LVDS/>
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|-
|}
<section end=LVDS/>
<section begin=FMC/>
=== FPGA Mezzanine Card (FMC) Connector - J27 ===
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
| K40||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
|}
<section end=FMC/>
=== Pin strip connectors ===
|-
|}
 
==== Ethernet GPIO - JP18 ====
|-
|}
 
==== SPI,NAND - JP19 ====
|}
<section begin=RTC/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/>
==== AUX PINs - JP29 ====
|}
<section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
|-
|}
 
==== Digilent Pmod™ Compatible - JP23 ====
|-
|}
<section end=PMOD/>
 
===JP27, JP27 and JP28===
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
{|class="wikitable" style="text-align: center;"! rowspan="2" |SoM
! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34
| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
| rowspan="2" |BoraX
| style="text-align: center;" | 7015
(CLG485 package)
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
 
===BoraXEVB voltage selection jumpers===
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
 
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
 
Even if PL's banks are independent, default configuration of BoraXEVB is such that
*bank 34 and bank 35 have the same supply voltage
*this voltage is selected via JP28.
This configuration is in accordance with default routing of signals used for FMC connector.
====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====
{|class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
! | rowspan="2" |Bora Lite| style="text-align: center; font-weight: bold;" | Nominal voltage [V]7007S/7010! (CLG400 package)| style="text-align: center; font-weight: bold;" | JP25HR(1.12 -23.3V)! | style="text-align: center; font-weight: bold;" | JP25.3-4User defined! | style="text-align: center; font-weight: bold;" | JP25HR(1.52 -63.3V)! | style="text-align: center; font-weight: bold;" | JP25.7-8User defined! | style="text-align: center; font-weight: bold;" | JP25HR(1.92 -103.3V)! | style="text-align: center; font-weight: bold;" | JP25.11-12User defined
|-
| style="text-align: center;" | 7014S/7020(CLG400 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|}[1]*HR = High Range*HP = High Performance ===BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''. Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details. Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5
| style="text-align: center;" | open
| style="text-align: center;" | '''closed'''
|}
 {|class="wikitable" style="text-align: center;"
|+Bank #35 (HP)
|-
|}
 {|class="wikitable" style="text-align: center;"
|+Bank #34 (HP)
|-
====Examples of valid combinations for Zynq 7015-based SOMs====
{|class="wikitable" style="text-align: center;"
|+Bank #13 (HR)
|-
|}
 {|class="wikitable" style="text-align: center;"
|+Bank #35 (HR)
|-
|}
 {|class="wikitable" style="text-align: center;"|+Bank #34 (HPHR)
|-
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V <section begin=SOM/> ==SoM's signals mapping=====Bora Lite===As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''. {| class="wikitable"|+! colspan="2" |SoM's signal! colspan="6" |Routing options at carrier board level|-! rowspan="2" |Bank! rowspan="2" |Name! colspan="3" |Option #1(default)! colspan="3" |Option #2|-!Name!Pin!Note!Name!Pin!Note|-| rowspan="54" |34| rowspan="2" |IO_0_34| rowspan="2" |'''IO_0_VRN_34'''|J31.2|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27D.H2|FMC conn.|-| rowspan="2" |IO_25_34| rowspan="2" |'''IO_25_VRP_35'''|J31.4|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27B.D1|FMC conn.|-|IO_L10N_T1_34|IO_L10N_T1_34|J27D.H26|FMC conn.||||-|IO_L10P_T1_34|IO_L10P_T1_34|J27D.H25|FMC conn.||||-|IO_L11N_T1_SRCC_34|IO_L11N_T1_SRCC_34|J27D.G3|FMC conn.||||-|IO_L11P_T1_SRCC_34|IO_L11P_T1_SRCC_34|J27D.G2|FMC conn.||||-|IO_L12N_T1_MRCC_34|IO_L12N_T1_MRCC_34|J27D.H5|FMC conn.||||-|IO_L12P_T1_MRCC_34|IO_L12P_T1_MRCC_34|J27D.H4|FMC conn.||||-|IO_L13N_T2_MRCC_34|'''IO_L13N_T1_MRCC_34'''|J27D.G7|FMC conn.||||-|IO_L13P_T2_MRCC_34|'''IO_L13P_T1_MRCC_34'''|J27D.G6|FMC conn.||||-|IO_L14N_T2_SRCC_34|IO_L14N_T2_SRCC_34|J27B.D9|FMC conn.||||-|IO_L14P_T2_SRCC_34|IO_L14P_T2_SRCC_34|J27B.D8|FMC conn.||||-|IO_L15N_T2_DQS_34|IO_L15N_T2_DQS_34|J27B.D21|FMC conn.||||-|IO_L15P_T2_DQS_34|IO_L15P_T2_DQS_34|J27B.D20|FMC conn.||||-|IO_L16N_T2_34|IO_L16N_T2_34|J27B.C23|FMC conn.||||-|IO_L16P_T2_34|IO_L16P_T2_34|J27B.C22|FMC conn.||||-|IO_L17N_T2_34|IO_L17N_T2_34|J27D.G22|FMC conn.||||-|IO_L17P_T2_34|IO_L17P_T2_34|J27D.G21|FMC conn.||||-|IO_L18N_T2_34|IO_L18N_T2_34|J27D.H20|FMC conn.||||-|IO_L18P_T2_34|IO_L18P_T2_34|J27D.H19|FMC conn.||||-| rowspan="2" |IO_L19N_T3_VREF_34| rowspan="2" |IO_L19N_T3_VREF_34|J27D.G19|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP21|TP SMD|-|IO_L19P_T3_34|n/a|n/a|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L1N_T0_34|IO_L1N_T0_34|J27B.C19|FMC conn.||||-|IO_L1P_T0_34|IO_L1P_T0_34|J27B.C18|FMC conn.||||-|IO_L20N_T3_34|IO_L20N_T3_34|J27B.D18|FMC conn.||||-|IO_L20P_T3_34|IO_L20P_T3_34|J27B.D17|FMC conn.||||-|IO_L21N_T3_DQS_34|IO_L21N_T3_DQS_34|J27D.H17|FMC conn.||||-|IO_L21P_T3_DQS_34|IO_L21P_T3_DQS_34|J27D.H16|FMC conn.||||-|IO_L22N_T3_34|IO_L22N_T3_34|J27D.G16|FMC conn.||||-|IO_L22P_T3_34|IO_L22P_T3_34|J27D.G15|FMC conn.||||-|IO_L23N_T3_34|IO_L23N_T3_34|J27B.C11|FMC conn.||||-|IO_L23P_T3_34|IO_L23P_T3_34|J27B.C10|FMC conn.||||-|IO_L24N_T3_34|IO_L24N_T3_34|J27D.H23|FMC conn.||||-|IO_L24P_T3_34|IO_L24P_T3_34|J27D.H22|FMC conn.||||-|IO_L2N_T0_34|IO_L2N_T0_34|J27B.C15|FMC conn.||||-|IO_L2P_T0_34|IO_L2P_T0_34|J27B.C14|FMC conn.||||-|IO_L3N_T0_DQS_34|IO_L3N_T0_DQS_34|J27D.G13|FMC conn.||||-|IO_L3P_T0_DQS_PUDC_B_34(10K pull-up on SoM)|IO_L3P_T0_DQS_PUDC_B_34|J27D.G12|FMC conn.||||-|IO_L4N_T0_34|IO_L4N_T0_34|J27D.G10|FMC conn.||||-|IO_L4P_T0_34|IO_L4P_T0_34|J27D.G9|FMC conn.||||-|IO_L5N_T0_34|IO_L5N_T0_34|J27D.H11|FMC conn.||||-|IO_L5P_T0_34|IO_L5P_T0_34|J27D.H10|FMC conn.||||-| rowspan="2" |IO_L6N_T0_VREF_34| rowspan="2" |IO_L6N_T0_VREF_34|J27B.D15|FMC conn.||||-|TP22|TP SMD||||-|IO_L6P_T0_34|n/a|n/a|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L7N_T1_34|IO_L7N_T1_34|J27D.H8|FMC conn.||||-|IO_L7P_T1_34|IO_L7P_T1_34|J27D.H7|FMC conn.||||-|IO_L8N_T1_34|IO_L8N_T1_34|J27D.H14|FMC conn.||||-|IO_L8P_T1_34|IO_L8P_T1_34|J27D.H13|FMC conn.||||-|IO_L9N_T1_DQS_34|IO_L9N_T1_DQS_34|J27B.D12|FMC conn.||||-|IO_L9P_T1_DQS_34|IO_L9P_T1_DQS_34|J27B.D11|FMC conn.||||-|||||||||-| rowspan="54" |35| rowspan="2" |IO_0_35| rowspan="2" |'''IO_0_VRN_35'''|J27C.F1|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.1|Header|-| rowspan="2" |IO_25_35| rowspan="2" |'''IO_25_VRP_35'''|J27E.K13|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.3|Header|-|IO_L10N_T1_AD11N_35|IO_L10N_T1_AD11N_35|J27D.G34|FMC conn.|FPGA_BANK35_AD11N|JP32.3|Header|-|IO_L10P_T1_AD11P_35|IO_L10P_T1_AD11P_35|J27D.G33|FMC conn.|FPGA_BANK35_AD11P|JP32.1|Header|-|IO_L11N_T1_SRCC_35|IO_L11N_T1_SRCC_35|J27E.J3|FMC conn.||||-|IO_L11P_T1_SRCC_35|IO_L11P_T1_SRCC_35|J27E.J2|FMC conn.||||-|IO_L12N_T1_MRCC_35|IO_L12N_T1_MRCC_35|J27E.K5|FMC conn.||||-|IO_L12P_T1_MRCC_35|IO_L12P_T1_MRCC_35|J27E.K4|FMC conn.||||-|IO_L13N_T2_MRCC_35|IO_L13N_T2_MRCC_35|J27C.F5|FMC conn.||||-|IO_L13P_T2_MRCC_35|IO_L13P_T2_MRCC_35|J27C.F4|FMC conn.||||-|IO_L14N_T2_AD4N_SRCC_35|IO_L14N_T2_AD4N_SRCC_35|J27C.E3|FMC conn.|FPGA_BANK35_AD4N|JP30.16|Header|-|IO_L14P_T2_AD4P_SRCC_35|IO_L14P_T2_AD4P_SRCC_35|J27C.E2|FMC conn.|FPGA_BANK35_AD4P|JP30.14|Header|-|IO_L15N_T2_DQS_AD12N_35|IO_L15N_T2_DQS_AD12N_35|J27D.H38|FMC conn.|FPGA_BANK35_AD12N|JP32.8|Header|-|IO_L15P_T2_DQS_AD12P_35|IO_L15P_T2_DQS_AD12P_35|J27D.H37|FMC conn.|FPGA_BANK35_AD12P|JP32.6|Header|-|IO_L16N_T2_35|IO_L16N_T2_35|J27D.G37|FMC conn.||||-|IO_L16P_T2_35|IO_L16P_T2_35|J27D.G36|FMC conn.||||-|IO_L17N_T2_AD5N_35|IO_L17N_T2_AD5N_35|J27E.K8|FMC conn.|FPGA_BANK35_AD5N|JP31.1|Header|-|IO_L17P_T2_AD5P_35|IO_L17P_T2_AD5P_35|J27E.K7|FMC conn.|FPGA_BANK35_AD5P|JP30.15|Header|-|IO_L18N_T2_AD13N_35|IO_L18N_T2_AD13N_35|J27E.J7|FMC conn.|FPGA_BANK35_AD13N|JP32.9|Header|-|IO_L18P_T2_AD13P_35|IO_L18P_T2_AD13P_35|J27E.J6|FMC conn.|FPGA_BANK35_AD13P|JP32.7|Header|-| rowspan="2" |IO_L19N_T3_VREF_35| rowspan="2" |IO_L19N_T3_VREF_35|J27C.F8|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP24|TP SMD|-|IO_L19P_T3_35|IO_L19P_T3_35|J27C.F7|FMC conn.||||-|IO_L1N_T0_AD0N_35|IO_L1N_T0_AD0N_35|J27D.G25|FMC conn.|FPGA_BANK35_AD0P|JP30.4|Header|-|IO_L1P_T0_AD0P_35|IO_L1P_T0_AD0P_35|J27D.G24|FMC conn.|FPGA_BANK35_AD0N|JP30.2|Header|-|IO_L20N_T3_AD6N_35|IO_L20N_T3_AD6N_35|J27C.E7|FMC conn.|FPGA_BANK35_AD6N|JP31.6|Header|-|IO_L20P_T3_AD6P_35|IO_L20P_T3_AD6P_35|J27C.E6|FMC conn.|FPGA_BANK35_AD6P|JP31.4|Header|-|IO_L21N_T3_DQS_AD14N_35|IO_L21N_T3_DQS_AD14N_35|J27E.K11|FMC conn.|FPGA_BANK35_AD14N|JP32.14|Header|-|IO_L21P_T3_DQS_AD14P_35|IO_L21P_T3_DQS_AD14P_35|J27E.K10|FMC conn.|FPGA_BANK35_AD14P|JP32.12|Header|-|IO_L22N_T3_AD7N_35|IO_L22N_T3_AD7N_35|J27E.J10|FMC conn.|FPGA_BANK35_AD7N|JP31.7|Header|-|IO_L22P_T3_AD7P_35|IO_L22P_T3_AD7P_35|J27E.J9|FMC conn.|FPGA_BANK35_AD7P|JP31.5|Header|-|IO_L23N_T3_35|IO_L23N_T3_35|J27C.F11|FMC conn.||||-|IO_L23P_T3_35|IO_L23P_T3_35|J27C.F10|FMC conn.||||-|IO_L24N_T3_AD15N_35|IO_L24N_T3_AD15N_35|J27C.E10|FMC conn.|FPGA_BANK35_AD15N|JP32.15|Header|-|IO_L24P_T3_AD15P_35|IO_L24P_T3_AD15P_35|J27C.E9|FMC conn.|FPGA_BANK35_AD15P|JP32.13|Header|-|IO_L2N_T0_AD8N_35|IO_L2N_T0_AD8N_35|J27B.D24|FMC conn.|FPGA_BANK35_AD8N|JP31.12|Header|-|IO_L2P_T0_AD8P_35|IO_L2P_T0_AD8P_35|J27B.D23|FMC conn.|FPGA_BANK35_AD8P|JP31.10|Header|-|IO_L3N_T0_DQS_AD1N_35|IO_L3N_T0_DQS_AD1N_35|J27D.H29|FMC conn.|FPGA_BANK35_AD1N|JP30.5|Header|-|IO_L3P_T0_DQS_AD1P_35|IO_L3P_T0_DQS_AD1P_35|J27D.H28|FMC conn.|FPGA_BANK35_AD1P|JP30.3|Header|-|IO_L4N_T0_35|IO_L4N_T0_35|J27D.G28|FMC conn.||||-|IO_L4P_T0_35|IO_L4P_T0_35|J27D.G27|FMC conn.||||-|IO_L5N_T0_AD9N_35|IO_L5N_T0_AD9N_35|J27B.D27|FMC conn.|FPGA_BANK35_AD9N|JP31.13|Header|-|IO_L5P_T0_AD9P_35|IO_L5P_T0_AD9P_35|J27B.D26|FMC conn.|FPGA_BANK35_AD9P|JP31.11|Header|-| rowspan="2" |IO_L6N_T0_VREF_35| rowspan="2" |IO_L6N_T0_VREF_35|J27B.C27|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP23|TP SMD|-|IO_L6P_T0_35|IO_L6P_T0_35|J27B.C26|FMC conn.||||-|IO_L7N_T1_AD2N_35|IO_L7N_T1_AD2N_35|J27D.H32|FMC conn.|FPGA_BANK35_AD2N|JP30.10|Header|-|IO_L7P_T1_AD2P_35|IO_L7P_T1_AD2P_35|J27D.H31|FMC conn.|FPGA_BANK35_AD2P|JP30.8|Header|-|IO_L8N_T1_AD10N_35|IO_L8N_T1_AD10N_35|J27D.G31|FMC conn.|FPGA_BANK35_AD10N|JP32.2|Header|-|IO_L8P_T1_AD10P_35|IO_L8P_T1_AD10P_35|J27D.G30|FMC conn.|FPGA_BANK35_AD10P|JP31.16|Header|-|IO_L9N_T1_DQS_AD3N_35|IO_L9N_T1_DQS_AD3N_35|J27D.H35|FMC conn.|FPGA_BANK35_AD3N|JP30.11|Header|-|IO_L9P_T1_DQS_AD3P_35|IO_L9P_T1_DQS_AD3P_35|J27D.H34|FMC conn.|FPGA_BANK35_AD3P|JP30.9|Header|-|||||||||-| rowspan="26" |13'''(not available on Zynq 7007S and 7010)'''|IO_L11P_T1_SRCC_13|'''IO_L23P_T3_13'''|JP17.3|PMOD [A]||||-|IO_L11N_T1_SRCC_13|'''IO_L23N_T3_13'''|JP17.4|PMOD [A]||||-|IO_L12P_T1_MRCC_13|'''IO_L9P_T1_DQS_13'''|JP17.2|PMOD [A]|IO_L9P_T1_DQS_13|J30.1|ONE PIECE|-|IO_L12N_T1_MRCC_13|'''IO_L9N_T1_DQS_13'''|JP17.1|PMOD [A]|IO_L9N_T1_DQS_13|J30.3|ONE PIECE|-|IO_L13P_T2_MRCC_13|'''IO_L7P_T1_13'''|JP17.7|PMOD [A]|IO_L7P_T1_13|J30.24|ONE PIECE|-|IO_L13N_T2_MRCC_13|'''IO_L7N_T1_13'''|JP17.8|PMOD [A]|IO_L7N_T1_13|J30.26|ONE PIECE|-|IO_L14P_T2_SRCC_13|'''IO_L15P_T2_DQS_13'''|n/a|ETH1_RXCK|IO_L15P_T2_DQS_13|J30.25|ONE PIECE|-|IO_L14N_T2_SRCC_13|'''IO_L15N_T2_DQS_13'''|n/a|ETH1_RXCTL|IO_L15N_T2_DQS_13|J30.27|ONE PIECE|-|IO_L15P_T2_DQS_13|'''IO_L5P_T0_13'''|JP17.6|PMOD [A]|IO_L5P_T0_13|J30.20|ONE PIECE|-|IO_L15N_T2_DQS_13|'''IO_L5N_T0_13'''|JP17.5|PMOD [A]|IO_L5N_T0_13|J30.18|ONE PIECE|-|IO_L16N_T2_13|IO_L16N_T2_13|n/a|ETH1_TXCTL|IO_L16N_T2_13|J30.31|ONE PIECE|-|IO_L16P_T2_13|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE|-|IO_L17N_T2_13|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE|-|IO_L17P_T2_13|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE|-|IO_L18N_T2_13|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE|-|IO_L18P_T2_13|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE|-|IO_L19N_T3_VREF_13|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE|-|IO_L19P_T3_13|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|J30.41|ONE PIECE|-|IO_L20N_T3_13|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE|-|IO_L20P_T3_13|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE|-|IO_L21N_T3_DQS_13|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE|-|IO_L21P_T3_DQS_13|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE|-|IO_L22N_T3_13|IO_L22N_T3_13|||IO_L22N_T3_13|J30.55|ONE PIECE|-|IO_L22P_T3_13|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE|-| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |IO_L6N_T0_VREF_13|JP23.3|PMOD [B]| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |J30.30| rowspan="2" |ONE PIECE|-|n/a|USB1_OC|} ==== BoraXEVB unavailable signals ====Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector. {| class="wikitable"|+BoraXEVB's signal that are not available when mated with Bora Lite SoM!Bank!Carrier's signal
|-
|2 13|| LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -IO_25_13
|-
|4 13|| LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -IO_L1P_T0_13
|-
|6 13|| LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -IO_L1N_T0_13
|-
|8 13|| LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -IO_L2P_T0_13
|-
|10 13|| LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -IO_L2N_T0_13
|-
|12 13|| LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -IO_L3P_T0_DQS_13
|-
|1, 3, 5, 7, 9, 11 13|| DGND|| - || -IO_L3N_T0_DQS_13
|-
|}13 The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" IO_L4P_T0_13
|-
!Pin# |13!Pin name!Function!Notes|IO_L4N_T0_13
|-
|2 500|| VADJ_FB (22K)|| selects 3.3V VADJ || -NAND_CS0/SPI0_CS1
|-
|4 500|| VADJ_FB (30K9)|| selects 2.5V VADJ || -NAND_IO3
|-
|6 500|| VADJ_FB (51K1)|| selects 1.8V VADJ || -NAND_IO4
|-
|8 500|| VADJ_FB (68K)|| selects 1.5V VADJ || -NAND_IO5
|-
|10 500|| VADJ_FB (100K)|| selects 1.2V VADJ || -NAND_IO6
|-
|12 500|| RFU|| Reserved || -NAND_IO7
|-
|1, 3, 5, 7, 9, 11 500|| DGND|| - || -NAND_RD_B/VCFG1
|-
|500
|NAND_CLE/VCFG0
|}
<section end=SOM/>
The jumper configurations are:# Jumper on 1-2 -<section begin=Schematics/> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V
==Schematics==
==PCB design (Mentor PADS)==
* [[mirror:bora/hw/BoraXEVB/CS143714.zip|CS143714.zip]]
<section end=Schematics/>
<section begin=Mechanicals/>
==Mechanical==
* DXF: [[mirror:bora/hw/BoraXEVB/boraxevb-2D-CS143714.dxf.zip|boraxevb-2D-CS143714.dxf.zip]]
* IDF (3D): [[mirror:bora/hw/BoraXEVB/boraxevb-3D-CS143714.zip|boraxevb-3D-CS143714.zip]]
* STEP (3D): [[mirror:bora/hw/BoraXEVB/boraxevb_3D_step_cs143714.zip|boraxevb_3D_step_cs143714.zip]]
<section end=Mechanicals/>
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