Difference between revisions of "BoraLite Adapter for the BoraXEVB carrier board"

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== CAN ==
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==Routing options==
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[[BoraXEVB#SoM.27s_signals_mapping|This table]] helps to map Bora Lite's signals when it is mated with the [[BoraXEVB|BoraXEVB]] carrier board. '''That table assumes that the adapter is populated according to the default mounting option''', which is illustrated in the schematics available [[#Schematics|here]].
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At the adapter level, other mounting options are available, however. They are detailed in the following table.
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TBD
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== CAN bus ==
 
Pins IO_L6P_T0_34 and IO_L19P_T3_34 can be used as CAN_TX and CAN_RX for the CAN0 interface. The BoraLite adapter provide the [http://www.ti.com/lit/ds/symlink/sn65hvd230.pdf SN65HVD232] CAN bus transceiver required for proper CAN bus bus interface.
 
Pins IO_L6P_T0_34 and IO_L19P_T3_34 can be used as CAN_TX and CAN_RX for the CAN0 interface. The BoraLite adapter provide the [http://www.ti.com/lit/ds/symlink/sn65hvd230.pdf SN65HVD232] CAN bus transceiver required for proper CAN bus bus interface.
  
 
The CAN_L and CAN_H translated signals are routed to the J5.103 and J5.105 connector pins on BoraXEVB.
 
The CAN_L and CAN_H translated signals are routed to the J5.103 and J5.105 connector pins on BoraXEVB.
  
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==Technical documentation==
 
===Schematics===
 
===Schematics===
 
* Orcad: [[mirror:bora/hw/BoraLiteADP/boralite-adapter_S-BLADP0000I0R-1.0.1-dsn.zip|boralite-adapter_S-BLADP0000I0R-1.0.1-dsn.zip]]
 
* Orcad: [[mirror:bora/hw/BoraLiteADP/boralite-adapter_S-BLADP0000I0R-1.0.1-dsn.zip|boralite-adapter_S-BLADP0000I0R-1.0.1-dsn.zip]]

Revision as of 11:18, 20 February 2020

Info Box
BORALite-TOP.png Applies to BORA Lite

Introduction[edit | edit source]

BORA Lite requires a dedicated adapter to be plugged to the BoraXEVB carrier board. This adapter:

  • provides the SODIMM socket for the BORA Lite SOM
  • provides the following additional features:
    • microSD slot (for SD boot)
    • JTAG connector
    • CAN traslator for testing the CAN bus on BoraXEVB
  • routes the signals from the BORA Lite pins to the BoraXEVB mating connectors

The following images show the top and bottom views of the BoraLite Adapter:

Top view
Bottom view

Connectors' pinout[edit | edit source]

J1 - SODIMM connector[edit | edit source]

J1 is a TE Connectivity 204-pin SODIMM socket. The pinout matches the Axel Lite pinout.

J4, J5, J6 - BoraXEVB mating connectors[edit | edit source]

J4, J5 and J6 are Hirose FX8C-140S-SV connectors that match the BoraXEVB SOM connectors' pinout.

J2 - JTAG[edit | edit source]

J2 is a SAMTEC FSI-110-03-G-S connector. The following table reports the connector's pinout:

Pin# Pin name Function Notes
1 DGND - -
2 JTAG_TCK - -
3 JTAG_TMS - -
4 JTAG_TDO - -
5 JTAG_TDI - -
6 FPGA_INIT_B - -
7 FPGA_PROGRAM_B - -
8 FPGA_DONE - -
9 D.N.C. - -
10 3V3 - -

Routing options[edit | edit source]

This table helps to map Bora Lite's signals when it is mated with the BoraXEVB carrier board. That table assumes that the adapter is populated according to the default mounting option, which is illustrated in the schematics available here.

At the adapter level, other mounting options are available, however. They are detailed in the following table.

TBD

CAN bus[edit | edit source]

Pins IO_L6P_T0_34 and IO_L19P_T3_34 can be used as CAN_TX and CAN_RX for the CAN0 interface. The BoraLite adapter provide the SN65HVD232 CAN bus transceiver required for proper CAN bus bus interface.

The CAN_L and CAN_H translated signals are routed to the J5.103 and J5.105 connector pins on BoraXEVB.

Technical documentation[edit | edit source]

Schematics[edit | edit source]

BOM[edit | edit source]

Layout[edit | edit source]