The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot configuration of iMX6 processor is determined by several pins (namely BOOT_MODE[1:0], BOOT_CFG4[7:0], BOOT_CFG3[7:0], BOOT_CFG2[7:0] and BOOT_CFG1[7:0]). These signals are sampled by iMX6's bootrom during the bootstrap stage to determine which boot sequence has to be performed. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
These signals are available on Axel Ultra's connectors, thus carrier board circuitry can drive them during bootstrap stage to change default boot configuration. As an example, refer to AxelEVB schematics for such a circuitry. Default configuration is set by internal pull up/down resistors in order to select SPI NOR flash as primary boot device:
| BOOT_CFG1
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
| BOOT_CFG2
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
|
1
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
| BOOT_CFG3
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
|
1
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
| BOOT_CFG1
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
For more details about bootstrap configuration please refer chapter System Boot of iMX6 Reference Manual.
Important note for DualLite/Solo based products (manufacture mode management)[edit | edit source]
When Dual Lite or Solo processor are used, manufacture mode is available as boot option. If internal boot is selected (BOOT_MODE[1:0]=10b), enabling of manufacture mode is controlled by EIM_A16 signal, corresponding to BOOT_CFG3[0] bit.
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