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[a] At the time of this writing, [[AN-BELK-001:_Asymmetric_Multiprocessing_(AMP)_on_Bora_–_Linux_FreeRTOS|this document]] refers to Bora BORA only. However the same AMP implementation is available for BORA Xpress as well.
[b] More complex configurations such as [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this one]] can be used as well.
*thanks to the communication channel between the two ARM cores, core #0 can be signalled by core #1 in case an alert condition is detected at the transceivers level. Thus appropriate actions can be taken at application level.
This solution has been tested on BoraXBORA Xpress/BoraXEVB BORA Xpress EVB platform implementing PCIe connectivity. PCIe Root Complex and AXI-to-DRP bridge have been integrated in PL. JTAG-to-AXI bridge has been included as well in order to keep the possibility to access monitoring data via JTAG during development/debugging stage. This allows to retrieve data from host running Vivado and generate 2D statistical eye diagrams very easily (for more details please refer to <ref name="XAPP743"></ref>). The following figures show a couple of such diagrams.
