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Created page with "__FORCETOC__ <section begin=Body/> == On board JTAG connector== The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface..."
__FORCETOC__
<section begin=Body/>
== On board JTAG connector==
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. This JTAG port grants access to the device chain composed of both the CPU core and the FPGA part.
JTAG signals are connected to the pinout connector (J2) on BORA.
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|J2.86 || JTAG_TCK || - || -
|-
|J2.84 || JTAG_TMS || - || -
|-
|J2.80 || JTAG_TDO || - || -
|-
|J2.82 || JTAG_TDI || - || -
|-
|J2.90 || FPGA_INIT_B || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
|J2.92 || FPGA_PROGRAM_B || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORA module)
|-
|J2.94 || FPGA_DONE || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
|}
<section begin=Body/>
<section begin=Body/>
== On board JTAG connector==
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. This JTAG port grants access to the device chain composed of both the CPU core and the FPGA part.
JTAG signals are connected to the pinout connector (J2) on BORA.
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|J2.86 || JTAG_TCK || - || -
|-
|J2.84 || JTAG_TMS || - || -
|-
|J2.80 || JTAG_TDO || - || -
|-
|J2.82 || JTAG_TDI || - || -
|-
|J2.90 || FPGA_INIT_B || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
|J2.92 || FPGA_PROGRAM_B || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORA module)
|-
|J2.94 || FPGA_DONE || - || For further details, please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
|}
<section begin=Body/>