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The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM.  === Boot options === The boot ROMsupports configuration from four different slave interfaces:* determines whether the boot is secure or nonQuad-secureSPI* performs some initialization of the system and clean-upsNAND* reads the mode pins to determine the primary boot deviceNOR flash (not available on BORA)* once it is satisfied, it executes the boot codeSD card

Default configuration for BORA module is:* Mode[0..3] =1000: Quad-SPI mode* Mode[4] = Boot options 0: PLL not bypassed* VCFG[0] =0: 2.5V, 3.3V operations for bank 0* VCFG[1] =1: 1.8 operations for bank 1

Two options are available related to system boot. They are identified by the Boot field of the ordering code as followsAssuming that:* 0: default configuration is not changed,* there's a valid boot code programmed in SPI NOR / SD option (SOM codeflash memory the actual boot sequence performed by ARM core will be: DXLxxxx0xxR)* 1: NAND / SD option (SOM # Bootrom is executed from internal ROM code: DXLxxxx1xxR)memoryFor both options the selection of primary boot device # FSBL is determined copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL bootrom# FSBL is executed from on-chip SRAM# U-Boot bootloader (2nd stage) is latched when processor reset copied by FSBL from NOR flash memory connected to Quad-SPI port to SDRAM# U-boot (2nd stage) is released.executed from SDRAM

In any case, If no boot process is managed by on-chip boot ROM code that is described available in detail in processor's Reference ManualSPI NOR flash, the bootrom tries JTAG peripheral booting.

=== SPI NOR / SD option Boot sequence customization ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = 0** primary boot device is SD1* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically* BOOT_MODE_SEL = 1 or floating** primary boot device is SPI NOR flash connected to eCSPI1** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically

=== NAND / SD option ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as followsBOOT_MODE[4:* BOOT_MODE_SEL = 0** primary boot device is SD1** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot device is NAND flash** in case no valid image is found in NAND flash] are routed to the J1 connector, enabling for the customization of the boot ROM shall enable USB serial download mode automaticallysequence through a simple resistor network that can be implemented on carrier board hosting BORA module.

{|class="wikitable" style==Important note for DualLite"text-align: center;"|-!Mode signal !J1 pin !Pin name|-| BOOT_MODE[4] || J1.129 || SPI0_SCLK/MODE4/Solo based products (''manufacture mode'' management)===NAND_IO1|-When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''| BOOT_MODE[3] || J1. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U125 || SPI0_DQ0/MODE3/NAND_ALE|-Boot boot loader)| BOOT_MODE[2] || J1. Please note that, in case GPIO_1 signal is used to implement 121 || SPI0_DQ2/MODE2/NAND_IO2|-| BOOT_MODE[[Reset_scheme_(AxelLite)#Handling_CPU1] || J1.123 || SPI0_DQ1/MODE1/NAND_WE|-initiated_software_reset|software reset circuitBOOT_MODE[0]], it is high during bootstrap stage by design|| J1.119 || SPI0_DQ3/MODE0/NAND_IO0|}