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The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot process is multi-stage and minimally includes the Boot ROM and the first-stage boot loader (FSBL). The Zynq-7000 AP SoC includes a factory-programmed Boot ROM that is not useraccessible. The boot ROM:

* performs some initialization of the system and clean-upscleanups

* once it is satisfied, it executes the boot codeFSBL

''TBDThe boot ROM supports configuration from four different slave interfaces: le sezioni di seguito sono valide * Quad- come esempio per AXEL SPI* NAND* NOR flash (not available on [[BORA SOM | BORA]], [[BORA Xpress SOM | BORA Xpress]],[[BORA Lite - da rivedere per gli altri prodotti ''SOM | BORA Lite]])* SD card

{|class="wikitable" style= "text-align: center;"|-!Function!Boot signals!Available options ==|-| JTAG mode || BOOT_MODE[3]<br>MIO[2]|| 0: Cascaded JTAG<br>1: Independent JTAG|-| Boot mode || BOOT_MODE[0-2-1]<br>MIO[5:3] || 000: JTAG<br>010: NAND<br>100: Quad-SPI<br>110: SD card|-| PLLs enable || BOOT_MODE[4]<br>MIO[6] || 0: PLL used<br>1: PLL bypassed|-| MIO Bank 0 Voltage || VMODE[0]<br>MIO[7] || 0: 2.5 V, 3.3 V<br>1: 1.8 V|-|MIO Bank 0 Voltage || VMODE[1]<br>MIO[8] || 0: 2.5 V, 3.3 V<br>1: 1.8 V|-|}

Two options are available related In order to system fully understand how boot. They are identified by the works on BORA platform, please refer to chapter 6 ("Boot field of the ordering code as follows:* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxRand configuration")* 1: NAND / SD option (SOM code: DXLxxxx1xxR)For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is releasedZynq7000 Technical Reference Manual.

In any case, === Default boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.configuration ===

=== SPI NOR / SD option ===Selection of primary boot device Default configuration for BORA module is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL Mode[0..3] = 01000: Quad-SPI mode** primary boot device is SD1Mode[4] = 0: PLL not bypassed* boot ROM will try to boot a valid image from the SD card firstVCFG[0] = 0: 2.5V, and then from the SPI NOR3. In case no valid image is found, boot ROM shall enable USB serial download mode automatically3V operations for bank 0* BOOT_MODE_SEL VCFG[1] = 1 or floating** primary boot device is SPI NOR flash connected to eCSPI1** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically: 1.8 operations for bank 1

=== NAND / SD option ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as followsAssuming that:* BOOT_MODE_SEL = 0** primary boot device default configuration is SD1not changed,** in case no there's a valid image is found boot code programmed in SD card, SPI flash memory the actual boot sequence performed by ARM core will be:# Bootrom is executed from internal ROM shall enable USB serial download mode automatically code memory* BOOT_MODE_SEL = 1 or floating# FSBL is copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom** primary boot device # FSBL is NAND flashexecuted from on-chip SRAM** in case no valid image # U-Boot bootloader (2nd stage) is found in NAND copied by FSBL from NOR flash, memory connected to Quad-SPI port to SDRAM# U-boot ROM shall enable USB serial download mode automatically(2nd stage) is executed from SDRAM

If no boot code is available in SPI NOR flash, the bootrom tries JTAG peripheral booting. ===Important note for DualLite/Solo based products (''manufacture mode'' management)Boot sequence customization ===When Dual Lite or Solo processor BOOT_MODE[4:0] are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order routed to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of J1 connector, enabling for the first instruction customization of user code (typically this is the reset vector of U-Boot boot loader)sequence through a simple resistor network that can be implemented on carrier board hosting BORA module. Please note that, in case GPIO_1  {|class="wikitable" style="text-align: center;"|-!Mode signal is used to implement !J1 pin !Pin name|-| BOOT_MODE[4] || J1.129 || SPI0_SCLK/MODE4/NAND_IO1|-| BOOT_MODE[3] || J1.125 || SPI0_DQ0/MODE3/NAND_ALE|-| BOOT_MODE[Reset_scheme_(AxelLite)#Handling_CPU2] || J1.121 || SPI0_DQ2/MODE2/NAND_IO2|-initiated_software_reset|software reset circuitBOOT_MODE[1]|| J1.123 || SPI0_DQ1/MODE1/NAND_WE|-| BOOT_MODE[0], it is high during bootstrap stage by design|| J1.119 || SPI0_DQ3/MODE0/NAND_IO0|}