Bureaucrats, dave_user, Administrators
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<section begin=History/>{| style="border-collapse:collapse; "!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History|- !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2021/10/29|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout|-|}<section end=History/>__FORCETOC__<section begin=Body/>
An on-board Microchip 24AA32AT device provides an added storage device for factory settings:
* the first 32 bytes of the device '''are RESERVED''': this region stores the bytes for the [[ConfigID_and_UniqueID#I2C_Eeprom|ConfigID]] on BORA SOMs configured for booting from NAND device (without NOR SPI on board)
* three address pins for configuring the I2C adddress A0, A1, A2 internally configured as A[0..2]='000'
* the EEPROM_WP is connected to J2.78 pin and '''should not be externally connected'''
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