BORA Lite SOM/BORA Lite Hardware

BORA Lite SOM HW Manual

BORA Lite TOP view BORA Lite Block diagram Processor and memory subsystem Hardware versioning and tracking BORA Lite SOM RFQ Request For Quotation

Customers are strongly recommended to register their kits. Registration grants access to reserved material such as source code and additional documentation. To register the kit, please send an email to helpdesk@dave.eu, providing the kit P/N and S/N. [link_TBD BORA Lite Hw Manual] PDF Manuals are available only on the latest version. Checkout the pages' history on wiki for previous releases or contact helpdesk@dave.eu

Connectors and Pinout		Power and Reset		Peripherals		Electrical, Thermal and Mechanical Features
Connectors and Pinout Table Pinout Table ODD pins declaration Pinout Table EVEN pins declaration		Power Supply Unit (PSU) and recommended power-up sequence Reset scheme and control signals System boot JTAG		Programmable logic (FPGA) CAN Ethernet SDIO SPI I2C UART USB GPIOs EEPROM Real Time Clock Watchdog		Operational characteristics Thermal management and heat dissipation Mechanical specifications