Getting startedEdit
Kit Identification CodesEdit
The development kits (DESK, XELK, XUELK, BELK, etc.) are identified by a couple of codes:
- P/N Part Number identification code
- S/N Serial Number identification code
These codes are printed on a label sticked to the box containing the kit.
For example, the following picture shows such a label of an AXEL Ultra XELK (XELK-H-S) with Serial Number 0CFA
These codes are required to complete the registration process of the kit.
UnboxingEdit
Once you've received the kit, please open the box and check the kit contents with the packing list included in the box, using the table on this chapter as a reference.
The hardware components (SOM, carrier boards and display) are pre-assembled, as shown in the picture below:
VideoEdit
Kit ContentsEdit
Component | Description | Notes |
---|---|---|
BoraLite SOM (p/n DBTD4111I0R)
|
||
BoraXEVB BoraLite Adapter board | ||
BoraXEVB carrier board | ||
AC/DC Single Output Wall Mount adapter Output: +12V – 2.0 A |
||
microSDHC card with SD adapter and USB adapter |
Order codesEdit
Order code | Description |
---|---|
BTELK-L-S | This code refers to the default configuration detailed above |
microSD LayoutEdit
The microSD provided with the kit is used to store:
- a bootable partition (mmcblk0p1, vfat) containing:
- binary images (u-boot and kernel images)
- root file system partition (mmcblk0p2, ext4)
Kit contentsEdit
Component | Description | Notes |
---|---|---|
BoraLite SOM (p/n DBTD4111I0R)
|
||
BoraXEVB BoraLite Adapter board | ||
BoraXEVB carrier board | ||
AC/DC Single Output Wall Mount adapter Output: +12V – 2.0 A |
||
microSDHC card with SD adapter and USB adapter |
Order codesEdit
Order code | Description |
---|---|
BTELK-L-S | This code refers to the default configuration detailed above |
Target setup and first bootEdit
This section describes how to quickly start Bora/BoraEVB and BoraX/BoraXEVB systems included in the BELK/BXELK:
- on target side, connect a null-modem cable on J17 DB9 connector, denoted also as UART1
- on host side, connect the other end of the null-modem cable to a COM port and start your favorite terminal software that will be used to interact with the target's serial console; communication parameters are 115200-8-N-1
- optionally connect the BoraEVB/BoraXEVB board to an Ethernet LAN by plugging cable into connector J8, also denoted as ETH0 on BoraEVB and BORAX ETHERNET on BoraXEVB
- connect 12V power supply to JP2 or J7 connector, also denoted as PSU 12V
- insert the microSD card in the slot J21, also denoted as MICROSD.
Once power has been applied to the target, FSBL or U-boot SPL and U-Boot bootloaders will be fetched from the SPI NOR flash that equips Bora/BoraX/BORA Lite SOM and executed. Boot messages will be printed out to the serial console. Redundant U-Boot environment is stored in the NOR flash as well, as depicted in the following image.
By default, U-Boot is configured to retrieve Linux kernel image stored in the microSD card [1]. In turn, Linux kernel shall mount root file system from the mmcblk0p2
partition of the microSD card itself [2], [3]. At the end of boot process, Linux shell shall be available on the serial console. Default boot process does not download any bitstream to the Programmable Logic.
The following dump shows the typical messages printed out to the console during bootstrap process. This log refers to Belk-4.0.0 running on BORA SOM. For BORAX SOM similar messages are printed out to the console.
U-Boot SPL 2017.01-belk-4.0.0 (Jul 11 2017 - 15:58:04) qspi boot Trying to boot from SPI U-Boot 2017.01-belk-4.0.0 (Jul 11 2017 - 15:58:04 +0200), Build: jenkins-BELK_u-boot-10 Model: Bora Board: Xilinx Zynq I2C: ready DRAM: ECC disabled 1 GiB Relocating to 3ff2e000, new gd at 3eaedee8, sp at 3eaedec0 NAND: 1024 MiB MMC: sdhci@e0100000: 0 (SD) SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 64 MiB *** Warning - bad CRC, using default environment In: serial@e0001000 Out: serial@e0001000 Err: serial@e0001000 Model: Bora Board: Xilinx Zynq SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 64 MiB SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 64 MiB SOM ConfigID#: 00000001 SOM UniqueID#: 01234567:89abcdef ds2431_readmem(): error in chip reset ds2431_readmem(): error in reading buffer ds2431_readmem(): error in chip reset ds2431_readmem(): error in reading buffer CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default CB ConfigID#: ffffffff CB UniqueID#: 00000000:00000000 Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id eth0: ethernet@e000b000 Hit ENTER within 3 seconds to stop autoboot starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found USB device 0: unknown device ** Bad device usb 0 ** switch to partitions #0, OK mmc0 is current device reading boot.scr 472 bytes read in 12 ms (38.1 KiB/s) Running bootscript from mmc ... ## Executing script at 02080000 bootscript generated with command "mkimage -A ARM -T script -C none -n BELK -d bootscript.txt boot.scr" reading uImage 3770880 bytes read in 642 ms (5.6 MiB/s) reading bora.dtb 10647 bytes read in 19 ms (546.9 KiB/s) Booting Bora/BoraX via mmc ## Error: "configid_fixup" not defined ## Booting kernel from Legacy Image at 02080000 ... Image Name: Linux-4.9.0-belk-4.0.0-xilinx Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3770816 Bytes = 3.6 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 02000000 Booting using the fdt blob at 0x2000000 Loading Kernel Image ... OK Loading Device Tree to 1effa000, end 1efff996 ... OK Switching to NAND storage before starting Linux Starting kernel ... Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.9.0-belk-4.0.0-xilinx (jenkins@linuxserver2) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Sun Jul 9 23:10:22 CEST 2017 [ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt:Machine model: Bora [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] cma: Reserved 16 MiB at 0x3f000000 [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] On node 0 totalpages: 262144 [ 0.000000] free_area_init_node: node 0, pgdat c0a2d840, node_mem_map ef7f7000 [ 0.000000] Normal zone: 1536 pages used for memmap [ 0.000000] Normal zone: 0 pages reserved [ 0.000000] Normal zone: 196608 pages, LIFO batch:31 [ 0.000000] HighMem zone: 65536 pages, LIFO batch:15 [ 0.000000] percpu: Embedded 14 pages/cpu @ef7d1000 s26124 r8192 d23028 u57344 [ 0.000000] pcpu-alloc: s26124 r8192 d23028 u57344 alloc=14*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260608 [ 0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait rw console=ttyPS0,115200n8 debug earlyprintk [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Memory: 1013220K/1048576K available (6144K kernel code, 232K rwdata, 1512K rodata, 1024K init, 323K bss, 18972K reserved, 16384K cma-reserved, 245760K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB) [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc0700000 (7136 kB) [ 0.000000] .init : 0xc0900000 - 0xc0a00000 (1024 kB) [ 0.000000] .data : 0xc0a00000 - 0xc0a3a1a0 ( 233 kB) [ 0.000000] .bss : 0xc0a3a1a0 - 0xc0a8afb4 ( 324 kB) [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 32. [ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2 [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] efuse mapped to f0802000 [ 0.000000] slcr mapped to f0804000 [ 0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x02460000 [ 0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x02460000 [ 0.000000] L2C-310 erratum 769419 enabled [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9 [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9 [ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled [ 0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB [ 0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001 [ 0.000000] zynq_clock_init: clkc starts at f0804100 [ 0.000000] Zynq clock init [ 0.000000] ps_clk frequency not specified, using 33 MHz. [ 0.000012] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns [ 0.007870] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns [ 0.018886] Switching to timer-based delay loop, resolution 3ns [ 0.024887] clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns [ 0.033937] timer #0 at f080c000, irq=17 [ 0.038252] Console: colour dummy device 80x30 [ 0.042581] Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333) [ 0.053061] pid_max: default: 32768 minimum: 301 [ 0.057843] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.064345] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [ 0.071973] CPU: Testing write buffer coherency: ok [ 0.076890] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.082484] Setting up static identity map for 0x100000 - 0x100058 [ 0.258340] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.258442] Brought up 2 CPUs [ 0.266979] SMP: Total of 2 processors activated (1333.33 BogoMIPS). [ 0.273360] CPU: All CPU(s) started in SVC mode. [ 0.278941] devtmpfs: initialized [ 0.285288] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [ 0.293052] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.303669] pinctrl core: initialized pinctrl subsystem [ 0.310015] NET: Registered protocol family 16 [ 0.316110] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.358364] cpuidle: using governor ladder [ 0.398352] cpuidle: using governor menu [ 0.414905] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.422775] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.428739] zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000 [ 0.435584] zynq-pinctrl 700.pinctrl: zynq pinctrl initialized [ 0.455610] vgaarb: loaded [ 0.458851] SCSI subsystem initialized [ 0.462817] usbcore: registered new interface driver usbfs [ 0.468276] usbcore: registered new interface driver hub [ 0.473587] usbcore: registered new device driver usb [ 0.479680] pps_core: LinuxPPS API ver. 1 registered [ 0.484514] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.493700] PTP clock support registered [ 0.499357] clocksource: Switched to clocksource arm_global_timer [ 0.520290] NET: Registered protocol family 2 [ 0.525350] TCP established hash table entries: 8192 (order: 3, 32768 bytes) [ 0.532409] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) [ 0.538840] TCP: Hash tables configured (established 8192 bind 8192) [ 0.545202] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 0.551082] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 0.557542] NET: Registered protocol family 1 [ 0.562207] RPC: Registered named UNIX socket transport module. [ 0.567985] RPC: Registered udp transport module. [ 0.572752] RPC: Registered tcp transport module. [ 0.577445] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.583922] PCI: CLS 0 bytes, default 64 [ 0.588414] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available [ 0.598056] futex hash table entries: 512 (order: 3, 32768 bytes) [ 0.604966] workingset: timestamp_bits=30 max_order=18 bucket_order=0 [ 0.612013] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. [ 0.619910] bounce: pool size: 64 pages [ 0.623630] io scheduler noop registered [ 0.627583] io scheduler deadline registered [ 0.631928] io scheduler cfq registered (default) [ 0.639167] dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330 [ 0.645763] dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 [ 0.654861] e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 145, base_baud = 3125000) is a xuartps [ 0.664307] e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 146, base_baud = 3125000) is a xuartps à[ 0.673432] console [ttyPS0] enabled [ 0.673432] console [ttyPS0] enabled [ 0.680527] bootconsole [earlycon0] disabled [ 0.680527] bootconsole [earlycon0] disabled [ 0.689751] xdevcfg f8007000.devcfg: ioremap 0xf8007000 to f086f000 [ 0.696648] [drm] Initialized [ 0.712609] brd: module loaded [ 0.723100] loop: module loaded [ 0.728406] libphy: Fixed MDIO Bus: probed [ 0.735460] CAN device driver interface [ 0.741807] libphy: MACB_mii_bus: probed [ 0.840108] macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 148 (00:50:c2:1e:af:e0) [ 0.849977] Micrel KSZ9031 Gigabit PHY e000b000.etherne:07: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=e000b000.etherne:07, irq=-1) [ 0.864140] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 0.869913] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 0.876782] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 0.883279] ehci-pci: EHCI PCI platform driver [ 0.887820] usbcore: registered new interface driver usb-storage [ 0.894012] e0002000.usb supply vbus not found, using dummy regulator [ 0.900703] ULPI transceiver vendor/product ID 0x0424/0x0006 [ 0.906275] Found SMSC USB331x ULPI transceiver. [ 0.910910] ULPI integrity check: passed. [ 0.916630] mousedev: PS/2 mouse device common for all mice [ 0.922521] i2c /dev entries driver [ 0.926190] cdns-i2c e0004000.i2c: 100 kHz mmio e0004000 irq 142 [ 0.933517] rtc-ds3232 0-0068: oscillator discontinuity flagged, time unreliable [ 0.943182] rtc-ds3232 0-0068: rtc core: registered ds3232 as rtc0 [ 0.950800] ina2xx 0-0041: power monitor ina226 (Rshunt = 10000 uOhm) [ 0.959126] Xilinx Zynq CpuIdle Driver started [ 0.964011] sdhci: Secure Digital Host Controller Interface driver [ 0.970180] sdhci: Copyright(c) Pierre Ossman [ 0.974447] sdhci-pltfm: SDHCI platform and OF driver helper [ 1.039420] mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using DMA [ 1.047063] usbcore: registered new interface driver usbhid [ 1.053610] usbhid: USB HID core driver [ 1.060557] nand: device found, Manufacturer ID: 0x01, Chip ID: 0xd3 [ 1.066828] nand: AMD/Spansion S34ML08G1 [ 1.070797] nand: 1024 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 [ 1.079104] Bad block table found at page 524224, version 0x01 [ 1.086183] Bad block table found at page 524160, version 0x01 [ 1.092800] 8 ofpart partitions found on MTD device pl35x-nand [ 1.098568] Creating 8 MTD partitions on "pl35x-nand": [ 1.103708] 0x000000000000-0x000000040000 : "nand-SPL" [ 1.120695] 0x000000040000-0x000000100000 : "nand-uboot" [ 1.137009] 0x000000100000-0x000000140000 : "nand-uboot-env1" [ 1.153846] 0x000000140000-0x000000180000 : "nand-uboot-env2" [ 1.160646] mmc0: new SDHC card at address 0001 [ 1.165619] mmcblk0: mmc0:0001 SD16G 14.6 GiB [ 1.170685] 0x000000180000-0x000000780000 : "nand-bitstream" [ 1.177693] 0x000000780000-0x000000800000 : "nand-device-tree" [ 1.183599] mmcblk0: p1 p2 [ 1.194709] 0x000000800000-0x000001000000 : "nand-linux" [ 1.211164] 0x000001000000-0x000020000000 : "nand-rootfs" [ 1.232466] NET: Registered protocol family 17 [ 1.236842] can: controller area network core (rev 20120528 abi 9) [ 1.243084] NET: Registered protocol family 29 [ 1.247450] can: raw protocol (rev 20120528) [ 1.251720] can: broadcast manager protocol (rev 20161123 t) [ 1.257345] can: netlink gateway (rev 20130117) max_hops=1 [ 1.263160] Registering SWP/SWPB emulation handler [ 1.274219] rtc-ds3232 0-0068: hctosys: unable to read the hardware clock [ 1.283162] EXT4-fs (mmcblk0p2): mounting ext3 file system using the ext4 subsystem [ 1.592447] random: fast init done [ 1.748727] EXT4-fs (mmcblk0p2): recovery complete [ 1.756780] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null) [ 1.764840] VFS: Mounted root (ext3 filesystem) on device 179:2. [ 1.775504] devtmpfs: mounted [ 1.781627] Freeing unused kernel memory: 1024K (c0900000 - c0a00000) INIT: version 2.88 booting Starting udev [ 2.706500] udevd[702]: starting version 3.2 [ 2.771034] udevd[703]: starting eudev-3.2 [ 2.915949] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null) Mon Jul 3 00:01:52 UTC 2017 INIT: Entering runlevel: 5 Configuring network interfaces... udhcpc (v1.24.1) started Sending discover... Sending discover... Sending discover... No lease, forking to background done. Starting system message bus: dbus. Starting Dropbear SSH server: dropbear. Starting rpcbind daemon...done. starting statd: done exportfs: can't open /etc/exports for reading NFS daemon support not enabled in kernel Starting syslogd/klogd: done Starting internet superserver: xinetd. * Starting Avahi mDNS/DNS-SD Daemon: avahi-daemon ...done. Starting tcf-agent: OK Poky (Yocto Project Reference Distro) 2.2.1 bora /dev/ttyPS0 bora login:
[1] bootscript
is used to do this task.
[2] This root file system has been generated by Yocto build system.
[3] The microSD card is bootable itself, as explained here.
microSD layoutEdit
The microSD card provided with BELK/BXELK is partitioned as shown in the following image:
Most of storage space is occupied by two partitions:
- a
FAT32
partition (mmcblk0p1
) containing:- For BELK <= 3.0.2 and BXELK <= 1.0.1 :
boot.bin
boot image (containing FSBL, FPGA Bitstream an U-boot binaries)- U-Boot
boot.scr
bootscript - Linux kernel and DTB binary images
- For BELK 4.0.0 or newer and BXELK 2.0.0 or newer:
boot.bin
u-boot SPL imagefpga.bit
optional FPGA bitstreamu-boot.img
u-boot image- U-Boot
boot.scr
bootscript - Linux kernel and DTB binary images
- MVM image in OVA format
- For BELK <= 3.0.2 and BXELK <= 1.0.1 :
- an
ext3
partition (mmcblk0p2
) containing the root file system for the target.
bootscript and root file system are used to boot the target as described in this section.
It is worth remembering that the microSD card is bootable and U-Boot environment is retrieved from (and stored to with saveenv
) into the FAT partition as bora.env
Boot mode selection - S5Edit
S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:
S5.1 | S5.2 | S5.3 | S5.4 | S5.5 | S5.6 | S5.7 | S5.8 | |
---|---|---|---|---|---|---|---|---|
SPI-NOR | OFF | ON | OFF | ON | ON | ON | ON | OFF |
SD-card | OFF | ON | OFF | ON | ON | OFF | ON | OFF |
NAND (*) | OFF | ON | OFF | ON | ON | OFF | ON | ON |
JTAG | OFF | ON | OFF | ON | ON | ON | ON | ON |
(*) Boot mode from NAND in supported ONLY on BORA Lite SOM module
Reset button - S6Edit
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
General InformationEdit
Product HighlightsEdit
The BORA Lite Evaluation Board platform presented here provides a compact solution for evaluating the BORA Lite SOM performances and connection capability.
The following table summarizes the main hardware and software features available with BoraXEVB:
HardwareEdit
Subsystem | Characteristics |
---|---|
CPU | Zynq 7000 Dual Core Cortex-A7 |
SD | microSD boot device |
USB | OTG |
Serial Ports | RS232 CAN interface |
Ethernet | Dual EMAC 10/100/1000Mbps |
Display | LVDS interface |
Touchscreen | Resistive |
Espansion | FMC connector |
PSU | 12 to 24V DC |
SoftwareEdit
Subsystem | Options |
---|---|
Operating System | Linux |
Distribution | Yocto, Petalinux |
Applications | SoftPLC |
Block DiagramEdit
The following picture shows BORA Xpress EVB block diagram:
Configurable routing optionsEdit
FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.
For a detailed description of FMC connector routing, please refer to this section.
BoraXEdit
Bora LiteEdit
Interfaces and ConnectorsEdit
Power SupplyEdit
Power supply - JP2Edit
Power is provided through the JP2 connector.
JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | VIN | Power supply | Nominal: +12V |
2 , 3 | DGND | Ground | - |
Voltage selectionsEdit
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
- each bank must be powered even if none of its I/Os is used
- voltage selection must be done before powering up the board.
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
SoM | Zynq p/n | Bank #34 | Bank #13 | Bank #35 | |||
---|---|---|---|---|---|---|---|
Type [1] | I/O voltage setting | Type [1] | I/O voltage setting | Type [1] | I/O voltage setting | ||
BoraX | 7015
(CLG485 package) |
HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined |
7030
(SBG485 package) |
HP
(1.2 - 1.8V) |
User defined | HR
(1.2 - 3.3V) |
User defined | HP
(1.2 - 1.8V) |
User defined | |
Bora Lite | 7007S/7010
(CLG400 package) |
HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined |
7014S/7020
(CLG400 package) |
HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined | HR
(1.2 - 3.3V) |
User defined |
[1]
- HR = High Range
- HP = High Performance
BoraXEVB voltage selection jumpersEdit
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, some of them are not allowed and may cause permanent hardware damages to the Zynq part.
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations are not the same for all of the BoraX models. Please refer to the following sections for more details.
Even if PL's banks are independent, default configuration of BoraXEVB is such that
- bank 34 and bank 35 have the same supply voltage
- this voltage is selected via JP28.
This configuration is in accordance with default routing of signals used for FMC connector.
Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)Edit
Nominal voltage [V] | JP25.1-2 | JP25.3-4 | JP25.5-6 | JP25.7-8 | JP25.9-10 | JP25.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | closed | closed | closed | open |
1.5 | open | closed | open | closed | open | open |
1.8 | open | closed | closed | open | closed | open |
2.5 | closed | open | closed | open | open | open |
3.3 | closed | closed | closed | open | open | open |
Nominal voltage [V] | JP27.1-2 | JP27.3-4 | JP27.5-6 | JP27.7-8 | JP27.9-10 | JP27.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | closed | closed | closed | open |
1.5 | open | closed | open | closed | open | open |
1.8 | open | closed | closed | open | closed | open |
Nominal voltage [V] | JP28.1-2 | JP28.3-4 | JP28.5-6 | JP28.7-8 | JP28.9-10 | JP28.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | open | open | closed | open |
1.5 | open | open | open | closed | open | open |
1.8 | open | open | closed | open | open | open |
Examples of valid combinations for Zynq 7015-based SOMsEdit
Nominal voltage [V] | JP25.1-2 | JP25.3-4 | JP25.5-6 | JP25.7-8 | JP25.9-10 | JP25.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | closed | closed | closed | open |
1.5 | open | closed | open | closed | open | open |
1.8 | open | closed | closed | open | closed | open |
2.5 | closed | open | closed | open | open | open |
3.3 | closed | closed | closed | open | open | open |
Nominal voltage [V] | JP27.1-2 | JP27.3-4 | JP27.5-6 | JP27.7-8 | JP27.9-10 | JP27.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | closed | closed | closed | open |
1.5 | open | closed | open | closed | open | open |
1.8 | open | closed | closed | open | closed | open |
2.5 | closed | open | closed | open | open | open |
3.3 | closed | closed | closed | open | open | open |
Nominal voltage [V] | JP28.1-2 | JP28.3-4 | JP28.5-6 | JP28.7-8 | JP28.9-10 | JP28.11-12 |
---|---|---|---|---|---|---|
1.2 | open | open | open | open | closed | open |
1.5 | open | open | open | closed | open | open |
1.8 | open | open | closed | open | open | open |
2.5 | open | closed | open | open | open | open |
3.3 | closed | open | open | open | open | open |
Advanced information about voltage selection connectorsEdit
Bank 13 VDDIO selection connector (JP25)Edit
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
2 | LDO_B13_1V6 | adds +1.6V to VDDIO_BANK13 | - |
4 | LDO_B13_800mV | adds +800mV to VDDIO_BANK13 | - |
6 | LDO_B13_400mV | adds +400mV to VDDIO_BANK13 | - |
8 | LDO_B13_200mV | adds +200mV to VDDIO_BANK13 | - |
10 | LDO_B13_100mV | adds +100mV to VDDIO_BANK13 | - |
12 | LDO_B13_50mV | adds +50mV to VDDIO_BANK13 | - |
1, 3, 5, 7, 9, 11 | DGND | - | - |
The jumper configurations are:
- No jumpers installed -> DC output for VDDIO_BANK13 is 500mV
- Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
- Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
- Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV
- Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV
- Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV
- Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
- Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
- Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
- Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
Bank 35 VDDIO selection connector (JP27)Edit
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
2 | LDO_B35_1V6 | adds +1.6V to VDDIO_BANK35 | - |
4 | LDO_B35_800mV | adds +800mV to VDDIO_BANK35 | - |
6 | LDO_B35_400mV | adds +400mV to VDDIO_BANK35 | - |
8 | LDO_B35_200mV | adds +200mV to VDDIO_BANK35 | - |
10 | LDO_B35_100mV | adds +100mV to VDDIO_BANK35 | - |
12 | LDO_B35_50mV | adds +50mV to VDDIO_BANK35 | - |
1, 3, 5, 7, 9, 11 | DGND | - | - |
The jumper configurations are:
- No jumpers installed -> DC output for VDDIO_BANK35 is 500mV
- Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV
- Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
- Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV
- Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV
- Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV
- Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV
The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):
- Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
- Jumper on 5-6 -> adds 400mV to VDDIO_BANK35
- Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10. |
Bank 34 and VADJ VDDIO selection connector (JP28)Edit
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
2 | VADJ_FB (22K) | selects 3.3V VADJ | - |
4 | VADJ_FB (30K9) | selects 2.5V VADJ | - |
6 | VADJ_FB (51K1) | selects 1.8V VADJ | - |
8 | VADJ_FB (68K) | selects 1.5V VADJ | - |
10 | VADJ_FB (100K) | selects 1.2V VADJ | - |
12 | RFU | Reserved | - |
1, 3, 5, 7, 9, 11 | DGND | - | - |
The jumper configurations are:
- Jumper on 1-2 -> supply VADJ with 3.3V
- Jumper on 3-4 -> supply VADJ with 2.5V
- Jumper on 5-6 -> supply VADJ with 1.8V
- Jumper on 7-8 -> supply VADJ with 1.5V
- Jumper on 9-10 -> supply VADJ with 1.2V
The default configuration is:
- Jumper on 5-6 -> supply VADJ with 1.8V
CPU connectorsEdit
SoM's signals mappingEdit
Bora LiteEdit
As known, Bora Lite requires an adapter to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here it is assumed to use an adapter with default mounting options.
SoM's signal | Routing options at carrier board level | ||||||
---|---|---|---|---|---|---|---|
Bank | Name | Option #1
(default) |
Option #2 | ||||
Name | Pin | Note | Name | Pin | Note | ||
34 | IO_0_34 | IO_0_VRN_34 | J31.2 | Header | |||
J27D.H2 | FMC conn. | ||||||
IO_25_34 | IO_25_VRP_35 | J31.4 | Header | ||||
J27B.D1 | FMC conn. | ||||||
IO_L10N_T1_34 | IO_L10N_T1_34 | J27D.H26 | FMC conn. | ||||
IO_L10P_T1_34 | IO_L10P_T1_34 | J27D.H25 | FMC conn. | ||||
IO_L11N_T1_SRCC_34 | IO_L11N_T1_SRCC_34 | J27D.G3 | FMC conn. | ||||
IO_L11P_T1_SRCC_34 | IO_L11P_T1_SRCC_34 | J27D.G2 | FMC conn. | ||||
IO_L12N_T1_MRCC_34 | IO_L12N_T1_MRCC_34 | J27D.H5 | FMC conn. | ||||
IO_L12P_T1_MRCC_34 | IO_L12P_T1_MRCC_34 | J27D.H4 | FMC conn. | ||||
IO_L13N_T2_MRCC_34 | IO_L13N_T1_MRCC_34 | J27D.G7 | FMC conn. | ||||
IO_L13P_T2_MRCC_34 | IO_L13P_T1_MRCC_34 | J27D.G6 | FMC conn. | ||||
IO_L14N_T2_SRCC_34 | IO_L14N_T2_SRCC_34 | J27B.D9 | FMC conn. | ||||
IO_L14P_T2_SRCC_34 | IO_L14P_T2_SRCC_34 | J27B.D8 | FMC conn. | ||||
IO_L15N_T2_DQS_34 | IO_L15N_T2_DQS_34 | J27B.D21 | FMC conn. | ||||
IO_L15P_T2_DQS_34 | IO_L15P_T2_DQS_34 | J27B.D20 | FMC conn. | ||||
IO_L16N_T2_34 | IO_L16N_T2_34 | J27B.C23 | FMC conn. | ||||
IO_L16P_T2_34 | IO_L16P_T2_34 | J27B.C22 | FMC conn. | ||||
IO_L17N_T2_34 | IO_L17N_T2_34 | J27D.G22 | FMC conn. | ||||
IO_L17P_T2_34 | IO_L17P_T2_34 | J27D.G21 | FMC conn. | ||||
IO_L18N_T2_34 | IO_L18N_T2_34 | J27D.H20 | FMC conn. | ||||
IO_L18P_T2_34 | IO_L18P_T2_34 | J27D.H19 | FMC conn. | ||||
IO_L19N_T3_VREF_34 | IO_L19N_T3_VREF_34 | J27D.G19 | FMC conn. | ||||
TP21 | TP SMD | ||||||
IO_L19P_T3_34 | n/a | n/a | At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24. | ||||
IO_L1N_T0_34 | IO_L1N_T0_34 | J27B.C19 | FMC conn. | ||||
IO_L1P_T0_34 | IO_L1P_T0_34 | J27B.C18 | FMC conn. | ||||
IO_L20N_T3_34 | IO_L20N_T3_34 | J27B.D18 | FMC conn. | ||||
IO_L20P_T3_34 | IO_L20P_T3_34 | J27B.D17 | FMC conn. | ||||
IO_L21N_T3_DQS_34 | IO_L21N_T3_DQS_34 | J27D.H17 | FMC conn. | ||||
IO_L21P_T3_DQS_34 | IO_L21P_T3_DQS_34 | J27D.H16 | FMC conn. | ||||
IO_L22N_T3_34 | IO_L22N_T3_34 | J27D.G16 | FMC conn. | ||||
IO_L22P_T3_34 | IO_L22P_T3_34 | J27D.G15 | FMC conn. | ||||
IO_L23N_T3_34 | IO_L23N_T3_34 | J27B.C11 | FMC conn. | ||||
IO_L23P_T3_34 | IO_L23P_T3_34 | J27B.C10 | FMC conn. | ||||
IO_L24N_T3_34 | IO_L24N_T3_34 | J27D.H23 | FMC conn. | ||||
IO_L24P_T3_34 | IO_L24P_T3_34 | J27D.H22 | FMC conn. | ||||
IO_L2N_T0_34 | IO_L2N_T0_34 | J27B.C15 | FMC conn. | ||||
IO_L2P_T0_34 | IO_L2P_T0_34 | J27B.C14 | FMC conn. | ||||
IO_L3N_T0_DQS_34 | IO_L3N_T0_DQS_34 | J27D.G13 | FMC conn. | ||||
IO_L3P_T0_DQS_PUDC_B_34
(10K pull-up on SoM) |
IO_L3P_T0_DQS_PUDC_B_34 | J27D.G12 | FMC conn. | ||||
IO_L4N_T0_34 | IO_L4N_T0_34 | J27D.G10 | FMC conn. | ||||
IO_L4P_T0_34 | IO_L4P_T0_34 | J27D.G9 | FMC conn. | ||||
IO_L5N_T0_34 | IO_L5N_T0_34 | J27D.H11 | FMC conn. | ||||
IO_L5P_T0_34 | IO_L5P_T0_34 | J27D.H10 | FMC conn. | ||||
IO_L6N_T0_VREF_34 | IO_L6N_T0_VREF_34 | J27B.D15 | FMC conn. | ||||
TP22 | TP SMD | ||||||
IO_L6P_T0_34 | n/a | n/a | At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24. | ||||
IO_L7N_T1_34 | IO_L7N_T1_34 | J27D.H8 | FMC conn. | ||||
IO_L7P_T1_34 | IO_L7P_T1_34 | J27D.H7 | FMC conn. | ||||
IO_L8N_T1_34 | IO_L8N_T1_34 | J27D.H14 | FMC conn. | ||||
IO_L8P_T1_34 | IO_L8P_T1_34 | J27D.H13 | FMC conn. | ||||
IO_L9N_T1_DQS_34 | IO_L9N_T1_DQS_34 | J27B.D12 | FMC conn. | ||||
IO_L9P_T1_DQS_34 | IO_L9P_T1_DQS_34 | J27B.D11 | FMC conn. | ||||
35 | IO_0_35 | IO_0_VRN_35 | J27C.F1 | FMC conn. | |||
J31.1 | Header | ||||||
IO_25_35 | IO_25_VRP_35 | J27E.K13 | FMC conn. | ||||
J31.3 | Header | ||||||
IO_L10N_T1_AD11N_35 | IO_L10N_T1_AD11N_35 | J27D.G34 | FMC conn. | FPGA_BANK35_AD11N | JP32.3 | Header | |
IO_L10P_T1_AD11P_35 | IO_L10P_T1_AD11P_35 | J27D.G33 | FMC conn. | FPGA_BANK35_AD11P | JP32.1 | Header | |
IO_L11N_T1_SRCC_35 | IO_L11N_T1_SRCC_35 | J27E.J3 | FMC conn. | ||||
IO_L11P_T1_SRCC_35 | IO_L11P_T1_SRCC_35 | J27E.J2 | FMC conn. | ||||
IO_L12N_T1_MRCC_35 | IO_L12N_T1_MRCC_35 | J27E.K5 | FMC conn. | ||||
IO_L12P_T1_MRCC_35 | IO_L12P_T1_MRCC_35 | J27E.K4 | FMC conn. | ||||
IO_L13N_T2_MRCC_35 | IO_L13N_T2_MRCC_35 | J27C.F5 | FMC conn. | ||||
IO_L13P_T2_MRCC_35 | IO_L13P_T2_MRCC_35 | J27C.F4 | FMC conn. | ||||
IO_L14N_T2_AD4N_SRCC_35 | IO_L14N_T2_AD4N_SRCC_35 | J27C.E3 | FMC conn. | FPGA_BANK35_AD4N | JP30.16 | Header | |
IO_L14P_T2_AD4P_SRCC_35 | IO_L14P_T2_AD4P_SRCC_35 | J27C.E2 | FMC conn. | FPGA_BANK35_AD4P | JP30.14 | Header | |
IO_L15N_T2_DQS_AD12N_35 | IO_L15N_T2_DQS_AD12N_35 | J27D.H38 | FMC conn. | FPGA_BANK35_AD12N | JP32.8 | Header | |
IO_L15P_T2_DQS_AD12P_35 | IO_L15P_T2_DQS_AD12P_35 | J27D.H37 | FMC conn. | FPGA_BANK35_AD12P | JP32.6 | Header | |
IO_L16N_T2_35 | IO_L16N_T2_35 | J27D.G37 | FMC conn. | ||||
IO_L16P_T2_35 | IO_L16P_T2_35 | J27D.G36 | FMC conn. | ||||
IO_L17N_T2_AD5N_35 | IO_L17N_T2_AD5N_35 | J27E.K8 | FMC conn. | FPGA_BANK35_AD5N | JP31.1 | Header | |
IO_L17P_T2_AD5P_35 | IO_L17P_T2_AD5P_35 | J27E.K7 | FMC conn. | FPGA_BANK35_AD5P | JP30.15 | Header | |
IO_L18N_T2_AD13N_35 | IO_L18N_T2_AD13N_35 | J27E.J7 | FMC conn. | FPGA_BANK35_AD13N | JP32.9 | Header | |
IO_L18P_T2_AD13P_35 | IO_L18P_T2_AD13P_35 | J27E.J6 | FMC conn. | FPGA_BANK35_AD13P | JP32.7 | Header | |
IO_L19N_T3_VREF_35 | IO_L19N_T3_VREF_35 | J27C.F8 | FMC conn. | ||||
TP24 | TP SMD | ||||||
IO_L19P_T3_35 | IO_L19P_T3_35 | J27C.F7 | FMC conn. | ||||
IO_L1N_T0_AD0N_35 | IO_L1N_T0_AD0N_35 | J27D.G25 | FMC conn. | FPGA_BANK35_AD0P | JP30.4 | Header | |
IO_L1P_T0_AD0P_35 | IO_L1P_T0_AD0P_35 | J27D.G24 | FMC conn. | FPGA_BANK35_AD0N | JP30.2 | Header | |
IO_L20N_T3_AD6N_35 | IO_L20N_T3_AD6N_35 | J27C.E7 | FMC conn. | FPGA_BANK35_AD6N | JP31.6 | Header | |
IO_L20P_T3_AD6P_35 | IO_L20P_T3_AD6P_35 | J27C.E6 | FMC conn. | FPGA_BANK35_AD6P | JP31.4 | Header | |
IO_L21N_T3_DQS_AD14N_35 | IO_L21N_T3_DQS_AD14N_35 | J27E.K11 | FMC conn. | FPGA_BANK35_AD14N | JP32.14 | Header | |
IO_L21P_T3_DQS_AD14P_35 | IO_L21P_T3_DQS_AD14P_35 | J27E.K10 | FMC conn. | FPGA_BANK35_AD14P | JP32.12 | Header | |
IO_L22N_T3_AD7N_35 | IO_L22N_T3_AD7N_35 | J27E.J10 | FMC conn. | FPGA_BANK35_AD7N | JP31.7 | Header | |
IO_L22P_T3_AD7P_35 | IO_L22P_T3_AD7P_35 | J27E.J9 | FMC conn. | FPGA_BANK35_AD7P | JP31.5 | Header | |
IO_L23N_T3_35 | IO_L23N_T3_35 | J27C.F11 | FMC conn. | ||||
IO_L23P_T3_35 | IO_L23P_T3_35 | J27C.F10 | FMC conn. | ||||
IO_L24N_T3_AD15N_35 | IO_L24N_T3_AD15N_35 | J27C.E10 | FMC conn. | FPGA_BANK35_AD15N | JP32.15 | Header | |
IO_L24P_T3_AD15P_35 | IO_L24P_T3_AD15P_35 | J27C.E9 | FMC conn. | FPGA_BANK35_AD15P | JP32.13 | Header | |
IO_L2N_T0_AD8N_35 | IO_L2N_T0_AD8N_35 | J27B.D24 | FMC conn. | FPGA_BANK35_AD8N | JP31.12 | Header | |
IO_L2P_T0_AD8P_35 | IO_L2P_T0_AD8P_35 | J27B.D23 | FMC conn. | FPGA_BANK35_AD8P | JP31.10 | Header | |
IO_L3N_T0_DQS_AD1N_35 | IO_L3N_T0_DQS_AD1N_35 | J27D.H29 | FMC conn. | FPGA_BANK35_AD1N | JP30.5 | Header | |
IO_L3P_T0_DQS_AD1P_35 | IO_L3P_T0_DQS_AD1P_35 | J27D.H28 | FMC conn. | FPGA_BANK35_AD1P | JP30.3 | Header | |
IO_L4N_T0_35 | IO_L4N_T0_35 | J27D.G28 | FMC conn. | ||||
IO_L4P_T0_35 | IO_L4P_T0_35 | J27D.G27 | FMC conn. | ||||
IO_L5N_T0_AD9N_35 | IO_L5N_T0_AD9N_35 | J27B.D27 | FMC conn. | FPGA_BANK35_AD9N | JP31.13 | Header | |
IO_L5P_T0_AD9P_35 | IO_L5P_T0_AD9P_35 | J27B.D26 | FMC conn. | FPGA_BANK35_AD9P | JP31.11 | Header | |
IO_L6N_T0_VREF_35 | IO_L6N_T0_VREF_35 | J27B.C27 | FMC conn. | ||||
TP23 | TP SMD | ||||||
IO_L6P_T0_35 | IO_L6P_T0_35 | J27B.C26 | FMC conn. | ||||
IO_L7N_T1_AD2N_35 | IO_L7N_T1_AD2N_35 | J27D.H32 | FMC conn. | FPGA_BANK35_AD2N | JP30.10 | Header | |
IO_L7P_T1_AD2P_35 | IO_L7P_T1_AD2P_35 | J27D.H31 | FMC conn. | FPGA_BANK35_AD2P | JP30.8 | Header | |
IO_L8N_T1_AD10N_35 | IO_L8N_T1_AD10N_35 | J27D.G31 | FMC conn. | FPGA_BANK35_AD10N | JP32.2 | Header | |
IO_L8P_T1_AD10P_35 | IO_L8P_T1_AD10P_35 | J27D.G30 | FMC conn. | FPGA_BANK35_AD10P | JP31.16 | Header | |
IO_L9N_T1_DQS_AD3N_35 | IO_L9N_T1_DQS_AD3N_35 | J27D.H35 | FMC conn. | FPGA_BANK35_AD3N | JP30.11 | Header | |
IO_L9P_T1_DQS_AD3P_35 | IO_L9P_T1_DQS_AD3P_35 | J27D.H34 | FMC conn. | FPGA_BANK35_AD3P | JP30.9 | Header | |
13
(not available on Zynq 7007S and 7010) |
IO_L11P_T1_SRCC_13 | IO_L23P_T3_13 | JP17.3 | PMOD [A] | |||
IO_L11N_T1_SRCC_13 | IO_L23N_T3_13 | JP17.4 | PMOD [A] | ||||
IO_L12P_T1_MRCC_13 | IO_L9P_T1_DQS_13 | JP17.2 | PMOD [A] | IO_L9P_T1_DQS_13 | J30.1 | ONE PIECE | |
IO_L12N_T1_MRCC_13 | IO_L9N_T1_DQS_13 | JP17.1 | PMOD [A] | IO_L9N_T1_DQS_13 | J30.3 | ONE PIECE | |
IO_L13P_T2_MRCC_13 | IO_L7P_T1_13 | JP17.7 | PMOD [A] | IO_L7P_T1_13 | J30.24 | ONE PIECE | |
IO_L13N_T2_MRCC_13 | IO_L7N_T1_13 | JP17.8 | PMOD [A] | IO_L7N_T1_13 | J30.26 | ONE PIECE | |
IO_L14P_T2_SRCC_13 | IO_L15P_T2_DQS_13 | n/a | ETH1_RXCK | IO_L15P_T2_DQS_13 | J30.25 | ONE PIECE | |
IO_L14N_T2_SRCC_13 | IO_L15N_T2_DQS_13 | n/a | ETH1_RXCTL | IO_L15N_T2_DQS_13 | J30.27 | ONE PIECE | |
IO_L15P_T2_DQS_13 | IO_L5P_T0_13 | JP17.6 | PMOD [A] | IO_L5P_T0_13 | J30.20 | ONE PIECE | |
IO_L15N_T2_DQS_13 | IO_L5N_T0_13 | JP17.5 | PMOD [A] | IO_L5N_T0_13 | J30.18 | ONE PIECE | |
IO_L16N_T2_13 | IO_L16N_T2_13 | n/a | ETH1_TXCTL | IO_L16N_T2_13 | J30.31 | ONE PIECE | |
IO_L16P_T2_13 | IO_L16P_T2_13 | n/a | ETH1_TXCK | IO_L16P_T2_13 | J30.29 | ONE PIECE | |
IO_L17N_T2_13 | IO_L17N_T2_13 | n/a | ETH1_RXD1 | IO_L17N_T2_13 | J30.35 | ONE PIECE | |
IO_L17P_T2_13 | IO_L17P_T2_13 | n/a | ETH1_RXD0 | IO_L17P_T2_13 | J30.33 | ONE PIECE | |
IO_L18N_T2_13 | IO_L18N_T2_13 | n/a | ETH1_RXD3 | IO_L18N_T2_13 | J30.39 | ONE PIECE | |
IO_L18P_T2_13 | IO_L18P_T2_13 | n/a | ETH1_RXD2 | IO_L18P_T2_13 | J30.37 | ONE PIECE | |
IO_L19N_T3_VREF_13 | IO_L19N_T3_VREF_13 | n/a | ETH1_TXD1 | IO_L19N_T3_VREF_13 | J30.43 | ONE PIECE | |
IO_L19P_T3_13 | IO_L19P_T3_13 | n/a | ETH1_TXD0 | IO_L19P_T3_13 | J30.41 | ONE PIECE | |
IO_L20N_T3_13 | IO_L20N_T3_13 | n/a | ETH1_TXD3 | IO_L20N_T3_13 | J30.47 | ONE PIECE | |
IO_L20P_T3_13 | IO_L20P_T3_13 | n/a | ETH1_TXD2 | IO_L20P_T3_13 | J30.45 | ONE PIECE | |
IO_L21N_T3_DQS_13 | IO_L21N_T3_DQS_13 | n/a | ETH1_MDC | IO_L21N_T3_DQS_13 | J30.51 | ONE PIECE | |
IO_L21P_T3_DQS_13 | IO_L21P_T3_DQS_13 | n/a | ETH1_MDIO | IO_L21P_T3_DQS_13 | J30.49 | ONE PIECE | |
IO_L22N_T3_13 | IO_L22N_T3_13 | IO_L22N_T3_13 | J30.55 | ONE PIECE | |||
IO_L22P_T3_13 | IO_L22P_T3_13 | n/a | DWM_WIFI_IRQ | IO_L22P_T3_13 | J30.53 | ONE PIECE | |
IO_L6N_T0_VREF_13 | IO_L6N_T0_VREF_13 | JP23.3 | PMOD [B] | IO_L6N_T0_VREF_13 | J30.30 | ONE PIECE | |
n/a | USB1_OC |
Edit
Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are not routed to the SoM due to the limited pin count of the SODIMM connector.
Bank | Carrier's signal |
---|---|
13 | IO_25_13 |
13 | IO_L1P_T0_13 |
13 | IO_L1N_T0_13 |
13 | IO_L2P_T0_13 |
13 | IO_L2N_T0_13 |
13 | IO_L3P_T0_DQS_13 |
13 | IO_L3N_T0_DQS_13 |
13 | IO_L4P_T0_13 |
13 | IO_L4N_T0_13 |
500 | NAND_CS0/SPI0_CS1 |
500 | NAND_IO3 |
500 | NAND_IO4 |
500 | NAND_IO5 |
500 | NAND_IO6 |
500 | NAND_IO7 |
500 | NAND_RD_B/VCFG1 |
500 | NAND_CLE/VCFG0 |
JTAGEdit
JTAGEdit
JTAG port is available as two different mechanical connectors:
- 2.00mm-pitch 7x2 header (Xilinx standard)
- 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
- This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
- JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
JTAG XILINX - J13Edit
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1, 3, 5, 7, 9, 11, 13 | DGND | - | - |
2 | 3.3V | - | - |
4 | JTAG_TMS | - | - |
6 | JTAG_TCK | - | - |
8 | JTAG_TDO | - | - |
10 | JTAG_TDI | - | - |
12 | N.C. | - | - |
14 | JTAG_TRSTn | - | - |
JTAG ARM - J18Edit
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | 3.3V | - | - |
2 | 3.3V | - | - |
3, 11, 17, 19 | N.C. | - | - |
4, 6 ,8 ,10 ,12, 14, 16, 18, 20 |
DGND | - | - |
5 | JTAG_TDI | - | - |
7 | JTAG_TMS | - | - |
9 | JTAG_TCK | - | - |
13 | JTAG_TDO | - | - |
15 | JTAG_TRSTn | - | - |
EthernetEdit
Ethernet port #0 (ETH0) - J8Edit
J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora Xpress integrated ethernet controller and PHY.
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | CT_TRD3 | center tap TRD3 | - |
2 | ETH_TXRX2_M | - | - |
3 | ETH_TXRX2_P | - | - |
4 | ETH_TXRX1_P | - | - |
5 | ETH_TXRX1_M | - | - |
6 | CT_TRD2 | center tap TRD2 | - |
7 | CT_TRD4 | center tap TRD4 | - |
8 | ETH_TXRX3_P | - | - |
9 | ETH_TXRX3_M | - | - |
10 | ETH_TXRX0_M | - | - |
11 | ETH_TXRX0_P | - | - |
12 | CT_TRD1 | center tap TRD1 | - |
13 | 3.3V_ETH0_LED2 | - | - |
15 | 3.3V_ETH0_LED1 | - | - |
14, 16 | +3.3V | - | - |
Ethernet port #1 (ETH1) - J9Edit
J9 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to Micrel KSZ9031 PHY (Gigabit Ethernet Transceiver). This, in turn, is connected to PL's bank 13 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem.
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | CT_TRD3 | center tap TRD3 | - |
2 | ETH1_TXRX2_M | - | - |
3 | ETH1_TXRX2_P | - | - |
4 | ETH1_TXRX1_P | - | - |
5 | ETH1_TXRX1_M | - | - |
6 | CT_TRD2 | center tap TRD2 | - |
7 | CT_TRD4 | center tap TRD4 | - |
8 | ETH1_TXRX3_P | - | - |
9 | ETH1_TXRX3_M | - | - |
10 | ETH1_TXRX0_M | - | - |
11 | ETH1_TXRX0_P | - | - |
12 | CT_TRD1 | center tap TRD1 | - |
13 | 3.3V_ETH1_LED2 | - | - |
15 | 3.3V_ETH1_LED1 | - | - |
14, 16 | +3.3V | - | - |
ConsoleEdit
UART1 - J17Edit
J17 is a standard DB9 connector that routes the signals coming from the RS232 transceiver that is connected to the PS MIO signals of the UART1 port.
Pin# | Pin name | Function | Notes |
---|---|---|---|
1, 6, 4, 9 | N.C. | N.C. | |
2 | UART_EXT_RX | Receive line | Connected to protection diode array |
3 | UART_EXT_TX | Transmit line | Connected to protection diode array |
5 | DGND | Ground | |
7, 8 | N.C. | N.C. | Connected to protection diode array |
SDEdit
MicroSD - J21Edit
J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | PS_SD0_DAT2 | - | - |
2 | PS_SD0_DAT3 | - | - |
3 | PS_SD0_CMD | - | - |
4 | 3.3V | - | - |
5 | PS_SD0_CLK | - | - |
6, 9, 10, 11, 12 | DGND | - | - |
7 | PS_SD0_DAT0 | - | - |
8 | PS_SD0_DAT1 | - | - |
3.3V | - | Pull up to 3.3V with 10K Ohm - |
USBEdit
USB OTG - J19Edit
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | USB_OTG_VBUS | - | - |
2 | USBM1 | - | - |
3 | USBP1 | - | - |
4 | OTG_ID | - | - |
5 | USB_OTG_DGND | - | - |
6, 7, 8, 9 | USB_OTG_SHIELD | - | - |
LVDSEdit
LVDS - J26Edit
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1, 2 | 3.3V_LCD | - | - |
3, 4, 7, 10, 13, 16, 19 |
DGND | Ground | - |
5 | LCD_LVDS_D0- | - | - |
6 | LCD_LVDS_D0+ | - | - |
8 | LCD_LVDS_D1- | - | - |
9 | LCD_LVDS_D1+ | - | - |
11 | LCD_LVDS_D2- | - | - |
12 | LCD_LVDS_D2+ | - | - |
14 | LCD_LVDS_CLK- | - | - |
15 | LCD_LVDS_CLK+ | - | - |
17 | LCD_P17 | - | - |
18 | LCD_P18 | - | - |
20 | LCD_P20 | - | - |
21,22 | DGND | Ground | Shield |
TouchscreenEdit
Touch screen - J25Edit
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | TSC_YP | - | - |
2 | TSC_XP | - | - |
3 | TSC_YM | - | - |
4 | TSC_XM | - | - |
CANEdit
CAN - J24Edit
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1, 6, 7, 8, 9, 10 |
N.C. | - | - |
2, 5 | CAN_SHIELD | - | - |
3 | CAN_L | - | - |
4 | CAN_H | - | - |
RTCEdit
FPGA, WatchDog, RTC, RST - JP22Edit
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | FPGA_INIT_B | - | - |
2 | RTC_32KHZ | - | - |
3 | FPGA_PROGRAM_B | - | - |
4 | RTC_RST | - | - |
5 | FPGA_DONE | - | - |
6 | RTC_INT/SQW | - | - |
7, 8 | DGND | Ground | - |
9 | WD_SET0 | - | - |
10 | SYS_RSTn | - | - |
11 | WD_SET1 | - | - |
12 | PORSTn | - | - |
13 | WD_SET2 | - | - |
14 | MRSTn | - | - |
15 | PS_MIO15_500 | - | - |
16 | CB_PWR_GOOD | - | - |
WatchdogEdit
WatchDog Settings - S1, S2 and S3Edit
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog. For more details please refer to this page.
S1.1 | S1.2 | |
---|---|---|
WD_SET0 SOM default | OFF | OFF |
WD_SET0 = '1' | ON | OFF |
WD_SET0 = '0' | OFF | ON |
S2.1 | S2.2 | |
---|---|---|
WD_SET1 SOM default | OFF | OFF |
WD_SET1 = '1' | ON | OFF |
WD_SET1 = '0' | OFF | ON |
S3.1 | S3.2 | |
---|---|---|
WD_SET2 SOM default | OFF | OFF |
WD_SET2 = '1' | ON | OFF |
WD_SET2 = '0' | OFF | ON |
DWMEdit
DWM (DAVE Wifi/BT module) socket - J23Edit
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the DWM Wireless Module (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1, 2 | 5V | - | - |
3, 4 | 3.3V | - | - |
5, 6, 9, 10, 19 |
DGND | - | - |
7 | DWM_SD_CMD | - | - |
8 | DWM_SD_CLK | - | - |
11 | DWM_SD_DAT0 | - | - |
12, 14, 16, 18, 20, 22 |
N.C. | - | - |
13 | DWM_SD_DAT1 | - | - |
15 | DWM_SD_DAT2 | - | - |
17 | DWM_SD_DAT3 | - | - |
21 | DWM_UART_RX | - | - |
23 | DWM_UART_CTS | - | - |
24 | DWM_BT_F5 | - | - |
25 | DWM_UART_TX | - | - |
26 | DWM_BT_F2 | - | - |
27 | DWM_UART_RTS | - | - |
28 | DWM_WIFI_IRQ | - | - |
29 | DWM_BT_EN | - | - |
30 | DWM_WIFI_EN | - | - |
PMODEdit
Digilent Pmod™ Compatible headersEdit
Please note that:
- Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
- Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector
Digilent Pmod™ Compatible - JP17Edit
JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | PMOD_A0 | - | |
2 | PMOD_A4 | - | |
3 | PMOD_A1 | - | |
4 | PMOD_A5 | - | |
5 | PMOD_A2 | - | |
6 | PMOD_A6 | - | |
7 | PMOD_A3 | - | |
8 | PMOD_A7 | - | |
9, 10 | DGND | Ground | - |
11, 12 | 3.3V | - |
Digilent Pmod™ Compatible - JP23Edit
JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | PMOD_B0 | - | - |
2 | PMOD_B4 | - | - |
3 | PMOD_B1 | - | - |
4 | PMOD_B5 | - | - |
5 | PMOD_B2 | - | - |
6 | PMOD_B6 | - | - |
7 | PMOD_B3 | - | - |
8 | PMOD_B7 | - | - |
9, 10 | DGND | Ground | - |
11, 12 | 3.3V | - | - |
FMCEdit
FPGA Mezzanine Card (FMC) Connector - J27Edit
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
Please note that BoraXpress EVB FMC Connector is:
- fully compliant to FMC LPC
- partially compliant to FMC HPC because HPC side is not fully populated.
The following tables detail how BORA Xpress signals have been routed to FMC connector. At this link a spreadsheet providing the same information is available for download.
For more information about I/O voltage of single-ended signals available on FMC connector, please refer to this section.
HPC Row AEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
A1 | DGND | GND | |
A2 | MGTxRXP1 | DP1_M2C_P | |
A3 | MGTxRXN1 | DP1_M2C_N | |
A4 | DGND | GND | |
A5 | DGND | GND | |
A6 | MGTxRXP2 | DP2_M2C_P | |
A7 | MGTxRXN2 | DP2_M2C_N | |
A8 | DGND | GND | |
A9 | DGND | GND | |
A10 | MGTxRXP3 | DP3_M2C_P | |
A11 | MGTxRXN3 | DP3_M2C_N | |
A12 | DGND | GND | |
A13 | DGND | GND | |
A14 | not connected | DP4_M2C_P | |
A15 | not connected | DP4_M2C_N | |
A16 | DGND | GND | |
A17 | DGND | GND | |
A18 | not connected | DP5_M2C_P | |
A19 | not connected | DP5_M2C_N | |
A20 | DGND | GND | |
A21 | DGND | GND | |
A22 | MGTxTXP1 | DP1_C2M_P | |
A23 | MGTxTXN1 | DP1_C2M_N | |
A24 | DGND | GND | |
A25 | DGND | GND | |
A26 | MGTxTXP2 | DP2_C2M_P | |
A27 | MGTxTXN2 | DP2_C2M_N | |
A28 | DGND | GND | |
A29 | DGND | GND | |
A30 | MGTxTXP3 | DP3_C2M_P | |
A31 | MGTxTXN3 | DP3_C2M_N | |
A32 | DGND | GND | |
A33 | DGND | GND | |
A34 | not connected | DP4_C2M_P | |
A35 | not connected | DP4_C2M_N | |
A36 | DGND | GND | |
A37 | DGND | GND | |
A38 | not connected | DP5_C2M_P | |
A39 | not connected | DP5_C2M_N | |
A40 | DGND | GND |
HPC Row BEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
B1 | RSVD | RES1 | |
B2 | DGND | GND | |
B3 | DGND | GND | |
B4 | not connected | DP9_M2C_P | |
B5 | not connected | DP9_M2C_N | |
B6 | DGND | GND | |
B7 | DGND | GND | |
B8 | not connected | DP8_M2C_P | |
B9 | not connected | DP8_M2C_N | |
B10 | DGND | GND | |
B11 | DGND | GND | |
B12 | not connected | DP7_M2C_P | |
B13 | not connected | DP7_M2C_N | |
B14 | DGND | GND | |
B15 | DGND | GND | |
B16 | not connected | DP6_M2C_P | |
B17 | not connected | DP6_M2C_N | |
B18 | DGND | GND | |
B19 | DGND | GND | |
B20 | MGTREFCLK1P | GBTCLK1_M2C_P | |
B21 | MGTREFCLK1N | GBTCLK1_M2C_N | |
B22 | DGND | GND | |
B23 | DGND | GND | |
B24 | not connected | DP9_C2M_P | |
B25 | not connected | DP9_C2M_N | |
B26 | DGND | GND | |
B27 | DGND | GND | |
B28 | not connected | DP8_C2M_P | |
B29 | not connected | DP8_C2M_N | |
B30 | DGND | GND | |
B31 | DGND | GND | |
B32 | not connected | DP7_C2M_P | |
B33 | not connected | DP7_C2M_N | |
B34 | DGND | GND | |
B35 | DGND | GND | |
B36 | not connected | DP6_C2M_P | |
B37 | not connected | DP6_C2M_N | |
B38 | DGND | GND | |
B39 | DGND | GND | |
B40 | RSVD | RES0 |
LPC Row CEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
C1 | DGND | GND | |
C2 | MGTxTXP0 | DP0_C2M_P | |
C3 | MGTxTXN0 | DP0_C2M_N | |
C4 | DGND | GND | |
C5 | DGND | GND | |
C6 | MGTxRXP0 | DP0_M2C_P | |
C7 | MGTxRXN0 | DP0_M2C_N | |
C8 | DGND | GND | |
C9 | DGND | GND | |
C10 | IO_L23P_T3_34 | LA06_P | |
C11 | IO_L23N_T3_34 | LA06_N | |
C12 | DGND | GND | |
C13 | DGND | GND | |
C14 | IO_L2P_T0_34 | LA10_P | |
C15 | IO_L2N_T0_34 | LA10_N | |
C16 | DGND | GND | |
C17 | DGND | GND | |
C18 | IO_L1P_T0_34 | LA14_P | |
C19 | IO_L1N_T0_34 | LA14_N | |
C20 | DGND | GND | |
C21 | DGND | GND | |
C22 | IO_L16P_T2_34 | LA18_P_CC | |
C23 | IO_L16N_T2_34 | LA18_N_CC | |
C24 | DGND | GND | |
C25 | DGND | GND | |
C26 | IO_L6P_T0_35 | LA27_P | |
C27 | IO_L6N_T0_VREF_35 | LA27_N | |
C28 | DGND | GND | |
C29 | DGND | GND | |
C30 | I2C0_SCL | SCL | |
C31 | I2C0_SDA | SDA | |
C32 | DGND | GND | |
C33 | DGND | GND | |
C34 | GA0 | GA0 | |
C35 | FMC_12P0V | 12P0V | |
C36 | DGND | GND | |
C37 | FMC_12P0V | 12P0V | |
C38 | DGND | GND | |
C39 | FMC_3P3V | 3P3V | |
C40 | DGND | GND |
LPC Row DEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
D1 | IO_25_VRP_34 | PG_C2M | |
D2 | DGND | GND | |
D3 | DGND | GND | |
D4 | MGTREFCLK0P | GBTCLK0_M2C_P | |
D5 | MGTREFCLK0N | GBTCLK0_M2C_N | |
D6 | DGND | GND | |
D7 | DGND | GND | |
D8 | IO_L14P_T2_SRCC_34 | LA01_P_CC | |
D9 | IO_L14N_T2_SRCC_34 | LA01_N_CC | |
D10 | DGND | GND | |
D11 | IO_L9P_T1_DQS_34 | LA05_P | |
D12 | IO_L9N_T1_DQS_34 | LA05_N | |
D13 | DGND | GND | |
D14 | IO_L6P_T0_34 | LA09_P | |
D15 | IO_L6N_T0_VREF_34 | LA09_N | |
D16 | DGND | GND | |
D17 | IO_L20P_T3_34 | LA13_P | |
D18 | IO_L20N_T3_34 | LA13_N | |
D19 | DGND | GND | |
D20 | IO_L15P_T2_DQS_34 | LA17_P_CC | |
D21 | IO_L15N_T2_DQS_34 | LA17_N_CC | |
D22 | DGND | GND | |
D23 | IO_L2P_T0_AD8P_35 | LA23_P | |
D24 | IO_L2N_T0_AD8N_35 | LA23_N | |
D25 | DGND | GND | |
D26 | IO_L5P_T0_AD9P_35 | LA26_P | |
D27 | IO_L5N_T0_AD9N_35 | LA26_N | |
D28 | DGND | GND | |
D29 | JTAG_TCK | TCK | |
D30 | JTAG_TDI | TDI | |
D31 | FMC_TDO_ZYNQ_TDI | TDO | |
D32 | FMC_3P3VAUX | 3P3VAUX | |
D33 | JTAG_TMS | TMS | |
D34 | JTAG_TRSTn | TRST_L | |
D35 | GA0 | GA1 | |
D36 | FMC_3P3V | 3P3V | |
D37 | DGND | GND | |
D38 | FMC_3P3V | 3P3V | |
D39 | DGND | GND | |
D40 | FMC_3P3V | 3P3V |
HPC Row EEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
E1 | DGND | GND | |
E2 | IO_L14P_T2_AD4P_SRCC_35 | HA01_P_CC | |
E3 | IO_L14N_T2_AD4N_SRCC_35 | HA01_N_CC | |
E4 | DGND | GND | |
E5 | DGND | GND | |
E6 | IO_L20P_T3_AD6P_35 | HA05_P | |
E7 | IO_L20N_T3_AD6N_35 | HA05_N | |
E8 | DGND | GND | |
E9 | IO_L24P_T3_AD15P_35 | HA09_P | |
E10 | IO_L24N_T3_AD15N_35 | HA09_N | |
E11 | DGND | GND | |
E12 | not connected | HA13_P | |
E13 | not connected | HA13_N | |
E14 | DGND | GND | |
E15 | not connected | HA16_P | |
E16 | not connected | HA16_N | |
E17 | DGND | GND | |
E18 | not connected | HA20_P | |
E19 | not connected | HA20_N | |
E20 | DGND | GND | |
E21 | not connected | HB03_P | |
E22 | not connected | HB03_N | |
E23 | DGND | GND | |
E24 | not connected | HB05_P | |
E25 | not connected | HB05_N | |
E26 | DGND | GND | |
E27 | not connected | HB09_P | |
E28 | not connected | HB09_N | |
E29 | DGND | GND | |
E30 | not connected | HB13_P | |
E31 | not connected | HB13_N | |
E32 | DGND | GND | |
E33 | not connected | HB19_P | |
E34 | not connected | HB19_N | |
E35 | DGND | GND | |
E36 | not connected | HB21_P | |
E37 | not connected | HB21_N | |
E38 | DGND | GND | |
E39 | FMC_VADJ | VADJ | |
E40 | DGND | GND |
HPC Row FEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
F1 | IO_0_VRN_35 | PG_M2C | |
F2 | DGND | GND | |
F3 | DGND | GND | |
F4 | IO_L13P_T2_MRCC_35 | HA00_P_CC | |
F5 | IO_L13N_T2_MRCC_35 | HA00_N_CC | |
F6 | DGND | GND | |
F7 | IO_L19P_T3_35 | HA04_P | |
F8 | IO_L19N_T3_VREF_35 | HA04_N | |
F9 | DGND | GND | |
F10 | IO_L23P_T3_35 | HA08_P | |
F11 | IO_L23N_T3_35 | HA08_N | |
F12 | DGND | GND | |
F13 | not connected | HA12_P | |
F14 | not connected | HA12_N | |
F15 | DGND | GND | |
F16 | not connected | HA15_P | |
F17 | not connected | HA15_N | |
F18 | DGND | GND | |
F19 | not connected | HA19_P | |
F20 | not connected | HA19_N | |
F21 | DGND | GND | |
F22 | not connected | HB02_P | |
F23 | not connected | HB02_N | |
F24 | DGND | GND | |
F25 | not connected | HB04_P | |
F26 | not connected | HB04_N | |
F27 | DGND | GND | |
F28 | not connected | HB08_P | |
F29 | not connected | HB08_N | |
F30 | DGND | GND | |
F31 | not connected | HB12_P | |
F32 | not connected | HB12_N | |
F33 | DGND | GND | |
F34 | not connected | HB16_P | |
F35 | not connected | HB16_N | |
F36 | DGND | GND | |
F37 | not connected | HB20_P | |
F38 | not connected | HB20_N | |
F39 | DGND | GND | |
F40 | FMC_VADJ | VADJ |
LPC Row GEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
G1 | DGND | GND | |
G2 | IO_L11P_T1_SRCC_34 | CLK0_C2M_P | |
G3 | IO_L11N_T1_SRCC_34 | CLK0_C2M_N | |
G4 | DGND | GND | |
G5 | DGND | GND | |
G6 | IO_L13P_T1_MRCC_34 | LA00_P_CC | |
G7 | IO_L13N_T1_MRCC_34 | LA00_N_CC | |
G8 | DGND | GND | |
G9 | IO_L4P_T0_34 | LA03_P | |
G10 | IO_L4N_T0_34 | LA03_N | |
G11 | DGND | GND | |
G12 | IO_L3P_T0_DQS_PUDC_B_34 | LA08_P | |
G13 | IO_L3N_T0_DQS_34 | LA08_N | |
G14 | DGND | GND | |
G15 | IO_L22P_T3_34 | LA12_P | |
G16 | IO_L22N_T3_34 | LA12_N | |
G17 | DGND | GND | |
G18 | IO_L19P_T3_34 | LA16_P | |
G19 | IO_L19N_T3_VREF_34 | LA16_N | |
G20 | DGND | GND | |
G21 | IO_L17P_T2_34 | LA20_P | |
G22 | IO_L17N_T2_34 | LA20_N | |
G23 | DGND | GND | |
G24 | IO_L1P_T0_AD0P_35 | LA22_P | |
G25 | IO_L1N_T0_AD0N_35 | LA22_N | |
G26 | DGND | GND | |
G27 | IO_L4P_T0_35 | LA25_P | |
G28 | IO_L4N_T0_35 | LA25_N | |
G29 | DGND | GND | |
G30 | IO_L8P_T1_AD10P_35 | LA29_P | |
G31 | IO_L8N_T1_AD10N_35 | LA29_N | |
G32 | DGND | GND | |
G33 | IO_L10P_T1_AD11P_35 | LA31_P | |
G34 | IO_L10N_T1_AD11N_35 | LA31_N | |
G35 | DGND | GND | |
G36 | IO_L16P_T2_35 | LA33_P | |
G37 | IO_L16N_T2_35 | LA33_N | |
G38 | DGND | GND | |
G39 | FMC_VADJ | VADJ | |
G40 | DGND | GND |
LPC Row HEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
H1 | FMC_VREF_A_M2C | VREF_A_M2C | |
H2 | FMC_PRSNT_M2C_L | PRSNT_M2C_L | |
H3 | DGND | GND | |
H4 | IO_L12P_T1_MRCC_34 | CLK0_M2C_P | |
H5 | IO_L12N_T1_MRCC_34 | CLK0_M2C_N | |
H6 | DGND | GND | |
H7 | IO_L7P_T1_34 | LA02_P | |
H8 | IO_L7N_T1_34 | LA02_N | |
H9 | DGND | GND | |
H10 | IO_L5P_T0_34 | LA04_P | |
H11 | IO_L5N_T0_34 | LA04_N | |
H12 | DGND | GND | |
H13 | IO_L8P_T1_34 | LA07_P | |
H14 | IO_L8N_T1_34 | LA07_N | |
H15 | DGND | GND | |
H16 | IO_L21P_T3_DQS_34 | LA11_P | |
H17 | IO_L21N_T3_DQS_34 | LA11_N | |
H18 | DGND | GND | |
H19 | IO_L18P_T2_34 | LA15_P | |
H20 | IO_L18N_T2_34 | LA15_N | |
H21 | DGND | GND | |
H22 | IO_L24P_T3_34 | LA19_P | |
H23 | IO_L24N_T3_34 | LA19_N | |
H24 | DGND | GND | |
H25 | IO_L10P_T1_34 | LA21_P | |
H26 | IO_L10N_T1_34 | LA21_N | |
H27 | DGND | GND | |
H28 | IO_L3P_T0_DQS_AD1P_35 | LA24_P | |
H29 | IO_L3N_T0_DQS_AD1N_35 | LA24_N | |
H30 | DGND | GND | |
H31 | IO_L7P_T1_AD2P_35 | LA28_P | |
H32 | IO_L7N_T1_AD2N_35 | LA28_N | |
H33 | DGND | GND | |
H34 | IO_L9P_T1_DQS_AD3P_35 | LA30_P | |
H35 | IO_L9N_T1_DQS_AD3N_35 | LA30_N | |
H36 | DGND | GND | |
H37 | IO_L15P_T2_DQS_AD12P_35 | LA32_P | |
H38 | IO_L15N_T2_DQS_AD12N_35 | LA32_N | |
H39 | DGND | GND | |
H40 | FMC_VADJ | VADJ |
HPC Row JEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
J1 | DGND | GND | |
J2 | IO_L11P_T1_SRCC_35 | CLK1_C2M_P | |
J3 | IO_L11N_T1_SRCC_35 | CLK1_C2M_N | |
J4 | DGND | GND | |
J5 | DGND | GND | |
J6 | IO_L18P_T2_AD13P_35 | HA03_P | |
J7 | IO_L18N_T2_AD13N_35 | HA03_N | |
J8 | DGND | GND | |
J9 | IO_L22P_T3_AD7P_35 | HA07_P | |
J10 | IO_L22N_T3_AD7N_35 | HA07_N | |
J11 | DGND | GND | |
J12 | not connected | HA11_P | |
J13 | not connected | HA11_N | |
J14 | DGND | GND | |
J15 | not connected | HA14_P | |
J16 | not connected | HA14_N | |
J17 | DGND | GND | |
J18 | not connected | HA18_P | |
J19 | not connected | HA18_N | |
J20 | DGND | GND | |
J21 | not connected | HA22_P | |
J22 | not connected | HA22_N | |
J23 | DGND | GND | |
J24 | not connected | HB01_P | |
J25 | not connected | HB01_N | |
J26 | DGND | GND | |
J27 | not connected | HB07_P | |
J28 | not connected | HB07_N | |
J29 | DGND | GND | |
J30 | not connected | HB11_P | |
J31 | not connected | HB11_N | |
J32 | DGND | GND | |
J33 | not connected | HB15_P | |
J34 | not connected | HB15_N | |
J35 | DGND | GND | |
J36 | not connected | HB18_P | |
J37 | not connected | HB18_N | |
J38 | DGND | GND | |
J39 | not connected | VIO_B_M2C | |
J40 | DGND | GND |
HPC Row KEdit
Pin# | Pin name | Function | Notes |
---|---|---|---|
K1 | not connected | VREF_B_M2C | |
K2 | DGND | GND | |
K3 | DGND | GND | |
K4 | IO_L12P_T1_MRCC_35 | CLK1_M2C_P | |
K5 | IO_L12N_T1_MRCC_35 | CLK1_M2C_N | |
K6 | DGND | GND | |
K7 | IO_L17P_T2_AD5P_35 | HA02_P | |
K8 | IO_L17N_T2_AD5N_35 | HA02_N | |
K9 | DGND | GND | |
K10 | IO_L21P_T3_DQS_AD14P_35 | HA06_P | |
K11 | IO_L21N_T3_DQS_AD14N_35 | HA06_N | |
K12 | DGND | GND | |
K13 | IO_25_VRP_35 | HA10_P | |
K14 | not connected | HA10_N | |
K15 | DGND | GND | |
K16 | not connected | HA17_P_CC | |
K17 | not connected | HA17_N_CC | |
K18 | DGND | GND | |
K19 | not connected | HA21_P | |
K20 | not connected | HA21_N | |
K21 | DGND | GND | |
K22 | not connected | HA23_P | |
K23 | not connected | HA23_N | |
K24 | DGND | GND | |
K25 | not connected | HB00_P_CC | |
K26 | not connected | HB00_N_CC | |
K27 | DGND | GND | |
K28 | not connected | HB06_P_CC | |
K29 | not connected | HB06_N_CC | |
K30 | DGND | GND | |
K31 | not connected | HB10_P | |
K32 | not connected | HB10_N | |
K33 | DGND | GND | |
K34 | not connected | HB14_P | |
K35 | not connected | HB14_N | |
K36 | DGND | GND | |
K37 | not connected | HB17_P_CC | |
K38 | not connected | HB17_N_CC | |
K39 | DGND | GND | |
K40 | not connected | VIO_B_M2C |
Electrical and Mechanical DocumentsEdit
SchematicsEdit
BOMEdit
- BoraXEVB: BORAXEVB_S.EVBBX0000C0R.1.6.0.CSV.zip
LayoutEdit
PCB design (Mentor PADS)Edit
BORA Lite AdapterEdit
BORA Lite requires a dedicated adapter to be plugged to the BoraXEVB carrier board. This adapter:
- provides the SODIMM socket for the BORA Lite SOM
- provides the following additional features:
- microSD slot (for SD boot)
- JTAG connector
- CAN traslator for testing the CAN bus on BoraXEVB
- routes the signals from the BORA Lite pins to the BoraXEVB mating connectors
The following images show the top and bottom views of the BoraLite Adapter:
Connectors' pinoutEdit
J1 - SODIMM connectorEdit
J1 is a TE Connectivity 204-pin SODIMM socket. The pinout matches the Axel Lite pinout.
J4, J5, J6 - BoraXEVB mating connectorsEdit
J4, J5 and J6 are Hirose FX8C-140S-SV connectors that match the BoraXEVB SOM connectors' pinout.
J2 - JTAGEdit
J2 is a SAMTEC FSI-110-03-G-S connector. The following table reports the connector's pinout:
Pin# | Pin name | Function | Notes |
---|---|---|---|
1 | DGND | - | - |
2 | JTAG_TCK | - | - |
3 | JTAG_TMS | - | - |
4 | JTAG_TDO | - | - |
5 | JTAG_TDI | - | - |
6 | FPGA_INIT_B | - | - |
7 | FPGA_PROGRAM_B | - | - |
8 | FPGA_DONE | - | - |
9 | D.N.C. | - | - |
10 | 3V3 | - | - |
Routing optionsEdit
This table helps to map Bora Lite's signals when it is mated with the BoraXEVB carrier board. That table assumes that the adapter is populated according to the default mounting option, which is illustrated in the schematics available here.
At the adapter level, other mounting options are available, however. Please refer to the schematics for more details.
CAN busEdit
Pins IO_L6P_T0_34 and IO_L19P_T3_34 can be used as CAN_TX and CAN_RX for the CAN0 interface. The BoraLite adapter provide the SN65HVD232 CAN bus transceiver required for proper CAN bus bus interface.
The CAN_L and CAN_H translated signals are routed to the J5.103 and J5.105 connector pins on BoraXEVB.
Technical documentationEdit
SchematicsEdit
BOMEdit
LayoutEdit
MechanicalEdit
- DXF: boraxevb-2D-CS143714
- IDF (3D): boraxevb-3D-CS143714
- STEP (3D): boraxevb_3D_step_cs143714