The microSD card provided with BELK/BXELK is partitioned as shown in the following image:
It is worth remembering that the microSD card is [[System boot and recovery via microSD card (BELK/BXELK)|bootable]] and U-Boot environment is retrieved from (and stored to with <code>saveenv</code>) into the FAT partition as <code>bora.env</code>
In BELK/BXELK, the following source trees are clones of the correspondent '''DAVE Embedded Systems''' git repositories:
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For more information about the access to these repositories, please refer to [[Build_system_(BELK/BXELK)Accessing_DAVE_Embedded_Systems_restricted_git_repositories#U-Boot_and_Linux_git_repositoriesPublic_key_access|this link]].
=== Updating the repositories from BELK 2.1.0 ===
When the account is enabled, you can synchronize a source tree entering the repository directory and launching the <code>git fetch</code> command. Please note that <code>git fetch</code> doesn't merge the commits on the current branch. To do that, you should run the <code>git merge</code> command or replace the ''fetch-merge'' process with a single <code>git pull</code> command. Please note that the recommended method is the ''fetch-merge'' process. For further information on Git, please refer to [http://git-scm.com/documentation Git Documentation].
<section end=Synchronizingthegitrepositories/>
<section begin=Releasenotes/>
== Release notes ==
<section end="Synchronizing" the="" git="" repositoriesBELK 4.1.4 ="" />== Updates:# Fixes for MAC programming on [[BELK-TN-010: MAC address programming on OTP|NOR SPI OTP]]
<section begin="Release" notes="" />== Known Limitations ====
{| class== Release notes =="wikitable" |-!ID!Component!Subsystem!Description|-|0001|BoraEVB|External DDR3 bank (BoraEVB only)|DDR3 bank can be populated on request. For more details please refer to [mailto:sales@dave.eu Sales Department].|-|0002|BoraEVB/BoraXEVB|ETH1 interface|Please refer to [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB|this application note]] for second Ethernet interface support.|-|0003|BoraEVB/BoraXEVB|RTC|Date/time retention is limited to about 4 hours.|-|0004|BoraEVB/BoraXEVB|System clock runs slower|As per [https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841831/CPU+frequency+scaling#Missing%20Features,%20Known%20Issues%20and%20Limitations Xilinx issue], @333MHz (speedgrade -3) system clock is slower then expected|}