View source for BELK/BXELK software components

==== Known Limitations ====

{| class="wikitable" 
|-
!ID
!Component
!Subsystem
!Description
|-
|0001
|BoraEVB
|External DDR3 bank (BoraEVB only)
|DDR3 bank can be populated on request. For more details please refer to [mailto:sales@dave.eu Sales Department].
|-
|0002
|BoraEVB/BoraXEVB
|ETH1 interface
|Please refer to [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB|this application note]] for second Ethernet interface support.
|-
|0003
|BoraEVB/BoraXEVB
|RTC
|Date/time retention is limited to about 4 hours.
|-
|0004
|BoraEVB/BoraXEVB
|System clock runs slower
|As per [https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841831/CPU+frequency+scaling#Missing%20Features,%20Known%20Issues%20and%20Limitations Xilinx issue], @333MHz (speedgrade -3) system clock is slower then expected
|}