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BELK-TN-013: Managing ethernet and USB physical transceivers reset

224 bytes removed, 09:37, 9 September 2022
→‎Reference
|-
|1.0.0
|Apri Apr 2022
|[[BORA_SOM/BELK-L/General/Release_Notes#BELK_4.1.5|4.1.5]]
|First release
== Introduction ==
This technical note provides some information for managing the rest reset of Ethernet and USB physical transceivers used in [[BORA SOM |BORA]], [[BORA Xpress SOM |BORA Xpress]] and [[BORA Lite SOM |BORA Lite]] DAVE Embedded Systems' SOMs.
=== Reference ===
The BORA and BORA Xpress ethernet and USB PHY reset signals are actually managed by the two MIO pins dedicated to this functionality. The MIO pins are documented in the Power and Reset wiki page for [[BORA_SOM/BORA_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_501 PS_MIO51_501_.28Ethernet_PHY_reset.29 | PS MIO51 501]] and [[BORA_SOM/BORA_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_500 PS_MIO50_501_.28USB_PHY_reset.29 | PS MIO50 501]] pins.
== Hardware reset using MIO pins ==
The default configuration for the two PHY reset signals is managed - by default - in the BORA and BORA Xpress SOMS using the two dedicated [[BORA_SOM/BORA_Hardware/Peripherals/Processing_System_(PS)| MIO pins]].
Those These MIO pins are connected to the PHY reset signals and the reset pulse is can be generated at using a proper software levelsroutine.
=== U-Boot PHY reset ===
int board_init(void)
</pre>
 
In this specific case, the reset pulse is generated directly by writing in the MIO registers as per the following source code:
 
<pre class="board-terminal">
/*
* temporary hack to take USB0 out of reset
*/
temp = readl(0xE000A244);
writel(temp | USB0_rst , 0xE000A244);
temp = readl(0xE000A248);
writel(temp | USB0_rst , 0xE000A248);
temp = readl(0xE000A044);
writel(temp & ~USB0_rst , 0xE000A044);
udelay(10000); // pause for 10ms
temp = readl(0xE000A044);
writel(temp | USB0_rst , 0xE000A044);
 
/*
* temporary hack to take ETH PHY out of reset
*/
temp = readl(0xE000A244);
writel((temp | ETH0_rst) , 0xE000A244);
temp = readl(0xE000A248);
writel((temp | ETH0_rst), 0xE000A248);
writel((temp & ~ETH0_rst), 0xE000A044);
mdelay(500); /* 500ms */
temp = readl(0xE000A044);
writel((temp | ETH0_rst), 0xE000A044);
</pre>
 
=== kernel PHY reset ===
The Linux kernel is assumed to find the two physical transceivers '''already reset'''. So, the hardware reset is not implemented at ''driver nor userspace '' levels.
==== ethernet ====
The ethernet PHY kernel driver, i.e. <code>drivers/net/ethernet/cadence/macb.c</code> supports a device tree entrry entry for generating the hardware reset pulse.
It is enough to add the following entries in order to let the kernel to reset the PHY too:
phy-handle = <&phy0>;
<b>phy-reset-gpio = <&gpio0 51 1>;
phy-reset-duration = <100>; phy-reset-active-low;</b>
...
...
==== USB ====
For issuing a reset pulse to the USB PHY, a dedicated kernel hacking is has to be realized; implemented: the USB PHY driver to be modified is the ULPI <code>drivers/netusb/phy/micrelphy-ulpi.c</code> kernel driver and then . An example of a USB driver with the proper BSP modifications have to hardware reset capability can be found on <code>drivers/usb/phy/phy-generic.c</code>. The reset management, via device tree property <code>reset-gpios</code> can be evaluatedused as a reference for implementing the hacking in the ULPI driver.
== Software reset ==
The ethernet PHY - in general - supports a software reset via the BCMR register. The MAC kernel driver issues a software reset during the ''phy attach'' to the ethernet device:
 
<pre>
ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
</pre>
 
in the <code>genphy_soft_reset</code> function.
U0007
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