== Hardware reset using MIO pins ==
The default configuration for the two PHY reset signals is managed - by default - in the BORA and BORA Xpress SOMS using the two dedicated [[BORA_SOM/BORA_Hardware/Peripherals/Processing_System_(PS)| MIO pins]].
Those MIO pins are connected to the PHY reset signals and the reset pulse is generated at software levels.
int board_init(void)
</pre>
In this specific case, the reset pulse is generated directly by writing in the MIO registers as per the following source code:
<pre class="board-terminal">
/*
* temporary hack to take USB0 out of reset
*/
temp = readl(0xE000A244);
writel(temp | USB0_rst , 0xE000A244);
temp = readl(0xE000A248);
writel(temp | USB0_rst , 0xE000A248);
temp = readl(0xE000A044);
writel(temp & ~USB0_rst , 0xE000A044);
udelay(10000); // pause for 10ms
temp = readl(0xE000A044);
writel(temp | USB0_rst , 0xE000A044);
/*
* temporary hack to take ETH PHY out of reset
*/
temp = readl(0xE000A244);
writel((temp | ETH0_rst) , 0xE000A244);
temp = readl(0xE000A248);
writel((temp | ETH0_rst), 0xE000A248);
writel((temp & ~ETH0_rst), 0xE000A044);
mdelay(500); /* 500ms */
temp = readl(0xE000A044);
writel((temp | ETH0_rst), 0xE000A044);
</pre>
=== kernel PHY reset ===