- /* instruzioni di setup vivado */ - *Open a new Vivado project, select "RTL project" and "BORA SOM" as target board - *Create your block design - **Add "FIR compiler" block (included in Vivado default IP) and setup it. To create a new filter block starting from the code c read the paragraph %CREATE A NEW BLOCK IP FROM C CODE% - **Add "AXI direct memory access" block and setup it - **Enable on "ZYNQ7 Processing System" block an "High Performance AXI 32b/64b Slave Ports" on interface HP0 - **Connect AXIS_DATA bus of AXI and FIR block - **"Run Connection Automation" to complete wiring - *create Hierarchy of AXI and FIR block named "filter" - *export bitstream file running "Generate Bitstream" - *export block design using tcl console command "write_bd_tcl </path/name>.tcl" - *rename generated files as "<overlay_name>.bit" and "<overlay_name>.tcl" - *create folder <overlay_name> and insert generated files - *copy folder in PYNQ target in pynq/overlays/
Overlay is ready to use in PYNQ Python console.
/*
/* sezione da approfondire e riscrivere meglio */
- *Load Overlay and Xlnx modules from pynq and pynq.lib.dma. - *Create Overlay and Xlnk object - *you can comunicate directly on dma buffer.
/*
/* da testare exportazione con diversi setaggi da vivado per checkhierarchy */
- *import DefaultHierarchy from pynq - *create a new class for fir filter with a method to comunicate directly on dma buffer - *create a checkhierarchy method to check ip contained under "filter" hierarchy
/*