This approach makes use of a different method to implement the filter. In this case, the filter was written in C++ and implemented by using [https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html Vivado High-Level Synthesis (HLS)]. The fundamental steps required to do this are: *Opening a new Vivado HLS project, selecting Bora SOM as the target board*Creating a new C++ source file*Writing C++ code of FIR custom IP**Creating AXI Stream interfaces for input and output**Defining FIR coefficients and normalize value**Using some pragmas to optimize the execution of algorithm /* CODICE IP VIVADO */ - Synthesizing new IP running "Run C synthesis" - Exporting new IP running "Export RTL" - Opening a new Vivado project, selecting RTL project and Bora SOM as the target board - Adding the new IP in IP list - Opening "IP Catalog" - Adding repository of the custom IP Now continue as before to complete ed export Vivado project.