Bureaucrats, dave_user, Administrators
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{{Applies To Bora}}
{{Applies To BoraX}}
{{AppliesToBORA_TN}}
{{AppliesToBORA_Xpress_TN}}
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*Load <code>Overlay</code> and <code>Xlnx</code> modules from <code>pynq</code> and <code>pynq.lib.dma</code>.
*Create <code>Overlay</code> and <code>Xlnk</code> objects
These steps allows you to communicate directly through a DMA buffer.
*Writing C++ code of FIR custom IP
**Creating AXI Stream interfaces for input and output
**Defining FIR coefficients and normalize valuenormalizing their values**Using some #pragmas to optimize the execution of the algorithm /* CODICE IP VIVADO */*Synthesizing new IP running "''Run C synthesis"''*Exporting new IP running "''Export RTL"''
*Opening a new Vivado project, selecting RTL project and Bora SOM as the target board
*Adding the new IP in IP list
**Opening "''IP Catalog"''
**Adding repository of the custom IP
The data flows are implemented as AXI streams. The following images show the input and the output to/from the filter respectively. [[File:PYNQ-Custom-IP-AxiS-input.png|thumb|center|600px|Input stream]] [[File:TBDPYNQ-Custom-IP-AxiS-output.png|thumb|center|150px600px|To be completedOutput stream]]