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{{Applies To Bora}}
{{Applies To BoraX}}
{{AppliesToBORA_TN}}
{{AppliesToBORA_Xpress_TN}}
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* clicked ''Run'' on the top bar to run code on a kernel.
The following image shows the noisy and the filtered signals.
[[File:PYNQ-jupyter-FIR-result.png|thumb|center|600px|Input and output signals]]
*Load <code>Overlay</code> and <code>Xlnx</code> modules from <code>pynq</code> and <code>pynq.lib.dma</code>.
*Create <code>Overlay</code> and <code>Xlnk</code> objects
These steps allows you to communicate directly through a DMA buffer.
====Creating and Running a New Custom Overlay: Approach #2====
This approach makes use of a different method to implement the filter. In this case, the filter was written in C++ and implemented by using [https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html Vivado High-Level Synthesis (HLS)]. The fundamental steps required to do this are: *Opening a new Vivado HLS project, selecting Bora SOM as the target board*Creating a new C++ source file*Writing C++ code of FIR custom IP**Creating AXI Stream interfaces for input and output**Defining FIR coefficients and normalizing their values**Using some #pragmas to optimize the execution of the algorithm*Synthesizing new IP running ''Run C synthesis''*Exporting new IP running ''Export RTL''*Opening a new Vivado project, selecting RTL project and Bora SOM as the target board*Adding the new IP in IP list**Opening ''IP Catalog''**Adding repository of the custom IP To complete the procedure and export the Vivado project, the same steps described previously have to be done. The data flows are implemented as AXI streams. The following images show the input and the output to/from the filter respectively. [[File:PYNQ-Custom-IP-AxiS-input.png|thumb|center|600px|Input stream]]
[[File:TBDPYNQ-Custom-IP-AxiS-output.png|thumb|center|600px|To be completedOutput stream]]