To see PYN PYNQ in action, please see [https://www.youtube.com/watch?v=LoLCtSzj9BU this clip].

*U-Boot 2018.1 (at the time of this writing, '''this version was not officially supported by any BELK release yet''')*Linux kernel 4.14.0 (at the time of this writing, '''this version was not officially supported by any BELK release yet''')

This example was inspired by [[http://www.fpgadeveloper.com/2018/03/how-to-accelerate-a-python-function-with-pynq.html|this tutorial]].

[[File:TBDPYNQ-jupyter-welcome.png|thumb|center|600px|captionJupyter Notebook web dashboard]]

[[File:PYNQ-jupyter-start-writing-python.png|thumb|center|600px|Writing Python code]]  * clicked ''Run'' on the top bar to run code on a kernel.  The following image shows the noisy and the filtered signals.  [[File:PYNQ-jupyter-FIR-result.png|thumb|center|600px|Input and output signals]]

We created a custom overlay associated with the hardware implementation of the FIR filter. This first approach made use of the FIR Compiler tool provided by Vivado. The fundamental steps required to do this are:*Opening a new Vivado project, selecting ''RTL project'' and ''Bora SOM'' as the target board*Creating your block design**Adding ''FIR compiler'' block (included in Vivado default IP) and setting it up**Adding ''AXI direct memory access'' block and setting it up**On ''ZYNQ7 Processing System'' block, enabling a ''High-Performance AXI 32b/64b Slave Ports'' on interface HP0**Connecting AXIS_DATA bus of AXI and FIR block**''Runnin Connection Automation'' to complete wiring*Creating Hierarchy of AXI and FIR block named <code>filter</code>*Exporting bitstream file running ''Generate Bitstream''*Exporting block design using Tcl console command <code>write_bd_tcl </path/name>.tcl</code>*Renaming generated files as <code>overlay_name>.bit</code> and <code><overlay_name>.tcl</code>*Creating a folder named <code><overlay_name></code> and inserting generated files*Copying the folder to the target's filesystem in <code>pynq/overlays/</code> direcrtory.

Overlay is ready to use in [[File:PYNQ Python console-jupyter-vivado-filter.png|thumb|center|600px|The resulting design]]

# RUN CUSTOM PYNQ OVERLAY WITH GENERIC DRIVER To access the overlay with the generic driver:*Load <code>Overlay</code> and <code>Xlnx</code> modules from <code>pynq</code> and <code>pynq.lib.dma</ titolo specifico per filtro fir?code>.*Create <code>Overlay</* sezione da approfondire e riscrivere meglio *code> and <code>Xlnk</code> objectsThese steps allows you to communicate directly through a DMA buffer.

/* vedi For more details, please refer to the section [http://www.fpgadeveloper.com/2018/03/how-to-accelerate-a-python-function-with-pynq.html paragrafo "''Hardware FIR Implementation" */''].

To access the overlay with a specific driver:*Import <code>DefaultHierarchy</code> from <code>pynq</code>* sezione da approfondire e riscrivere meglio */create a new class for FIR filter with a method to communicate directly thorough a DMA buffer/* da testare exportazione con diversi setaggi da vivado per create a <code>checkhierarchy *</code> method to check the IP contained under ''filter'' hierarchy

/* vedi For more details, please refer to the section [http://www.fpgadeveloper.com/2018/03/how-to-accelerate-a-python-function-with-pynq.html paragrafo "''Driver for FIR accelerator" */''].

This approach makes use of a different method to implement the filter. In this case, the filter was written in C++ and implemented by using [https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html Vivado High-Level Synthesis (HLS)]. The fundamental steps required to do this are: *Opening a new Vivado HLS project, selecting Bora SOM as the target board*Creating a new C++ source file*Writing C++ code of FIR custom IP**Creating AXI Stream interfaces for input and output**Defining FIR coefficients and normalizing their values**Using some #pragmas to optimize the execution of the algorithm*Synthesizing new IP running ''Run C synthesis''*Exporting new IP running ''Export RTL''*Opening a new Vivado project, selecting RTL project and Bora SOM as the target board*Adding the new IP in IP list**Opening ''IP Catalog''**Adding repository of the custom IP To complete the procedure and export the Vivado project, the same steps described previously have to be done.   The data flows are implemented as AXI streams. The following images show the input and the output to/from the filter respectively.  [[File:PYNQ-Custom-IP-AxiS-input.png|thumb|center|600px|Input stream]] 

# CREATE A NEW BLOCK [[File:PYNQ-Custom-IP FROM C CODE/* sezione da scrivere la prossima settimana */-AxiS-output.png|thumb|center|600px|Output stream]]