Difference between revisions of "BELK-TN-004: Managing both Ethernet ports with U-Boot (BoraEVB/BoraXEVB)"

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== Introduction ==
 
== Introduction ==
 +
This white paper is based on [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB | AN-BELK-006]] and it describes how to access both ETH PHY on Bora SOM and BoraEVB through MDIO interfaces under U-boot. Some changes must be made in U-boot sources in order to enable access to both GEM0 and GEM1 Zynq controllers. For more details please contact TBD
 +
 +
The [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB | AN-BELK-006]] gives access to both ethernet ports only under U-boot. For some reasons the user may want to fully access the net independently through both ETH connection even by the U-boot bootloader.
 +
 +
Below is the block diagram describing the ethernet phy's topology as implemented in the [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB | AN-BELK-006]].
 +
* PHY #1 : is the ethernet PHY on the Bora SOM
 +
* PHY #2 : is the ethernet PHY on the BoraEVB
 +
* PHY #3 : is a dummy PHY implemented in the GMII-to-RGMII bridge IP. It has only one register to correctly set the RGMII bus frequency based on ETH link speed.
 +
 +
 +
[[File:01-BoraEVB-DUAL-ETH.png|thumb|center|600px]]
 +
 +
 +
Following commands shows how to initialize the second ethernet PHY in U-boot and download a file via TFTP:
 +
* at first boot the second ethernet interface is unable to find MAC address, so it must be set as an U-boot environment variable:
 +
<pre>
 +
U-Boot 2014.07-00002-g61aeb00 (Nov 07 2016 - 14:42:16) [belk-3.0.0]
 +
 +
Board:  BORA/BORAX
 +
Environment: SPI Flash
 +
I2C:  ready
 +
DRAM:  ECC disabled 1 GiB
 +
NAND:  1024 MiB
 +
MMC:  zynq_sdhci: 0
 +
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
 +
In:    serial
 +
Out:  serial
 +
Err:  serial
 +
SOM ConfigID not found, using default
 +
SOM UniqueID not found, using default
 +
SOM ConfigID#: ffffffff
 +
SOM UniqueID#: ffffffff:ffffffff
 +
ds2431_readmem(): error in chip reset
 +
ds2431_readmem(): error in reading buffer
 +
ds2431_readmem(): error in chip reset
 +
ds2431_readmem(): error in reading buffer
 +
CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default
 +
CB ConfigID#: ffffffff
 +
CB UniqueID#: 00000000:00000000
 +
Net:  Gem.e000b000, Gem.e000c000
 +
Warning: failed to set MAC address
 +
 +
Hit any key to stop autoboot:  0
 +
zynq-uboot> setenv eth1addr XX:XX:XX:XX:XX:XX
 +
zynq-uboot> saveenv
 +
Saving Environment to SPI Flash...
 +
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
 +
Erasing SPI flash...Writing to SPI flash...done
 +
Valid environment: 1
 +
zynq-uboot> reset
 +
resetting ...
 +
</pre>
 +
* To switch between the two ethernet interfaces the user must be corretly set the ''ethact'' environment variable (this variable is reset to its default at every system reboot):
 +
** To access GEM0 (Bora SOM ethernet phy) : <code>setenv ethact Gem.e000b000</code>
 +
** To access GEM1 (BoraEVB ethernet phy) : <code>setenv ethact Gem.e000c000</code>
 +
 +
If the user want to use the Bora SOM ethernet interface all accesses such as loading a file via TFTP are stright forward.
 +
 +
If the user want to access the net through the BoraEVB ethernet interface, some init commands must be issued. Below this steps are provided:
 +
 +
Issue a net access like ping. This command is used to init the ethernet PHY #2 on the BoraEVB. The ping command fails because the GMII-to-RGMII bridge (PHY #3) is not yet initialized :
 +
<pre>
 +
zynq-uboot> ping 192.168.0.23
 +
Gem.e000c000 Waiting for PHY auto negotiation to complete...... done
 +
Using Gem.e000c000 device
 +
ping failed; host 192.168.0.23 is not alive
 +
</pre>
 +
The two PHY #2 and PHY #3 are now listed and accessed via ''mii'' U-boot command:
 +
<pre>
 +
zynq-uboot> mii info
 +
PHY 0x00: OUI = 0x0885, Model = 0x22, Rev = 0x02, 100baseT, FDX
 +
PHY 0x06: OUI = 0x0885, Model = 0x22, Rev = 0x02, 100baseT, FDX
 +
PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX
 +
</pre>
 +
The last steps implies to correctly configure the GMII-to-RGMII bridge. This IP has an internal dummy MDIO PHY at the ''0x8'' address. Is has only one internal register that is used to set ethernet link speed and consequently the RGMII interface clock frequency. For more detail about the GMII-to-RGMII bridge IP and the internal register please refer to the [https://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v3_0/pg160-gmii-to-rgmii.pdf Product Guide]
 +
 +
Since the ethernet PHY on BoraEVB is configured with auto-negotiation enabled by default, The user must know the link speed negotiated on this interface before setting the GMII-to-RGMII register.
 +
Following are the commands :
 +
** link @ 10M : <code>mii write 0x08 0x10 0x0</code>
 +
** link @ 100M : <code>mii write 0x08 0x10 0x2000</code>
 +
** link @ 1000M : <code>mii write 0x08 0x10 0x40</code>
 +
 +
After the user can access the net via the BoraEVB ethernet:
 +
<pre>
 +
zynq-uboot> ping 192.168.0.23
 +
Using Gem.e000c000 device
 +
host 192.168.0.23 is alive
 +
</pre>

Revision as of 10:49, 8 November 2016

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Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress

History[edit | edit source]

Version Date Notes
1.0.0 November 2016 First public release

Introduction[edit | edit source]

This white paper is based on AN-BELK-006 and it describes how to access both ETH PHY on Bora SOM and BoraEVB through MDIO interfaces under U-boot. Some changes must be made in U-boot sources in order to enable access to both GEM0 and GEM1 Zynq controllers. For more details please contact TBD

The AN-BELK-006 gives access to both ethernet ports only under U-boot. For some reasons the user may want to fully access the net independently through both ETH connection even by the U-boot bootloader.

Below is the block diagram describing the ethernet phy's topology as implemented in the AN-BELK-006.

  • PHY #1 : is the ethernet PHY on the Bora SOM
  • PHY #2 : is the ethernet PHY on the BoraEVB
  • PHY #3 : is a dummy PHY implemented in the GMII-to-RGMII bridge IP. It has only one register to correctly set the RGMII bus frequency based on ETH link speed.


01-BoraEVB-DUAL-ETH.png


Following commands shows how to initialize the second ethernet PHY in U-boot and download a file via TFTP:

  • at first boot the second ethernet interface is unable to find MAC address, so it must be set as an U-boot environment variable:
U-Boot 2014.07-00002-g61aeb00 (Nov 07 2016 - 14:42:16) [belk-3.0.0]

Board:  BORA/BORAX
Environment: SPI Flash
I2C:   ready
DRAM:  ECC disabled 1 GiB
NAND:  1024 MiB
MMC:   zynq_sdhci: 0
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
In:    serial
Out:   serial
Err:   serial
SOM ConfigID not found, using default
SOM UniqueID not found, using default
SOM ConfigID#: ffffffff
SOM UniqueID#: ffffffff:ffffffff
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default
CB ConfigID#: ffffffff
CB UniqueID#: 00000000:00000000
Net:   Gem.e000b000, Gem.e000c000
Warning: failed to set MAC address

Hit any key to stop autoboot:  0
zynq-uboot> setenv eth1addr XX:XX:XX:XX:XX:XX
zynq-uboot> saveenv
Saving Environment to SPI Flash...
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
Erasing SPI flash...Writing to SPI flash...done
Valid environment: 1
zynq-uboot> reset
resetting ...
  • To switch between the two ethernet interfaces the user must be corretly set the ethact environment variable (this variable is reset to its default at every system reboot):
    • To access GEM0 (Bora SOM ethernet phy) : setenv ethact Gem.e000b000
    • To access GEM1 (BoraEVB ethernet phy) : setenv ethact Gem.e000c000

If the user want to use the Bora SOM ethernet interface all accesses such as loading a file via TFTP are stright forward.

If the user want to access the net through the BoraEVB ethernet interface, some init commands must be issued. Below this steps are provided:

Issue a net access like ping. This command is used to init the ethernet PHY #2 on the BoraEVB. The ping command fails because the GMII-to-RGMII bridge (PHY #3) is not yet initialized : 

zynq-uboot> ping 192.168.0.23
Gem.e000c000 Waiting for PHY auto negotiation to complete...... done
Using Gem.e000c000 device
ping failed; host 192.168.0.23 is not alive

The two PHY #2 and PHY #3 are now listed and accessed via mii U-boot command: 

zynq-uboot> mii info
PHY 0x00: OUI = 0x0885, Model = 0x22, Rev = 0x02, 100baseT, FDX
PHY 0x06: OUI = 0x0885, Model = 0x22, Rev = 0x02, 100baseT, FDX
PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

The last steps implies to correctly configure the GMII-to-RGMII bridge. This IP has an internal dummy MDIO PHY at the 0x8 address. Is has only one internal register that is used to set ethernet link speed and consequently the RGMII interface clock frequency. For more detail about the GMII-to-RGMII bridge IP and the internal register please refer to the Product Guide

Since the ethernet PHY on BoraEVB is configured with auto-negotiation enabled by default, The user must know the link speed negotiated on this interface before setting the GMII-to-RGMII register. Following are the commands :

    • link @ 10M : mii write 0x08 0x10 0x0
    • link @ 100M : mii write 0x08 0x10 0x2000
    • link @ 1000M : mii write 0x08 0x10 0x40

After the user can access the net via the BoraEVB ethernet: 

zynq-uboot> ping 192.168.0.23
Using Gem.e000c000 device
host 192.168.0.23 is alive
HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
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