BELK-TN-003: Video processing and hardware/software partitioning

Info Box Applies to Bora Applies to BORA Xpress

History

Version	Date	Notes
1.0.0	June 2016	First public release

Introduction

This white paper describes a video processing system - built upon Bora/BoraEVB - that satisfies specific functional and safety requirements.

From the functional point of view, it is required to (FR denotes a functional requirement):

• [FR1] acquire two independent video streams
• [FR2] mix the input stream and visualize them on a HDMI monitor
• [FR3] visualize informational and statistical data on a 7" LVDS TFT LCD.

Safety requirements (SR for short) are:

• [SR1]FR1 and FR2 must be enabled as quickly as possible upon power-up
• [SR2] once started, video processing chain must keep operating even if software running on PS hangs.

The implementation combines different techniques that are available on Zynq platform to implement a hardware/software partitioning that allows to meet system requirements.

Implementation

The following picture shows a simplified block diagram of the entire system [1].

Concept block diagram of the system without monitoring subsystem

At top level, the natural PS/PL partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization. The following section describes in more detail the actual implementation.

[1] At the time of this writing not all of the shown modules have been completed.

PL subsystem

PL subsystem integrates several functional modules. The video processing chain is described first, as it represents the most important part of it.

Two video sources are supported as per requirement FR1:

• OV7670 camera module (640x480 @ 30fps)
• generic 1280x720 @ 60fps stream over HDMI connection.

Each video source is connected to a specific interface module:

• std res video i/f
  • converts BT656-encoded LVTTL bus into AXI4 stream
  • performs color space conversion (YUV 4:2:2 to 24-bit RGB)
• hi res video i/f
  • converts TMDS differential signals to AXI4 stream.

Video frames encapsulated in AXI4 streams are then stored - by AXI-VDMAs not shown in the picture - in two independent buffers, both implemented on SDRAM bank #1 (this 16-bit wide bank refers to U14 component of BoraXEVB board). Frames are then retrieved by AXI-VDMAs from these buffers and are forwarded to [On-Screen Display LogiCORE IP block] (named video mixer in the diagram) that mixes them. The resulting stream in processed by LCD controller #1 module that converts it to TMDS signals that feed external monitor.

PS subsystem

(for more details see also this white paper)

Notes about SDRAM banks organization

unico banco di ram per riduzione costi ma più fragile