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At top level, the natural PS/PL [2] partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervising and informational data visualization. The following section describes in more detail the actual implementation.
[1] At the time of this writing not all of the shown modules have been completed.
[2]
PS (Processing system): indicates the dual Cortex-A9 block.
PL (Programmable logic): indicates the FPGA fabric, including Logic Cells, DSP modules, BRAMs, clock resources etc.
===PL subsystem===
PL subsystem integrates several functional modules. The video processing chain is described first, as it represents the most important part of it.
