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→Notes about SDRAM banks organization
===Notes about SDRAM banks organization===
The block diagram shows two distinct SDRAM banks. Bank #0 is 32-bit wide and includes memory regions used by FreeRTOS and by Linux. It is also used to implement the frame buffer associated to 7" LCD screen. Bank #1 is 16-bit wide and it is used to implement frame buffer buffers for HDMI screen video chain only. Bank #0 is accessed via Zynq's native DDR memory controller. Bank #1 is accessed via memory controller instantiated in PL and created by [http://www.xilinx.com/products/intellectual-property/mig.html|Memory Interface Generator (MIG)].
SDRAM banks physical separation allows to satisfy requirement [[#SR2|SR2]]: even if native DDR memory controller stops working [1], video processing chain is unaffected because it relies on its own frame buffer.
[1] For example because a misconfiguration caused by a software bug in Linux drivers or by malicious code injected by an attacker.
===Video latency and SDRAM arbitering===
Applications that are based on such a video processing chain, often have a performance requirement in terms of video latency [1]. For this reason the ''latency gauge'' module has been implemented. It is based on a bank of 32-bit 10ns-resolution timers that allows to measure this latency precisely. This bank - that is encapsulated in an IP - is accessible by PS via AXI-Lite bus in order to expose these measurements for offline manipulation and visualization on 7" display.
