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→Notes about SDRAM banks organization
==Notes about SDRAM banks organization==
The block diagram shows two distinct SDRAM banks. Bank #0 is 32-bit wide and includes memory regions used by FreeRTOS and by Linux. It is also used to implement the frame buffer associated to 7" LCD screen. Bank #1 is 16-bit wide and it is used to implement frame buffer for HDMI screen only. Bank #0 is accessed via Zynq's native DDR memory controller. Bank #1 is accessed via memory controller instantiated in PL and created by [[http://www.xilinx.com/products/intellectual-property/mig.html|Memory Interface Generator (MIG)]].
SDRAM banks physical separation allows to satisfy requirement [[#SR2|SR2]]: even if native DDR memory controller stops working - [1], video processing chain is unaffected because it relies on its own frame buffer.
unico banco di ram per riduzione costi ma più fragile
[1] For example because an accidental a misconfiguration caused by a software bug in Linux drivers or by malicious code injected by an attacker.
==Video latency and SDRAM arbitering==
