Bureaucrats, dave_user, Administrators
4,650
edits
Changes
no edit summary
At top level, the natural PS/PL partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning supervising and informational data visualization. The following section describes in more detail the actual implementation.
PL subsystem integrates several functional modules. The video processing chain is described first, as it represents the most important part of it.
*OV7670 camera module (640x480 @ 30fps)
*generic 1280x720 @ 60fps stream over HDMI connection.
**converts TMDS differential signals to AXI4 stream.
Video frames encapsulated in AXI4 streams are then stored - by AXI-VDMAs not shown in the picture - in two independent buffers, both implemented on SDRAM bank #1 (this 16-bit wide bank refers to U14 component of BoraXEVB board). Frames are then retrieved by AXI-VDMAs from these buffers and are forwarded to [[http://www.xilinx.com/products/intellectual-property/ef-di-osd.html|Xilinx On-Screen Display LogiCORE IP block]] (named ''video mixer'' in the diagram) that mixes them. The resulting stream in processed by ''LCD controller #1'' module that converts it to TMDS signals feeding the external monitor.
The ''latency gauge'' module is used to perform video latency measurement. Specifically, it is used to measure the time it takes a frame to traverse the entire video chain, from the input to the output interface.
To satisfy requirement [[#FR1|FR1]], a second controller (''LCD controller #0'' in the diagram) is instantiated. It feeds a 7" LVDS LCD. LVDS signals are generated by the FPGA directly.
===PS subsystem===
At software level, partitioning has been implemented by using the well-known AMP technique combined with SafeG monitor (for more details please see [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this white paper]]). FreeRTOS domain - associated to core #1 - is the first to come up and takes care of video processing chain initialization. Linux domain - associated to core #0 - controls ''LCD controller #0'' to visualize informational data on 7" LCD. It also provides generic connectivity such as TCP/IP networking over Ethernet connection.
TrustZone technology - enabled with the help of SafeG monitor - allows to enforce the partitioning by preventing software running in Linux domain to access video processing chain resources.
unico banco di ram per riduzione costi ma più fragile
[1] For example because an accidental misconfiguration caused by
==Video latency and SDRAM arbitering==
==Future work==
==References==
{{reflist}}
