Difference between revisions of "BELK-TN-003: Video processing and hardware/software partitioning"
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| − | [[File:Bora-dual-video-controller-bd.png|thumb|center| | + | [[File:Bora-dual-video-controller-bd.png|thumb|center|750px|Concept block diagram of the system without monitoring subsystem]] |
At hardware level, the natural PS/PL partitioning has been exploited: the processing video chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization. | At hardware level, the natural PS/PL partitioning has been exploited: the processing video chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization. | ||
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| + | [1] At the time of this writing not all of the shown modules have been completed. | ||
===PL subsystem=== | ===PL subsystem=== | ||
===PS subsystem=== | ===PS subsystem=== | ||
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(for more details see also [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this white paper]]) | (for more details see also [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this white paper]]) | ||
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==References== | ==References== | ||
{{reflist}} | {{reflist}} | ||
Revision as of 10:24, 16 June 2016
Info Box
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History[edit | edit source]
| Version | Date | Notes |
|---|---|---|
| 1.0.0 | June 2016 | First public release |
Introduction[edit | edit source]
This white paper describes a video processing system that has been built upon Bora/BoraEVB. This system has functional and safety requirements that have to be satisfied.
From the functional point of view, it is required to (FR denotes a functional requirement):
- FR1 acquire two independent video streams
- FR2 mix the input stream and visualize them on a HDMI monitor
- FR3 visualize informational and statistical data on an 7" LVDS TFT LCD.
Safety requirements (SR for short) are:
- SR1FR1 and FR2 have to be enabled as quickly as possible upon power-up
- SR1apart from initialization, FR1 and FR2 have to be independent on the execution of the software; in other words, they keep to be satisfied even if software hangs.
The implementation combines different techniques that are available on Zynq platform to implement a hardware/software partitioning that allows to meet system requirements.
Implementation[edit | edit source]
The following picture shows a simplified block diagram of the entire system [1].
At hardware level, the natural PS/PL partitioning has been exploited: the processing video chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization.
[1] At the time of this writing not all of the shown modules have been completed.
PL subsystem[edit | edit source]
PS subsystem[edit | edit source]
(for more details see also this white paper)
