Bureaucrats, dave_user, Administrators
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From the functional point of view, it is required to (FR denotes a functional requirement):
*<span id="FR1">[FR1]</span> acquire two independent video streams
*<span id="FR2">[FR2]</span> mix the input stream streams and visualize them on a HDMI monitor
*<span id="FR3">[FR3]</span> visualize informational and statistical data on a 7" LVDS TFT LCD.
Safety requirements (SR for short) are:
*<span id="SR2">[SR2]</span> once started, video processing chain must be independent from the software running on PS, that is it must keep operating even in case software running on PS hangs.
The implementation combines different techniques that are available on Zynq platform, to implement a hardware/software partitioning scheme meeting these requirements.
==Implementation==
At top level, the natural PS/PL [2] partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervising and informational data visualization. The following section describes in more detail the actual implementation.
[1] At the time of this writing not all of the shown modules have been completed.
[2]
PS (Processing system): indicates the dual Cortex-A9 block.
PL (Programmable logic): indicates the FPGA fabric, including Logic Cells, DSP modules, BRAMs, clock resources etc.
===PL subsystem===
PL subsystem integrates several functional modules. The video processing chain is described first, as it represents the most important part of it.
