Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→Block diagram and Vivado design
[[File:An-belk-005-01.jpg|700px]]
The TFEL display is driven by a controller implemented in PL that fetches pixel data from frame buffer and periodically refreshes physical screen. The LCD controller system is composed of an AXI VDMA IP and a custom version of the LCD controller (derived from [[AN-BELK-004 :_Interfacing_BoraEVB_to_TFT_LCD_display|AN-BELK-004]] LCD controller) itself. AXI VDMA and the LCD controller provides configuration registers that are mapped in the following address range:
*AXI VDMA: 0x43000000 - 0x4300FFFF
*Custom LCD Controller: 0x43C00000 - 0x43C0FFFF
