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To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver. Even if LCD is 18 bpp, each pixel is represented by 32-bit word in memory. In fact each pixel is in RGB666 format, so for each colour only the six most significant bits of the frame buffer RGB888 are used to drive the display.
 
The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]].
===Bora + BoraEVB===
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The Vivado (*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project can be downloaded from this [https://www.dave.eu/system/files/area-riservata/AN-BELK-004-bora-xpr.zip link]signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%).
The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(*BELK/BXELK) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For #Command_line_based_procedure|here]] with the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%).following modifications:*<code>export BASE_NAME bora_LVDS</code>*<code>export U-BOOT_PS7_DIR bora</code>
===BoraLite + Adapter + BoraXEVB===
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The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]] with the following modifications:
**<code>export BASE_NAME boralite_LVDS</code>
**<code>export U-BOOT_PS7_DIR bora</code>
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%). This is a CMOS 2.5V level signal. Make sure that voltage levels of this signal are compatible with LCD backlight input.<br>
(**) On the adapter this signal is routed (via configurable 0R) to multiple pins of the EVB connector to meet all the features of the EVB. Please make sure to configure the Adapter for the use of the LVDS connector.
 
The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]] with the following modifications:
*<code>export BASE_NAME boralite_LVDS</code>
*<code>export U-BOOT_PS7_DIR bora</code>
==== BoraLiteAdapter BLADP0000R0R ====
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The Vivado (*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project can be downloaded from this [https://wwwsignal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%). This is a CMOS 2.dave5V level signal.eu/system/files/area-riservata/AN-BELK-004-Interfacing-to-Make sure that voltage levels of this signal are compatible with LCD-display_0backlight input.zip link]
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For The Vivado project can also be build with the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported procedure explained [[Creating_and_building_example_Vivado_project_(0% and 100%BELK/BXELK). This is a CMOS 2.5V level signal. Make sure that voltage levels of this signal are compatible #Command_line_based_procedure|here]] with LCD backlight input.the following modifications:*<code>export BASE_NAME borax_LVDS</code>*<code>export U-BOOT_PS7_DIR borax</code>
==Enabling frame buffer driver in linux kernel==
 
To enable frame buffer driver user needs to:
* for Bora get the pre-built binaries [https://www.dave.eu/system/files/area-riservata/AN-BELK-004-bora-sw.zip here]
* for BoraLite get the pre-built binaries [https://www.dave.eu/system/files/area-riservata/AN-BELK-004-boralite-sw.zip here] '''TODO''': add binaries
* for BoraX get the pre-built binaries [https://www.dave.eu/system/files/area-riservata/AN-BELK-004-borax-sw.zip here]
 
The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]] with the following modifications:
* For Bora SoM use:
**<code>export BASE_NAME bora_LVDS</code>
**<code>export U-BOOT_PS7_DIR bora</code>
* For BoraLite SoM use:
**<code>export BASE_NAME boralite_LVDS</code>
**<code>export U-BOOT_PS7_DIR bora</code>
* For BoraX SoM use:
**<code>export BASE_NAME borax_LVDS</code>
**<code>export U-BOOT_PS7_DIR borax</code>
U-boot:
Once the kernel has completed boot, frame buffer can be accessed from user space applications via <code>/dev/fb0</code> device file (for more details please refer to https://www.kernel.org/doc/Documentation/fb/framebuffer.txt).
 
=== Pre-built binaries ===
 
* For Bora/BoraLite SoMs use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an004.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora_LVDS_fpga.bin fpga]
* For BoraX SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an004.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_borax_LVDS_fpga.bin fpga]
=== How to install test tools for LCD device ===
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