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→Block diagram and Vivado project
==Block diagram and Vivado project==
The following picture shows pictures show simplified block diagram of the design.
[[File:An-belk-004-01.png|thumb|center|600px|Simplified block diagram of the design (Bora + BoraEVB)]][[File:An-belk-004-borax-01.png|thumb|center|600px|Simplified block diagram of the design (BoraX + BoraXEVB)]][[File:an-belk-004-boralite-01.png|thumb|center|600px|Simplified block diagram of the design (BoraLite + Adapter + BoraXEVB)]]
LCD is driven by a controller implemented in PL that fetches pixel data from frame buffer and periodically refreshes physical screen.
To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver. Even if LCD is 18 bpp, each pixel is represented by 32-bit word in memory. In fact each pixel is in RGB666 format, so for each colour only the six most significant bits of the frame buffer RGB888 are used to drive the display.
===Bora + BoraEVB===
Here is the pinout assignment to drive the LCD:
{| class="wikitable" |
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%).
===BoraLite + Adapter + BoraXEVB===Here is the pinout assignment to drive the LCD:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''LCD Signal'''| align="center" style="background:#f0f0f0;"|'''BORA SOM Signal'''|-| BackLight (*)||IO_L6N_T0_VREF_13 (**)|-| LVDS_CLK_P||IO_L13P_T2_MRCC_13 (**)|-| LVDS_CLK_N||IO_L13N_T2_MRCC_13 (**)|-| LVDS_D0_P||IO_L12P_T1_MRCC_13 (**)|-| LVDS_D0_N||IO_L12N_T1_MRCC_13 (**)|-| LVDS_D1_P||IO_L15P_T2_DQS_13 (**)|-| LVDS_D1_N||IO_L15N_T2_DQS_13 (**)|-| LVDS_D2_P||IO_L11P_T1_SRCC_13 (**)|-| LVDS_D2_N||IO_L11N_T1_SRCC_13 (**)|-|} The Vivado project can be downloaded from this [https://www.dave.eu/system/files/area-riservata/AN-BELK-004-Interfacing-to-LCD-display_0.zip link] '''TODO''': update link (*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%). This is a CMOS 2.5V level signal. Make sure that voltage levels of this signal are compatible with LCD backlight input.<br>(**) On the adapter this signal is routed (via configurable 0R) to multiple pins of the EVB connector to meet all the features of the EVB. Please make sure to configure the Adapter for the use of the LVDS connector. ==== BoraLiteAdapter BLADP0000R0R ==== As the BoraLite SOM has fewer signals routed out as the other SOM, some signal are multiplexed via 0R resistors: the following table list these configurations:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''Reference'''| align="center" style="background:#f0f0f0;"|'''PmodA conn.'''| align="center" style="background:#f0f0f0;"|'''LVDS conn.'''|-| R33 || 0R || DNP|-| R34 || 0R || DNP|-| R35 || 0R || DNP|-| R36 || 0R || DNP|-| R37 || 0R || DNP|-| R38 || 0R || DNP|-| R39 || 0R || DNP|-| R40 || x || DNP|-| R41 || 0R || DNP|-| R42 || x || 0R|-| R43 || DNP || 0R|-| R44 || DNP || 0R|-| R45 || DNP || 0R|-| R46 || DNP || 0R|-| R47 || DNP || 0R|-| R48 || DNP || 0R|-| R49 || DNP || 0R|-| R50 || DNP || 0R|-|} ===BoraX + BoraXEVB===
Here is the pinout assignment to drive the LCD:
{| class="wikitable" |
