Difference between revisions of "BELK-AN-004: Interfacing BoraEVB/BoraXEVB to TFT LCD display"
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==Introduction== | ==Introduction== | ||
| − | This application note describes the interfacing of [[http://www.ampire.com.tw/en/index.asp|Ampire AM-800480STMQW-TA1]] display to BoraEVB. Main characteristics of this TFT LCD panel are: | + | This application note describes the interfacing of [[http://www.ampire.com.tw/en/index.asp|Ampire 7" AM-800480STMQW-TA1]] display to BoraEVB. Main characteristics of this TFT LCD panel are: |
* 800x480 resolution | * 800x480 resolution | ||
* color depth: 18 bpp | * color depth: 18 bpp | ||
Revision as of 07:18, 2 September 2015
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Contents
History[edit | edit source]
| Version | Date | BELK version | Notes |
|---|---|---|---|
| 1.0.0 | 2.2.0 | First release |
Introduction[edit | edit source]
This application note describes the interfacing of [7" AM-800480STMQW-TA1] display to BoraEVB. Main characteristics of this TFT LCD panel are:
- 800x480 resolution
- color depth: 18 bpp
- electrical interface: LVDS (3 pairs).
This project is based on BELK 2.2.0.
Physical interfacing[edit | edit source]
To interface the display a small adapter board is needed. It interfaces J22 connector on BoraEVB side and provides a 20-pin connector to directly attach display cable.
The adapter board
- is also equipped with a linear regulator generating 2.5V. This voltage is used as power supply for the VDDIO_BANK13 rail. This voltage is required to implement LVDS differential pairs that drive display.
- integrates a pad (denoted as TP1) that is used to connect 5V power supply generated by MOD2 PSU of BoraEVB. This additional power rails is required by display backlight circuitry.
The schematics can be downloaded from the following URL:
TBD
Block diagram and Vivado design[edit | edit source]
The following picture shows simplified block diagram of the design.
LCD is driven by a controller implemented in PL that fetches pixel data from frame buffer and periodically refreshes physical screen. The LCD controller is composed of an AXI VDMA IP, the LCD controller itself and a parallel-to-LVDS serializer. AXI VDMA and the LCD controller provides configuration registers that are mapped in the following address range:
- AXI VDMA: 0x43000000 - 0x4300FFFF
- LCD Controller: 0x43C00000 - 0x43C0FFFF
The following picture shows the block diagram of the Vivado project with LCD controller:
To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver. Even if LCD is 18 bpp, each pixel is represented by 32-bit word in memory.
The Vivado design can be downloaded from the following URL:
TBD.
Enabling frame buffer driver in linux kernel[edit | edit source]
To enable frame buffer driver TBD
During kernel bootstrap, the following messages are printed out on console, indicating framebuffer driver has been loaded succesfully:
TBD
Once the kernel has completed boot, frame buffer can be accessed from user space applications via /dev/fb0 device file (for more details please refer to https://www.kernel.org/doc/Documentation/fb/framebuffer.txt).
The following image shows Qt 4.??? demo application running on top of it. TBD
