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→Block diagram and Vivado design
[[File:An-belk-004-01.png|700px]]
LCD is driven by a controller implemented in PL that fetches pixel data from frame buffer and periodically refreshes physical screen. The LCD controller is composed of an AXI VDMA IP, the LCD controller itself and a parallel-to-LVDS serializer.AXI VDMA and the LCD controller provides configuration registers that are mapped in the following address range:TBD* AXI VDMA: 0x43000000 - 0x4300FFFF* LCD Controller: 0x43C00000 - 0x43C0FFFF The following picture shows the block diagram of the Vivado project with LCD controller: [[File:An-belk-004-02.png|800px]]
To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver. Even if LCD is 18 bpp, each pixel is represented by 32-bit word in memory.
