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BELK-AN-003: Interfacing DDR3 SDRAM to PL

200 bytes added, 12:16, 17 October 2018
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{{Applies To Bora}}
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{{WarningMessage|text=This application note was validated against specific versions of the kit only. It may not work with other versions. Supported versions are listed in the ''History'' section.}}
==History==
{| class="wikitable" border="1"
The Vivado example project can be downloaded from the following URL:
[httphttps://www.dave.eu/system/files/area-riservata/AN-BELK-003-bora-AXI-DDR3-BELK-2.1.0_no_results.xpr_.zip AN-BELK-003 Vivado project (without synthesis and implementation results)]
This project requires a 200 MHz clock source. It has been tested with
The bitstream and boot binaries can be downloaded from the following URL:
[httphttps://www.dave.eu/system/files/area-riservata/AN-BELK-003.bitstream-boot-binaries.zip AN-BELK-003 binaries]
==SDRAM bank mapping==
The kernel patch can be downloaded from the following URL:
[httphttps://www.dave.eu/system/files/area-riservata/AN-BELK-003_Add_AXI_DDR3.patch_.zip AN-BELK-003 Linux patch]
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