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{{Applies To Bora}}
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{{WarningMessage|text=This application note was validated against specific versions of the kit only. It may not work with other versions. Supported versions are listed in the ''History'' section.}}
==History==
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==Introduction==
Even if PL can share main SDRAM with PS, several applications need a dedicated bank for FPGA IPs in order to have exclusive access and to maximize bandwidth. In any case, since this additional SDRAM bank is accessible via AXI bus, it is mapped in the processor's memory space and thus it can be accessed by PS as well.
BoraEVB can optionally be populated with a 16-bit 512MB SDRAM chip that is directly connected to PL (1). This application note describes how to enable the support for this additional memory bank. An example Vivado design is released along with this application note, based on BELK 2.1.0 (http://wiki.dave.eu/index.php/[[Bora_Embedded_Linux_Kit_%28BELK%29#BELK_software_components)|BELK 2.1.0]].
The Vivado example project can be downloaded from the following URL:
[https://www.dave.eu/system/files/area-riservata/AN-BELK-003-bora-AXI-DDR3-BELK-2.1.0_no_results.xpr_.zip AN-BELK-003 Vivado project (without synthesis and implementation results)]
This project requires a 200 MHz clock source. It has been tested with
The bitstream and boot binaries can be downloaded from the following URL:
[https://www.dave.eu/system/files/area-riservata/AN-BELK-003.bitstream-boot-binaries.zip AN-BELK-003 binaries]
==SDRAM bank mapping==
The kernel patch can be downloaded from the following URL:
[https://www.dave.eu/system/files/area-riservata/AN-BELK-003_Add_AXI_DDR3.patch_.zip AN-BELK-003 Linux patch]
